DE4442958C2 - Method and circuit arrangement for performing multi-stage butterfly operations - Google Patents

Abstract

In a method for performing multi-stage transformations using butterfly operations, successive stages of the transformation are calculated in a common arithmetic unit for performing butterfly operations in time-division multiplex, the calculation results permuting after the calculation of one stage, fed back into the arithmetic unit via a delay line and one be subjected to a further butterfly operation, the arithmetic unit being used jointly for the partial calculations of the individual stages and the partial calculations of the stages being carried out alternately, and the remaining stages of the transformation being calculated in at least one further arithmetic unit without time multiplexing.

Description

The invention relates to a method and a circuit arrangement for Implementation of multi-level transformations using butterfly operations, such as those B. in the Trans formation coding and decoding, in particular for the discrete cosine Transformation (DCT) can be used.

Technical field

Various block transformation algorithms can be calculated particularly effectively if the calculation is carried out in several stages. The signal flow graph is broken down into smaller, possibly similar subgraphs with two inputs and two outputs, which mostly have the shape of a butterfly and are therefore called butterfly. Butterflies with two entrances and two exits are common. Additions, subtractions and the comparatively complex multiplications are usually required as internal arithmetic operations for the butterflies. In the signal flow graph, several butterflies are required in parallel in each stage. Examples of this are the Fast Fourier Transform (FFT), which is described in detail in "Digital Signal Processing" by AV Oppenheim and RW Schäfer, Engelwood Cliffs: Prentice Hall, 1975, and the Discrete Cosine Transform (DCT) and the inverse DCT (IDCT). Further versions can also be found in:
[N. Ahmed, T. Natarajan & KR Rao: "Discrete Cosine Transform", IEEE transactions on Computer, Vol. C-23, pp. 90-93, Jan. 1974],
[BG Lee: "A New Algorithm to Compute the Discrete Cosine Transform", IEEE transactions on Acoustics, Speed and Signal Processing, Vol. 32, No. 6, pp. 1243-1245, Dec. 1984], y
[A. Artieri, F. Jutand: "Procédé de détermination de transformée en cosinus discrète", certification no. 89 02347, Feb. 1989], [C. Loeffler, A. Lightenberg, GS Moschytz: "Practical Fast 1-D DCT Algorithm with 11 Multiplications", IEEE, pp. 988-991, 1989],
[M. Vetterli, H. Nussbaumer: "Simple FFT and DCT Algorithms with Reduced Number of Operations", Signal Processing, Vol. 6, pp. 267-278, Aug. 1984].

DCT and IDCT are commonly used for data compression of video signals used. The procedures are in the standards JPEG, MPEG, "Information Technology - Coding of Moving Pictures and Associated Audio for Digital Storage Media up to about 1.5 Mbit / s ", Draft International Standard ISO / IEC DIS 11172, 1992. A two-dimensional form of the DCT is used, which in two one-dimensional DCT transformations with a length of 8 separable is.

The problem is also in "Video Codec for Audiovisual Services at p × 64 kbit / s, Recommendation H. 261 ", The International Telegraph and Telephone Consultative Committee (CCITT), 1990 further defined.

In principle, there are several options for implementing signal flow graphs for block transformation algorithms. The entire signal flow graph can be converted directly into hardware, so that each multiplication requires a hard-wired multiplier, each addition an adder and each subtraction a subtractor. Although this procedure leads to extremely high throughput rates, it is comparatively expensive. The other extreme is to perform all operations one after the other in a programmable unit using simple time division multiplexing. An example is given on page 265 of the LSI-Logic data manual (Implementing Fast Fourier Transform Systems with the L64280 / 81 Chipset. Digital Signal Processing (DSP) Databook. Milpitas: LSI Logic, June 1990 , pp. 258-268). This procedure is very flexible and delivers high utilization rates, but leads to low throughput rates.

Often, the possibility is used to adjust the number of butterflies realized via a time multiplex operation to the desired throughput rate. A butterfly is usually assigned to each processing level (LSI-Logic, Databook, page 261, Figure 1 and 2 ). The assignment can take place, for example, via a projection algorithm. In addition to the actual Butterflies, permutation elements are required for operation in order to bring the data into the predefined, chronological order in each stage.

In most cases, however, when designing processing components aimed for a simple system concept, on average with everyone Clock step a date is processed. Each cycle step can also, if necessary  consist of several partial measures. Even synchronously clocked buffers that possibly between several processing units for adapting data formats are required, usually deliver a maximum of one date per measure, provided that they are not divided in a complex manner. That is why butterflies are sometimes used in Time division multiplex used together for several levels. For an optimal out load on the processing units (processors) and therefore one if possible To get low effort, the number of processors must pass through rate can be adjusted.

The complex implementation of multipliers can be minimized by carrying out the transformation with as large a number of multiplications as possible with a fixed coefficient. For example, in the combination of hard-wired add, subtract and shift operations, the effort for a multiplication with a fixed coefficient is considerably lower than for a multiplication with a variable coefficient [K. Hwang: Computer Arithmetic, Principles, Architectures and Design. John Wiley & Sons, 1979) and (P. Pirsch: VLSI Implementation Strategies. In: P. Pirsch (ed.): VLSI Implementations for Image Communications, Elsevier 1993 , p. 67].

With 2 values per cycle step, the Butterflies usually work faster than that Memory and data infeed and outfeed, usually 1 value per clock step need. Corresponding conditions also arise during processing complex numbers such as those required for FFT. Frequently all n levels are processed one after the other. With optimal Data supply via adapted buffers then drops, however, that at n Levels reached throughput rate to 2 / n times the value. For achieving an optimal throughput rate with minimal effort, it is therefore necessary Select the number of butterflies made so that the value n / 2 is the number of corresponds to the values to be processed per cycle step. If the number is odd, n results however, the problem arises that n / 2 is not an integer. The same applies to comparable tasks where the optimal number of butterflies is not is an integer. In all of these cases, implementation is not yet optimal possible.

This applies, for example, to three-stage implemented signal flow graphs for the 8-point DCT too. For example, if only one butterfly Processor worked, so the processing unit is complete in time used, but the throughput rate of memory and overall system is 2/3 of the Maximum value decreased. In contrast, two or three butterfly processors  are used to achieve a throughput rate of one value / clock however, the processors are not fully utilized.

In US Patent 4,821,224 a method and a circuit arrangement for Computation of a Fast Fourier transform described using a variety Butterfly calculation modules arranged in parallel and optionally switchable are. Each butterfly calculation module disadvantageously requires a complex one Multiplier.

US Pat. No. 5,293,330 describes a method for calculating a Fast Fourier Transformation described, in which the transformation is serial one after the other is performed. For this purpose, a large number of butterfly calculation modules are serial connected in series, between the butterfly calculation modules Permutators for controlling the calculation sequences are provided. The serial Implementation of the transformation requires very complex to implement Arithmetic units.

DE 39 00 349 A1 describes a circuit arrangement for real-time implementation described a fast Fourier transformation, in which the two halves one Sequence of complex input words via a series-parallel input register and a buffer to several butterfly operators working in parallel be handed over. In this way, a quasi-parallel calculation of the complex numbers when performing the transformation in series.

The object of the invention was to provide a method and a circuit arrangement Implementation of multi-stage transformations using butterfly operations, in which the Implementation needs, in particular the number of multipliers to be minimal should be an optimal one for an odd number of butterfly levels Utilization of the arithmetic units is achieved.

The object is achieved by the method according to claim 1 in that that successive stages of transformation in a common  Calculator for performing butterfly operations in time division multiplexing the calculation results after the calculation of a stage permuted, fed back into the arithmetic logic unit via a delay line and undergo a further butterfly operation, the arithmetic unit for the Partial calculations of the individual levels are shared and the partial calculations Calculations of the stages are carried out alternately, and that the remaining stages the transformation in at least one other arithmetic unit without time division multiplexing be calculated.

This transforms the transformation so that it is selected and suitable successive stages in time division multiplexing and the remaining stages without Time division multiplex can be calculated. The calculations for the Stages are carried out alternately in the same calculator.

The butterflies in the signal flow graphs for the block transformation algorithms must be chosen so skillfully that the comparatively complex programmable multiplications implemented Need to become.

Accordingly, the circuit arrangement has an arithmetic unit for calculating a Butterfly operation for successive stages of transformation in the Time-division multiplexing, with the arithmetic unit having two inputs and two outputs and one Series-parallel converter an input of the calculator to convert a serial data stream into a parallel data stream and a parallel serial Converter at the output of the calculator to convert the parallel Data stream at the two outputs of the arithmetic unit in a serial Data stream is provided, and that the outputs of the arithmetic unit via a Circuit for permutation and subsequent delay elements on multiplexers are fed back at the two inputs of the arithmetic unit, and that at the serial input or the serial output of the calculator another Calculator for performing a butterfly operation without time division is switched.  

To perform butterfly operations, for example for FFT or DCT, is on the output of the circuit arrangement for calculating several stages in the Time division multiplexing an arithmetic unit for performing butterfly operations and Permutations switched that works without gradual time division multiplexing. For the The inverse transformations are calculated without a step-wise time multiplex working calculator for performing butterfly operations and Permutations upstream of the circuit characterized by time division multiplexing.

With an odd number n, at least one of the butterfly Processing units with fixed or switchable multiplication coefficients  realize. This processing unit is usually at the entrance or exit of the Circuit arranged. It is therefore possible that n - 1 butterfly levels in two times time division multiplex and the remaining stage separately without Time division multiplex is implemented. This will result in the elaborate stages Utilization rate reached 1, while only the first or last one Level of utilization is 0.5. Because the separate stage in general makes up only a fraction of the total effort, so it becomes total utilization degree of almost 1 reached. The same can often be done with others Achieve throughput rates.

drawings

The invention is explained in more detail with reference to the figures. Show it:

Fig. 1: Example of a suitable DCT data flow diagram with three stages

Fig. 2: Mixed multiplex normal operation with optimal use of the butterflies

Fig. 3: Mixed multiplex normal operation for IDCT (with IDCT butterflies)

Fig. 4: permutation circuit

Examples of use

The invention finds z. B. Application for the comparatively regular transformations FFT and IFFT, described in "Digital Signal Processing" (page 293, Figure 6.6 , and page 304, Figure 6.17 ), as well as for some relatively irregular DCT and IDCT implementations such as the signal flow graphs based on Lee's algorithm for the 8-point DCT (N. Demassieux, F. Jutand: "Orthogonal Transforms", in P. Pirsch, "Implementations for Image Communications," Elsevier, 1993, p. 217-250, esp. P. 223, Figure 3 ).

Complex numbers are expected at the FFT. The required operations However, they can also be based on real additions, subtractions and multiplication lead back. The forms of FFT include addition and subtraction in the first or last stage only the multiplication with the value 1 is required in the second or penultimate stage, multiplication with the imaginary number i. Both can be easily implemented without a hardware multiplier. In the The third or third to last level is additionally multiplied by the square  root of 2 is required, which can then be realized with hard-wired multipliers leaves. In this case, removing up to three levels can be worthwhile.

Butterflies can also be found in the DCT of length 8 , which is frequently required for image coding methods, in such a way that the very complex, programmable multipliers are only required in the first two butterfly stages B1 and B2 ( FIG. 1). In the third butterfly stage B3, only a very simple, hard-wired multiplier is required, which multiplies by the square root of 2 (factor 2. P4) or by half the square root of 2 (factor P4). Switching between these two multipliers is therefore very easy. For example, when using the usual dual number system, it only requires a bit-wise shifting of the multiplicands. In addition, a simple correction network K and a scaling Sk are necessary. The correction network contains only simple additions and can therefore be set up comparatively easily. The scaling for the factor P4 / 2 corresponds to a quarter of the square root of 2. If a two-dimensional DCT ( 2 D-DCT) is calculated as for image coding tasks, this scaling is required twice. Due to the principle linearity of the arrangement, the two scaling factors can be combined to a factor of 1/8. This factor corresponds to a power of two and can therefore be implemented in connection with the commonly used number systems with a hard-wired sliding operation without additional hardware.

Overall, in addition to the effort required to implement the Data input and output only hardware for the implementation of the 1st, 2nd and 3rd Butterfly levels with permutation and the correction network required.

It is therefore possible to divide the processing according to the invention in such a way that the first two complex butterfly stages B1 / B2 work in time-division multiplex, but the last, simply constructed butterfly stage B3 is operated directly with the processing cycle ( FIG. 2). The level B3 must also include the correction network necessary for the necessary. For the introduction of time-division multiplexing, only additional synchronous delays D (pipeline stages) and multiplexer M are required to carry out the series / parallel conversion and the parallel / series conversion. If stage 3 is operated in time division multiplexing, the parallel / series conversion is only carried out after this stage ( FIG. 3).

In such a multiplex operation, at least the is expensive built part of the processing unit fully used without the maxi possible throughput rate is reduced. This property enables effizi ent hardware implementations.

With adapted butterflies and reversal of the processing modes, this basic principle can also be applied to IDCT processing ( FIG. 4). In this case, the multiplier used for the Butterfly B1 only needs to be operated with hard-wired coefficients without time multiplex, while the complex units for the Butterflies B2 / B3 are operated in time multiplex. Again, only a few delays D and multiplexers are required for time-division multiplexing.

Between the stages, the data may have to be permuted so that the output data for the next stage are in the correct order at the input of the butterfly stage. The permutation can e.g. B. with the circuit arrangement shown in Fig. 5. However, the arrangement of the memories and multiplexers is dependent on the transformation algorithm and must be adapted to the respective task.

Reference list

D delay element
M multiplexer
B1 first butterfly level
B2 second butterfly level
B3 third butterfly level
PS permutation circuit
P1-P7 weighting factors
K correction network
Sk scaling

Claims (4)

1. A method for performing multi-stage transformations using butterfly operations, characterized in that successive stages of the transformation are calculated in a common arithmetic unit for performing butter fly operations in time multiplex, the calculation results permuting after the calculation of a stage, via a The delay line is fed back into the arithmetic unit and subjected to a further butterfly operation, the arithmetic unit being shared for the partial calculations of the individual stages and the partial calculations of the stages being carried out alternately, and that the remaining stages of the transformation in at least one additional arithmetic unit without Time division multiplex can be calculated. 2. Circuit arrangement for carrying out multi-stage transformations by means of Butterfly operation, characterized by an arithmetic unit for calculating a Butterfly operation for successive stages of transformation in time multiples plex, where the arithmetic unit has two inputs and two outputs and a Seri Parallel converter an input of the arithmetic unit for converting a seri ellen data stream into a parallel data stream and a parallel-series converter  at the output of the arithmetic unit for converting the parallel data stream featured in a serial data stream at the two outputs of the arithmetic unit can be seen, and that the outputs of the arithmetic unit via a circuit to the Per mutation and subsequent delay elements on multiplexers at the two Inputs of the arithmetic unit are fed back, and that to the serial on gear or the serial output of the calculator to another calculator Performing a butterfly operation without time division multiplexing. 3. Circuit arrangement according to claim 2, characterized in that the par allel series converter a delay element at one of the outputs of the Re chenwerkes and a multiplexer, the other output of the arithmetic unit kes and the output of the delay element connected to the multiplexer is. 4. Circuit arrangement according to claim 2 or 3, characterized in that the series-parallel converter has a delay element and a multiplexer each has at the inputs of the arithmetic unit, the serial input to the ver delay element and the one multiplexer and the output of the delay element is connected to the other multiplexer.