GB2132047A - Frequency divider circuits - Google Patents

Abstract

A frequency divider circuit allows a desired long-term output frequency (with acceptable short-term deviations) to be generated from a master crystal oscillating at a higher frequency. A digital monostable divider unit D1 is connected in cascade with another such unit D2 and is supplied with a stable oscillator-controlled frequency input at I. The unit D1 has a period of N cycles, providing the major frequency division component, and the unit D2 provides the desired lower output frequency at O and is controllable for alternative switching after 1 or 3 cycles instead of the normal 2, the sum of the periods (N+2) representing the basic division ratio of the circuit. The output O is connected to the input i of a digital M counter which resets automatically after a count of M, when an output "modify" signal from an output o of the counter is applied at m to the divider unit D2. This signal renders operative a control signal applied to a fast/slow control signal input c1 of the unit D2 so that this unit switches after 1 or 3 cycles, instead of the basic 2, according to the value of the control signal. The M counter is programmable by a programme control signal at c2, so that the value of M can be varied to vary the long-term output frequency. <IMAGE>

Description

SPECIFICATION Frequency divider circuits This invention relates to frequency divider circuits employing digital electronic divider means for the division of a crystal-controlled input frequency.

In many instances, for example in phase-locked loops, an oscillator is required with an accurately controllable output frequency, and with small deviation from a known centre frequency. In these circumstances conventional VCO (voltage-controlled oscillator) phase-locked loops are often too imprecise to be used directly, and frequently a piezoelectric crystal is added to stabilise the centre frequency associated with some means of frequency modification.

The object of the invention is to provide a frequency divider circuit which allows a desired long-term output frequency (with acceptable shortterm deviations) to be generated from a master crystal oscillating at a higher frequency, the output frequency being controllable within a range either side of an intermediate frequency with a high degree of controllability and stability.

According to the invention such a frequency divider circuit employs a digital electronic divider arrangement which normally switches to\provide a basic output frequency derived from a crystalcontrolled frequency input, but which can be controlled by a fast/slow signal input to switch so as to provide an instantaneous modified lower or higher effective division ratio the output pulses of the circuit being applied to a counter which after a predetermined count automatically resets and supplies a "modify" signal pulse which instantaneously renders the fast/slow control signal operative to modify the instantaneous division ratio accordingly.

Preferably the counter is programmable so that the count at which it resets is variable. Although the invention is applicable to digital divider circuit means generally, the circuit conveniently utilises a monostable divider in which case the circuit may employ two separate monostable divider units, the first of which provides the major division component and the second of which provides the output and can be controlled to provide alternative high and low division components. In this case if the first such unit is a . N monostable unit and the second is a t1,2,3 monostable unit, the overall high and low division ratios will be (N+3) and (N+1) respectively and the intermediate ratio (N +2) corresponds to the basic frequency output.The fast/slow control signal may have three operative values, corresponding to switching of the second monostable unit after 1,2 or 3 cycles. However, it is preferred that it should have only alternative "fast" and "slow" values (logic 0 and logic 1), and that the basic unmodified frequency output condition is then achieved by programming the counter to such a high count value that the fast/slow signal is operative so infrequently that it has no significant effect on the long-term output frequency. The same result can be achieved by inhibiting the counter at times when frequency modification is not required. The division component N of the first monostable unit may also be programmable for variation of the basic frequency.

As an alternative to the described use of two monostable divider units, the digital divider arrangement may for example employ a programmable N+(1,20r3) adder followed by a programmable counter providing the output.

The invention will now be further described with reference to the accompanying drawing which illustrates, by way of example and in block diagram form, a preferred embodiment of the invention. The frequency divider circuit illustrated employs two digital monostable divider units D1 and D2 connected in series, D1 being supplied with a stable oscillator-controlled frequency input at I and D2 providing the desired lower ouput frequency at 0.

The unit D1 has a period of of N cycles and the unit D2 is controllable for alternative switching after 1 or 3 cycles instead of the normal 2, the sum of the periods (N+2) representing the basic division ratio of the circuit.

The output 0 is connected to the input i of a digital "M" counter which resets automatically after a count of M, when an output "modify" signal from an output o of the counter is applied atm to the unit D2.

This signal renders operative control signal applied to a fast/slow control input c1 of the unit D2, so that this unit switches after 1 or 3 cycles instead of the basic 2 cycles, according to whether a "fast" or "slow" signal (logic O or logic 1) is applied at c1. The M counter is programmable, by a 16 bit programme control signal applied at c2, so that the value of M can be varied.

When no modification of the basic outputfrequen- cy is required, corresponding to the unit D2 switching after the normal 2 cycles to provide the basic division ratio of (N+2), the M counter is programmed to a large value of M such that whether a fast or a slow control signal is applied has no significant effect on the long-term output frequency. For example, use of a 16 bit number allows a maximum value of M and 216. The value of N may be fixed or may also be programmable when it is desired that the basic centre frequency should be variable.

If a "fast" control signal is applied at c1 the unit D2 switches after one cycle at the instant of termination of each M count, to provide a lower division ratio of (N+1). Conversely, if a "slow" control signal is applied the unit D2 instantaneously switches after 3 cycles and a higher division ratio of (N +3) applies.

Thus the effect of the modify signal from the counter is to instruct the unit D2 to switch after 1 or 3 cycles, rather than the basic 2, dependent upon the setting of the fast/slow signal input. The effect that this has on the long-term output frequency depends on the programmed value of M.

As an alternative to programming a very large value of M when modification of the basic (N+2) division is not desired,the same result can according to a modified embodiment be achieved by inhibiting the M counter. Thus no "modify" signal pulses are produced and the slow/fast signal remains inoperative.

The use of two monostable units D1 and D2 allows a greater degree of freedom of the choice of basic division ratio, as D1 can be a standard unit suitably chosen to provide the desired N for use with the special switchable D2 unit. The programmable nature of the M counter enables the effective long-term output frequency to be continuously varied over a wide range about the basic centre frequency. For example, with the embodiment illustrated a basic output frequency f0 of 64 kH derived from a master crystal of 1.536 MHz can readily be modified within a range of to 00 p.p.m and set to a stability of +100 p.p.m (excluding long-term crystal drift).

Such an input of 1.536 MHz and nominal output at 64 kHz requires that N = 22, giving a basic division ratio of (22 + 2) = 24. If, for example, it is desired to set the long-term output frequency 10 p.p.m. fast of nominal it is necessary to remove 1 output cycle per 100,000 output cycles, which is 24 input cycles per 100,000 output cycles or 1 input cycle per 4167 (approx) output cycles. This can be achieved by setting M = 4167 and the fast/slow control signal to fast, resulting in one output cycle that is short by one input cycle for every 4167 output cycles. Thus the long-term frequency is increased by about 10 p.p.m.

CLAIMS (Filed on 17 Nov83) 1. A frequency divider circuit for generating a desired long-term output frequency (with acceptable short-term deviations) from a master crystal oscillating at a higher frequency, comprising a digital electronic divider arrangement which normally switches to provide a basic output frequency from the crvstal-controlled frequency input but which is switchable by a fast/slow signal input so as to provide an instantaneous modified lower or higher effective division ratio, and a counter to which the output pulses of the circuit are applied and which after a predetermined count automatically resets and supplies a "modify" signal pulse which instantaneously renders the fast/slow control signal operative to modify the instantaneous frequency division ratio accordingly.

2. A frequency divider circuit according to claim 1, wherein the counter is programmable so that the count at which it resets is variable.

3. A frequency divider circuit according to claim 1 or claim 2, wherein the circuit utilises a monostable divider.

4. A frequency divider circuit according to claim 3, wherein the circuit employs two monstable divider units connected in cascade, the first of these units providing the major frequency division component whereas the second thereof provides the circuit output and can be controlled by means of the fast/slow control signal to provide alternative high low frequency division components.

5. Afrequency divider circuit according to claim 4, wherein the first divider unit is programmable to vary the frequency division component provided thereby.

6. A frequency divider circuit according to claim 4 or claim 5, wherein said second monostable divider unit is a s1,2,3 monostable unit.

7. A frequency divider circuit according to claim 6, wherein the fast/slow control signal can have any one of three operative values, corresponding to switching of the second monostable unit after 1,2 or 3 cycles.

8. A frequency divider circuit according to any one of claims 1 to 6, wherein the fast/siow control signal can take one of onlytwo alternative "fast" and "slow" values, and the counter is programmable for a high count value such that the fast/slow signal is rendered operative so infrequently that it has no significant effect on the long-term output frequency when the basic frequency output is required.

9. A frequency divider circuit according to any one of claims 1 to 6, wherein the fast/slow control signal can take one of only two alternative "fast" and "slow" values, and the cunter is inhibited at times when frequency modification is not required.

10. A frequency divider circuit according to any one of claims 1 to 3, wherein the circuit comprises a programmable N+(1,2Or3) adder connected in case cade with a programmable counter providing the circuit output.

11. A frequency divider circuit arranged substantially as herein particularly described with reference to the accompanying drawing.

**WARNING** end of DESC field may overlap start of CLMS **.

Claims (11)

**WARNING** start of CLMS field may overlap end of DESC **. division ratio, as D1 can be a standard unit suitably chosen to provide the desired N for use with the special switchable D2 unit. The programmable nature of the M counter enables the effective long-term output frequency to be continuously varied over a wide range about the basic centre frequency. For example, with the embodiment illustrated a basic output frequency f0 of 64 kH derived from a master crystal of 1.536 MHz can readily be modified within a range of to 00 p.p.m and set to a stability of +100 p.p.m (excluding long-term crystal drift). Such an input of 1.536 MHz and nominal output at 64 kHz requires that N = 22, giving a basic division ratio of (22 + 2) = 24. If, for example, it is desired to set the long-term output frequency 10 p.p.m. fast of nominal it is necessary to remove 1 output cycle per 100,000 output cycles, which is 24 input cycles per 100,000 output cycles or 1 input cycle per 4167 (approx) output cycles. This can be achieved by setting M = 4167 and the fast/slow control signal to fast, resulting in one output cycle that is short by one input cycle for every 4167 output cycles. Thus the long-term frequency is increased by about 10 p.p.m. CLAIMS (Filed on 17 Nov83)

1. A frequency divider circuit for generating a desired long-term output frequency (with acceptable short-term deviations) from a master crystal oscillating at a higher frequency, comprising a digital electronic divider arrangement which normally switches to provide a basic output frequency from the crvstal-controlled frequency input but which is switchable by a fast/slow signal input so as to provide an instantaneous modified lower or higher effective division ratio, and a counter to which the output pulses of the circuit are applied and which after a predetermined count automatically resets and supplies a "modify" signal pulse which instantaneously renders the fast/slow control signal operative to modify the instantaneous frequency division ratio accordingly.

2. A frequency divider circuit according to claim 1, wherein the counter is programmable so that the count at which it resets is variable.

3. A frequency divider circuit according to claim 1 or claim 2, wherein the circuit utilises a monostable divider.

4. A frequency divider circuit according to claim 3, wherein the circuit employs two monstable divider units connected in cascade, the first of these units providing the major frequency division component whereas the second thereof provides the circuit output and can be controlled by means of the fast/slow control signal to provide alternative high low frequency division components.

5. Afrequency divider circuit according to claim 4, wherein the first divider unit is programmable to vary the frequency division component provided thereby.

6. A frequency divider circuit according to claim 4 or claim 5, wherein said second monostable divider unit is a s1,2,3 monostable unit.

7. A frequency divider circuit according to claim 6, wherein the fast/slow control signal can have any one of three operative values, corresponding to switching of the second monostable unit after 1,2 or 3 cycles.

8. A frequency divider circuit according to any one of claims 1 to 6, wherein the fast/siow control signal can take one of onlytwo alternative "fast" and "slow" values, and the counter is programmable for a high count value such that the fast/slow signal is rendered operative so infrequently that it has no significant effect on the long-term output frequency when the basic frequency output is required.

9. A frequency divider circuit according to any one of claims 1 to 6, wherein the fast/slow control signal can take one of only two alternative "fast" and "slow" values, and the cunter is inhibited at times when frequency modification is not required.

10. A frequency divider circuit according to any one of claims 1 to 3, wherein the circuit comprises a programmable N+(1,2Or3) adder connected in case cade with a programmable counter providing the circuit output.

11. A frequency divider circuit arranged substantially as herein particularly described with reference to the accompanying drawing.