GB2131206A - Program control device - Google Patents
Program control device Download PDFInfo
- Publication number
- GB2131206A GB2131206A GB08330431A GB8330431A GB2131206A GB 2131206 A GB2131206 A GB 2131206A GB 08330431 A GB08330431 A GB 08330431A GB 8330431 A GB8330431 A GB 8330431A GB 2131206 A GB2131206 A GB 2131206A
- Authority
- GB
- United Kingdom
- Prior art keywords
- time
- power supply
- minutes
- control
- program
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
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Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B9/00—Safety arrangements
- G05B9/02—Safety arrangements electric
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
- G05B19/0428—Safety, monitoring
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/20—Pc systems
- G05B2219/25—Pc structure of the system
- G05B2219/25381—Restart program at predetermined position, crash recovery after power loss
Abstract
A program control device for controlling apparatus, such as a vulcanizing machine, to perform a predetermined series of operations in timed sequence includes two time counters 2,3, the first of which continues to count and the other of which stops counting but holds its count during a power failure, and a microcomputer 8,9,10 coupled to the counters so that if a power supply failure occurs during said sequence of operations, the control is restarted at the operational step during which the failure occurred and any prolongation of said operational step due to the power failure is minimised. <IMAGE>
Description
SPECIFICATION
Program control device
This invention relates to a program control device for controlling an object or means under control at predetermined respective time points.
There is known a control device which is so adapted that clock pulses of a constant frequency are counted buy a counter to measure time, and a microcomputer is so programed that when the measured time coincides with predetermined established times the apparatus under control is controlled. However, with such control device, if the power supply fails during the time that the microcomputer is prosecuting a program, when the power supply recovers the microcomputer re-starts from the beginning of the prosecution of the program. As a result the control of the apparatus under the control becomes confused, which applies even when the power supply failure lasts for only a very short time.
The confusion of control can be avoided when all of the control equipment, i.e. the microcomputer, the counter and apparatus under control are backed up with batteries as auxiliary power supplies but as batteries of considerably large capacity are necessary it is not a practical solution.
In Japanese specification No. 56-99934 there is disclosed a program control device for controlling valves in a vulcanizing machine. The device includes means for generating pulses in a timed manner, and a counter for counting the pulses and producing a signal dependent upon the counted time. The output signal of the counter is supplied to a program control circuit which compares the signal with predetermined time values and produces an output for operating the valves oftheyulcanizing machine in the required sequence when the signal coincides with each time value. The counter of the control device is arranged so that it does not reset in the event of a power failure and upon recovery of the power supply it starts counting again from the point at which the power was interrupted.By this means the disadvantages mentioned above are avoided and the required operations of the vulcanizing machine are performed in correct sequence. However, the particular step in the machine operation cycle during which the power supply failed becomes
prolonged by the time duration of the power supply failure. This prolongation of a particular operation in the sequence can be a disadvantage especially when the power failure lasts for longer than just a very short time.
The present invention has for its object to provide a program control device which avoids or alleviates the disadvantages of the known devices. In accordance with this object there is provided a program control device for controlling apparatus to perform a
predetermined series of operations in timed sequence, comprising:
first time counting means adapted to start counting time in response to a starting signal and to continue the time counting even during power supply failure;
second time counting means adapted to start counting time in response to said starting signal, and to stop the time counting when power supply fails but maintain the counting time value during the power supply failure;
means for modifying the time value of said second time counting means;
means for inputting a program defining the time steps of said series of operations; and
a microcomputer coupled to the first and second time counting means and to said inputting means to: read in said program and generate a control signal for each of said series of operations when the counted time value of said second time counting means corresponds to each of said time steps; and, upon recovery of the power supply after a power supply failure during execution of said program,
read in again the program from said inputting means,
determine the time step at which the series of operations is to be re-started in response to the read-in program, the time at which the power supply failed given by the counted time value of the second time counting means, and the duration of the power supply failure determined by the difference between the counted time values of said first and second time counting means
control said counting time value modifying means to make the counted time value of the second time counting means correspond with the determined operation re-starting time step, and
generate successively the control signals for said series of operations to be performed after said recovery of the power supply in response to the modified counted time value of the second time counting means corresponding with said time steps.
Afull understanding of the invention will be had from the following detailed description which is given with reference to the accompanying drawings, in which
Figure 1 is a circuit diagram of a control device in accordance with the invention and arranged to control a plurality of latch relays for controlling the operation of a vulcanizing machine;
Figure 2 is a graph showing the outputs of the two time counters plotted against time when a power failure lasting 15.5 minutes occurs at the 15 minute time point; and
Figure 3 is a flow chart illustrating the various steps involved in the operation of the control device.
Hereinafter, the invention will be explained in detail based on the example of an embodiment in which this invention is practiced in a program control device of a vulcanizing machine. In Figure 1, there is shown a clock pulse oscillator 1 which generates clock pulses of a constant frequency.
Counters 2 and 3 count the clock pulses when load terminals thereof are at H level. The load terminal of the counter 2 is directly connected to a latch circuit 4, and the load terminal of the counter 3 is connected to the latch circuit 4 through an AND gate 5. Output of a power supply failure detector 6 is supplied to the
AND gate 5. The power supply failure detector 6 produces an output of H level when the power source circuit is in normal condition, during a power supply failure it produces an output of L level.
Although it is not shown in Figure 1 the clock pulse oscillator 1,the counters 2 and 3, and AND gate 5 and the latch circuit 4 are backed up by battery power supply. Therefore, as long the latch circuit 4 is latching the H level signal, the counter 2 continues the counting even when power supply failed. On the other hand, while the latch circuit 4 is latching the H level signal and the output of the power supply failure detector 6 is of H level, the counter 3 continues to count, but when the output of the power supply failure detector 6 becomes L level the counter 3 stops counting, and holds the then current count value.Therefore, if there is no power supply failure the count values of the counters 2 and 3 will always coincide as indicated by the straight line 20 in
Figure 2 but if there is power supply failure and the supply recovers, the count value of the counter 3 becomes smaller than the count value of the counter 2, as indicated by the stepped line 21 in Figure 2.
The outputs of the two counters are fed to a central processing device 8 of a microcomputer which includes also a ROM 9, and a RAM 10. The central processing device is connected to an external memory device 7, a display and output device 11, an input device 12, a start signal source 16, e.g. the device under control, and latch relays A to E which are controlled. The device 8 is connected also to control inputs of the counters 2 and 3, and the outputs of these counters are supplied additionally to respective display devices 14, 15. The signal from the start source 16 is also supplied to the latching circuit 4 and the output of the clock pulse oscillator is fed to an establishing device 13 the function of which is described later.
Based on the count values of the counters 2 and 3, and established time points established in the external memory device 7, the central processing device 8 provides on-off control for the latch relays A to E which are to be controlled in accordance with the flow chart shown in Figure 3.
Operation will now be explained, firstly with regard to a first example or mode of use and in the case where there is no failure in the power supply.
In response to a start command 30, the central processing device 8 makes an initial establishment 31, and in a step 32 reads in from the external memory device 7 the data determining the manner in which the latch relays A to E are to be controlled with time. Then, when start signal 33 comes from the device under control 16 to the latch circuit 4, the latch circuit 4 supplies H level signals to the load terminals of the counters 2 and 3. The start signal from the device under control 16 is also supplied to the central processing device 8 which reads the start signal 34 and checks the readiness to start at 35, if ready the control commences and if not ready the control is not commenced and a further start signal 33 is awaited. As the power supply has not failed, H level signal is sent out from the power supply failure detector 6, and the counter 3 counts time the same as the counter 2.
When the central processing device 8 commences the control, it judges in a step 36 whether it is to function according to the first example of use or not.
If it is the first example of use in this case, the value of the counter 3 is compared with the value of each of the respective established time points successive
ly, these points being set by the data read during step 32. More specifically, when at 37 the 0 minute of the first established time point coincides with the 0 minute of the value C2 of the counter 3, the latch relays A and B are put ON while latch relays C, D and
E are maintained OFF (stage 38). When at 39 C2 becomes 5 minutes and coincides with the value 5 minutes of the second establishment time point, the latch relay A is put off and the latch relay D is put on (stage 40). Next, when at41 C2 becomes 14.8 minutes, it coincides with the value 14.8 minutes of the third established time point, the latch relay B is put off (stage 42).When at 43 C2 becomes 20 minutes it coincides with the value 20 minutes of the fourth established time point, and the latch relay D is put off, and the latch relay C is put on (stage 44).
When at 45 C2 becomes 30 minutes, it coincides with the value 30 minutes of the fifth established time point and the latch relay C is put off, and the latch relay E is put on. Finally, when at 47 C2 becomes 50 minutes, it coincides with the final time point value 50 minutes, and all of the latch relays A two E are put off, and the counters 2 and 3 and the latch circuit are cleared (stage 48). When the next start signal 33 is supplied, the aforementioned sequence of operations is performed again.
Next, the operation in the case of power supply failure will be explained. It is supposed that the power supply fails after 15 minutes from the start.
The control up to that time is entirely the same as the case of no power failure as described above. Upon power failure counter 2 continues counting, but the counter 3 stops and holds the count of 15 minutes.
Suppose that the power supply recovers at 25.5 minutes from the start. The value C1 of the counter 2 at that time is 25.5 minutes, but the value C2 of the counter 3 is still 15 minutes. Thereafter, the control is recommended, comparing the value C2 of the counter 3 with respective established time points which are the same as for the case of no power supply failure. More specifically after the recovery of the power supply, the central processing device makes again the initial establishment 31 the read-in 32 of the data from the external memory device 7, etc., and judges whether the count value C2 of the counter 3 isO or not (step 37). If C2 did correspond to 0 minutes the control would proceed as normal through stage 38. However, the C2 value corresponds to 15 minutes, and it is judged next at step 50 whether C2 is equal to or below 5 minutes or not. If
C2 did correspond to 5 minutes or less the control would proceed through the timing check 39. As the
C2 value is greater than 5 minutes, it is checked at 51 whether it is equal to or less than 14.8 minutes or not. If it were control would recommence at time check 41. As it is not below 14.8 minutes, it is next judged at step 52 whether C2 is equal to or below 20 minutes or not. As the C2 is below 20 minutes, the control is recommenced at time check 41 so that when C2 becomes 20 minutes, the control proceeds through stages 42-48 in the same manner as in the case of no power supply failure. Even if the power supply failed at a time point otherthan 15 minutes, the control is recommenced from the time point of the interruption as is apparent from the flow chart of
Figure 3.Thus, if the power interruption had occurred at a time between 20 and 30 minutes, a judging step 53 would recognise this to be the case and control would be restarted at time check 45. Similarly, if the interruption had occurred between the fifth and final time point values, ie. between 30 and 50 minutes, a check 54 would be made and result in the control continuing at time check 47. If the failure occurred after the 50 minute time point the control would proceed to stage 48.For the particular example given, the time spacing between the third time point of 14.8 minutes and the fourth time point of 20 minutes is 5.2. minutes if the power supply does not fail between those time points but if the power supply fails during that period as described the time spacing becomes 5.2 + (25.5 - 15) = 15.7 minutes,
The advantages of a control performed in the abovementioned manner are as follows:
(1) The central processing device does not necessarily restart from the first of the established time points when the power supply is recovered.
(2) If control were effected by comparing the value C1 of the counter 2, instead of the value C2 of the counter 3, with the respective established time point, on-off control will be attempted through the latch relays during the period of power supply failure when the object of control can not be controlled.
Thus the control can not be accomplished, and the control becomes executed immediately after the recovery of the power supply. If the aforementioned interruption in supply happens, the time spacing between the third and fourth established time points would become 10.7 minutes (25.5 - 14.8 minutes) and the time spacing between the fourth and fifth ones becomes 4.5 minutes (30 - 25.5 minutes). (The desired controls are 5.2 minutes between the third and the fourth ones and 10 minutes between the fourth and fifth ones). In a control of this kind, the extension of time to some extent may be allowed as the next best method, but a reduction of time is not acceptable.
A second mode or example of use will now be explained. In the case of no power supply failure at all during a control cycle the respective latch relays A to E are controlled in order through stages 38 to 48 just as described for the first example of use when there is no failure of the power supply.
Let it be supposed however that a failure of the power supply occurs as shown in Figure 2. The power supply fails 15 minutes later after the start of control (0.2 minutes after the latch relay B is put off) and 25.5 minutes after the start of power supply recovers. Due to said recovery, the central processing device 8 starts the control operation again, it makes the initial establishment 31, the reading 32 of data from the external memory device 7, and the read-in 34 of the start signal of the latch circuit 4. The control processing device is not operating according to the first example of use and it performs step 60 to judge whether C1 and C2 coincide or not. C1 and C2 will not coincide due to the power interruption, but if they did control would proceed normally with time check 37.
Then, with Cl and C2 not coinciding, the central processing device 8 in a step 61 reads in C2 (in this case it is a count value which is corresponding to 15 minutes) as t1 which represents the time point at which the power supply failure took place. Next, in a step 62 C2 is subtracted from C1 (the time at which the power supply was recovered), and the result is read-in as t2 which represents the duration of power supply failure (10.5 minutes).
Then in a step 63 it is judged whether tl is larger than 5 minutes or smaller. tl is larger than 5 minutes in this particular example and it is judged in a step 64 whether to is larger than 14.8 minutes or smaller. As tl is larger than 14.8 minutes in this case, it is judged in a step 65 whether to is larger than 20 minutes or smaller. As tl in this example is smaller than 20 minutes, it will be known that although the relay B was put off at 14.8 minutes, i.e. at stage 42, the power supply failure took place before the latch relay
C was put on and the relay D was put off at stage 44.
Then the central processing device 8 in a step 66 judges whether C1 (the time point at which the power supply was recovered) exceeds 20 minutes or not. In this case, 20 minutes is already exceeded, and, therefore in a step 67 the count value of the counter 3 is brought forcibly to the count value which corresponds to 20 minutes, and the program is allowed to jump to the judgement step 43 which determines whether C2 has become 20 minutes or not. Thereby, the latch relay C is put on immediately, the latch relay D is putt off, ie stage 43 is reached and the remaining part of the control cycle is executed normally.
If C1 does not exceed 20 minutes at step 66, t2 is added in a step 68 to the count value C2 of the counter 3 and the program is allowed to jump to the judgement step 43 which then determines when C2 has reached 20 minutes. Thereby, when C2 reaches 20 minutes, the latch relay C is put on, the latch relay
D is put off (stage 44) and the normal control program is executed thereafter.
As is apparent from the flow chart of Figure 3, no matter at what time point the power supply fails between the first and final established time points, i.e. 0 minutes and 50 minutes the same procedure is applied. Thus, if the power interruption occurred between 0 and 5 minutes the central processing device 8 would after determining t1 to be less than 5 minutes in step 63 pass to a step 70 to judge whether or not C1 is greater than 5 minutes. If it is the C2 value is made equal to 5 minutes in a step 70 and the control program proceeds to step 39 so that latch relay A is turned off and latch relay D is turned on immediately in stage 40. If on the other hand C1 is not greater than 5 minutes C2 is corrected in a step 72 by adding to it t2 and the control program continues normally at step 39 which judges when C2 reaches a value corresponding to 5 minutes.
Similarly, if the power failure occurred at a time between the second and third established time points i.e. and 14.8 minutes, the central processing device on recovery of the power supply runs through the steps 31-36 and 60-64. After determining t1 to be less than 14.8 minutes it is then determined in a step 73 if C1 is greater than 14.8 minutes. If the answer is yes C2 is made equal to 14.8 in a step 74 and if the answer is no C2 is corrected in a step 75. In either case normal control is recommended through step 41 and stage 42.
From Figure 3 it will be understood also that on recovery of power supply after an interruption between the third and fourth established time points, 14.8 and 30 minutes respectively, the central processing device will determine that the interruption occurred during this period by running through steps 31-36,60-65 and 76, and will then restart the normal control program at step 45 and hence stage 46 after setting C2 equal to 30 minutes orto C2 + t2 in a step 78 or 79, respectively, according to whether or not C1 is greater or less than 30 minutes as judged in a preceding step 77.Furthermore if the power failure occurred between 30 and 50 minutes from the start, i.e. between the fourth and final established time points, upon recovery of the power the control processing device 8 would go through steps 31-36, 60-65 and 76 and would then determine in a step 80 if C1 is greater than 50 so that C2 is set equal to 50 minutes in a step 81 if it is, and is made equal to C2 + t2 in a step 82 if it is not. The adjusted C2 value is used to recommence the normal control program at step 47 and stage 48.
The advantage of the second specific example will now be discussed. The counter 2 continues time count even when the power supply fails but the counter 3 stops counting when the power supply is interrupted. Before what particular established time point the power supply failed is judged based on the count value C2 of the counter 3 and the respective established time points, at the time recovery of the power supply. It is then determined whether the time point of the recovery of the power supply exceeds said established time point or not; if it does exceed said established time point the count value of the counter 3 is changed to said established time point value; and if said established time point is not exceeded the count value of the counter 3 is charged to the value corresponding to the actual time of power recovery.In the latter case confusion will not happen in the control even, of the microcomputer stops due to the power supply failure, since the count value of the counter 3 is changed to the count value of the counter 2 of the time recovery of the power supply. Furthermore, by stopping the counting of the counter 3 at the time of interruption in power supply the following advantage can be provided. Consider the case where a battery backed-up counter is used which continues the counting even when the power supply failed and the count value is compared with respective established time points after the recovery of the power supply. Suppose that the relays A and B are put on for 5 minutes from 0 minutes to 5 minutes, the relays C, D, E remaining off during that time and for 9.8 minutes from 5 minutes to 14.8 minutes the relay A is put off and the relay D is put on.If the power supply fails 3 minutes after 0 minutes and the failure continued for 4 minutes up to seven minutes, at the time of recovery of the power supply it can be arranged that the relay A is put off and the relay D is put on, but as the next control stage is started at 14.8 minutes there is left only 7.8 minutes in spite of the fact that a period of 9.8 minutes is required during which the realy A is to be put off and the relay D is to be put on. On the other hand, according to the method of the present invention, when the power supply is recovered at 7 minutes, the counter 3 is set to 5 minutes, and, therefore, the time period for which relay A is put off and the relay D is put on can be maintained for 9.8 minutes as was programmed initially.
More specifically, the period of time between an established time point and the next established time point will always be equal to or longer than the initially established period of time, even when there happens to be power supply failure, and it can never become shorter. Further, when it does become longer due to a power supply failure, the increment is minimized.
The establishing device 13 shown in Figure lisa device for changing the count value of the counter 3 for example in order to let the control of the object of control to be completed faster of slower. The apparatus can be slowed down if the output signal of the power supply failure detector 6 is made to be L level forcibly under the condition that the microcomputer and the object of control are operating. In this manner, the respective established time points established in the external memory device 7 beforehand can be changed forcibly to arbitrary established time points.Furthermore by displaying the count value C1 of the counter 2 and the count value
C2 of the counter 3 on liquid crystal display devices 14 and 15 which are capable of displaying even during a power supply failure, it may be easily determined at the time of power supply failure, how far the control program has progressed.
The foregoing established time points, the object of control, etc. of the abovementioned embodiment are mere examples, they can be established arbitrarily, and the number of latch relays can be chosen as desired. In addition, in the aforementioned second example of use, t2 is calculated, then it is added to
C2, but C2 could instead be made directly to coincide to C1 in steps 68, 72, 75, 79 and 82. On the other hand although it was explained that both of the first and second examples of use are practices, either one only may be used depending on the case. Further, in place of the external memory device 7, a host computer can be used.
Claims (2)
1. A program control device for controlling apparatus to perform a predetermined series of operations in timed sequence, comprising:
first time counting means adapted to start counting time in response to a starting signal and to continue the time counting even during a power supply failure;
second time counting means adapted to start counting time in response to said starting signal, and to stop the time counting when power supply fails but maintain the counting time value during the power supply failure;
means for modifying the time value of said second time counting means;
means for inputting a program defining the time steps of said series of operations; and
a microcomputer coupled to the first and second time counting means and to said inputting means to: read in said program and generate a control signal for each of said series of operations when the counted time value of said second time counting means corresponds to each of said time steps; and, upon recovery of the power supply after a power supply failure during execution of said program,
read in again the program from said inputting means,
determine the time step at which the series of operations is to be re-started in response to the read-in program, the time at which the power supply failed given by the counted time value of the second time counting means, and the duration of the power supply failure determined by the difference between the counted time values of said first and second time counting means,
control said counted time value modifying means to make the counted time value of the second time counting means correspond with the determined operaton re-starting time step, and
generate successively the control signals for said series of operations to be performed after said recovery of the power supply in response to the modified counted time value of the second time counting means corresponding with said time steps.
2. A program control device substantially as herein described with reference to the accompanying drawings.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP20080282A JPS5990102A (en) | 1982-11-15 | 1982-11-15 | Program controller |
Publications (3)
Publication Number | Publication Date |
---|---|
GB8330431D0 GB8330431D0 (en) | 1983-12-21 |
GB2131206A true GB2131206A (en) | 1984-06-13 |
GB2131206B GB2131206B (en) | 1986-03-12 |
Family
ID=16430429
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB08330431A Expired GB2131206B (en) | 1982-11-15 | 1983-11-15 | Program control device |
Country Status (2)
Country | Link |
---|---|
JP (1) | JPS5990102A (en) |
GB (1) | GB2131206B (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2146458A (en) * | 1983-09-09 | 1985-04-17 | British Telecomm | Improvements in or relating to video player control |
EP1345108A2 (en) | 2002-02-19 | 2003-09-17 | Siemens Aktiengesellschaft | Electrical apparatus with an operational state and an interrupted state, and method for detecting an interruption state |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61133401A (en) * | 1984-11-30 | 1986-06-20 | Hitachi Ltd | Start system of microcomputer control system at power restoration |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5126430A (en) * | 1974-08-29 | 1976-03-04 | Yamatake Honeywell Co Ltd | |
JPS586181B2 (en) * | 1974-12-31 | 1983-02-03 | 富士通株式会社 | Processing method with power failure countermeasures |
JPS5912642Y2 (en) * | 1977-02-28 | 1984-04-16 | 横河電機株式会社 | data processing equipment |
-
1982
- 1982-11-15 JP JP20080282A patent/JPS5990102A/en active Granted
-
1983
- 1983-11-15 GB GB08330431A patent/GB2131206B/en not_active Expired
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2146458A (en) * | 1983-09-09 | 1985-04-17 | British Telecomm | Improvements in or relating to video player control |
EP1345108A2 (en) | 2002-02-19 | 2003-09-17 | Siemens Aktiengesellschaft | Electrical apparatus with an operational state and an interrupted state, and method for detecting an interruption state |
Also Published As
Publication number | Publication date |
---|---|
GB8330431D0 (en) | 1983-12-21 |
GB2131206B (en) | 1986-03-12 |
JPS5990102A (en) | 1984-05-24 |
JPH0348522B2 (en) | 1991-07-24 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PCNP | Patent ceased through non-payment of renewal fee |