JPS5912642Y2 - data processing equipment - Google Patents

data processing equipment

Info

Publication number
JPS5912642Y2
JPS5912642Y2 JP1977023646U JP2364677U JPS5912642Y2 JP S5912642 Y2 JPS5912642 Y2 JP S5912642Y2 JP 1977023646 U JP1977023646 U JP 1977023646U JP 2364677 U JP2364677 U JP 2364677U JP S5912642 Y2 JPS5912642 Y2 JP S5912642Y2
Authority
JP
Japan
Prior art keywords
abnormality
power supply
power
processor
time
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP1977023646U
Other languages
Japanese (ja)
Other versions
JPS53119832U (en
Inventor
忠 畔上
不二夫 菅野
Original Assignee
横河電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 横河電機株式会社 filed Critical 横河電機株式会社
Priority to JP1977023646U priority Critical patent/JPS5912642Y2/en
Publication of JPS53119832U publication Critical patent/JPS53119832U/ja
Application granted granted Critical
Publication of JPS5912642Y2 publication Critical patent/JPS5912642Y2/en
Expired legal-status Critical Current

Links

Description

【考案の詳細な説明】 この考案は人出力装置とプロセッサとの間でデータ転送
を行い、そのプロセッサでデータ処理を行い、その結果
を上記入出力装置に供給するデータ処理装置に関し、特
にそのプロセッサの電源異常に対処する装置に関する。
[Detailed description of the invention] This invention relates to a data processing device that transfers data between a human output device and a processor, processes the data with the processor, and supplies the results to the input/output device, and particularly relates to The present invention relates to a device for dealing with power supply abnormalities.

例えばプロセス制御においてその検出端よりの信号を電
子計算機に取入れてそのデータを処理し、即ち例えば比
例積分演算を行ってその結果を制御信号としてプロセス
に与えるプロセッサを使用したデジタル制御方式が用い
られている。
For example, in process control, a digital control method is used that uses a processor to input the signal from the detection end into an electronic computer and process the data, that is, perform proportional-integral calculations and give the result to the process as a control signal. There is.

このような装置においてその電源が例えば停電になった
場合、従来においてはその停電復1日と共にそのままプ
ロセス制御を継続して行っていた。
In the case of a power outage in such an apparatus, for example, when the power goes out, process control has conventionally continued as soon as one day after the power outage is restored.

しかしながら制御対象によっては例えば第1図に示すよ
うに温度を時間と共に徐々に上昇させた後、比較的急に
上昇させるような温度制御を行う場合に、その比較的急
に温度を上昇する領域内の温度T1になった時点t1に
おいて停電が生じ、その停電によって制御が停止された
ため温度が下り停電が復旧した時点t2には、比較的徐
々に上昇すべきところがある温度T2に降下していたと
する。
However, depending on the control target, for example, when performing temperature control that gradually increases the temperature over time and then raises it relatively suddenly, as shown in Figure 1, within the region where the temperature increases relatively suddenly. Assume that a power outage occurs at time t1 when the temperature reaches T1, and as the power outage causes the control to stop, the temperature drops and by time t2 when the power outage is restored, the temperature has dropped to T2, which should have risen relatively gradually. .

この復旧時点t2よりの制御は、温度T1における・制
御特性と同様な特性の曲線12として制御する場合、或
は温度T2における現曲線11に沿った曲線13として
制御する場合、又はこれ等曲線12. 13ではなく他
の特性により曲線11に近ずける特性とする場合、更に
制御を停止してしまう場合等各種の制御が考えられる。
The control from this restoration time point t2 is carried out as a curve 12 having the same characteristics as the control characteristic at temperature T1, or as a curve 13 along the current curve 11 at temperature T2, or as a curve 12 that is similar to the control characteristic at temperature T1. .. Various types of control can be considered, such as a case where the characteristic approaches the curve 11 by other characteristics instead of 13, a case where the control is further stopped, etc.

従来においてはこのような事を無視してそのまま復旧後
の運転を行っていた。
In the past, such matters were ignored and operation continued after restoration.

しかし停電が比較的長い場合は停電時における状態変化
を考慮しない制御は問題となり、停電時間に応じてもつ
とも好ましい制御特性を取る事が望まれる。
However, if the power outage is relatively long, control that does not take into account the state change during the power outage becomes a problem, and it is desirable to have control characteristics that are desirable depending on the duration of the power outage.

この考案はこのような点よりプロセッサに対する電源の
異常があると、その制御を停止すると共にその異常の間
の時間を計数し、異常がなくなった状態においてこの異
常時間に応じた異常発生時とは異なる制御特性の制御を
行うようにしたものである。
From this point of view, this invention stops the control when there is an abnormality in the power supply to the processor, counts the time during the abnormality, and determines when the abnormality occurred according to the abnormality time when the abnormality has disappeared. It is designed to perform control with different control characteristics.

例えば第2図に示すように制御プロセス対象15との間
で必要なデータを取り又制御信号を供給する入出力装置
16が設けられ、この入出力装置16はプロセッサ17
との間でデータのやり取りを行い、プロセッサ17にお
いて例えば比例積分演算などの必要な処理を行って入出
力装置に制御信号として与え、これにより制御プロセス
対象15を制御することが行われている。
For example, as shown in FIG. 2, an input/output device 16 is provided which receives necessary data from the control process object 15 and supplies control signals.
The processor 17 performs necessary processing, such as proportional-integral calculations, and supplies the resultant signal to the input/output device as a control signal, thereby controlling the control process object 15.

この考案においてはプロセッサ17に対する電源18、
例えば商用電源の異常を電源異常検出器19にて検出し
その異常を検出すると時計回路21を駆動してその異常
の期間を計時させる。
In this invention, a power supply 18 for the processor 17;
For example, an abnormality in the commercial power source is detected by the power abnormality detector 19, and when the abnormality is detected, the clock circuit 21 is driven to time the period of the abnormality.

勿論この時計回路21は電源18とは別の例えば電池に
よって動作される。
Of course, this clock circuit 21 is operated by a battery other than the power supply 18, for example.

電源異常検出器19は例えば第3図に示すように監視さ
れるべき電源18に接続された電源トランス22の二次
側に整流回路23が接続され、その整流出力は比較的容
量の大きいコンデンサ24に供給される。
For example, the power supply abnormality detector 19 has a rectifier circuit 23 connected to the secondary side of a power transformer 22 connected to the power supply 18 to be monitored, as shown in FIG. supplied to

このコンテ゛ンサ24の両端電圧は基準電圧発生回路2
5に与えられ、この基準電圧発生回路25の例えばツエ
ナーダイオード26から得た基準電圧は比較器27の反
転入力端子に供給される。
The voltage across this capacitor 24 is determined by the reference voltage generation circuit 2.
A reference voltage obtained from, for example, a Zener diode 26 of this reference voltage generating circuit 25 is supplied to an inverting input terminal of a comparator 27.

一方電源トランス22の二次側の中点と一端との間にそ
れぞれRCの移相器28, 29が設けられ、これ等移
相器の出力は互に90゜位相がずらされ、又この電源ト
ランス22の二次側の中点と他端との間に同様に移相器
31. 32が設けられ、これ等の移相器31. 32
の出力は互に90゜ずらされる。
On the other hand, RC phase shifters 28 and 29 are provided between the middle point and one end of the secondary side of the power transformer 22, respectively, and the outputs of these phase shifters are shifted in phase by 90 degrees from each other. Similarly, a phase shifter 31. 32 are provided, these phase shifters 31 . 32
The outputs of are shifted by 90° from each other.

従って移相器28, 29, 31, 32より順次位
相が90゜ずれた4相の出力が得られ、これ等が整流回
路33にて整流され、平滑回路34に供給される。
Therefore, four-phase outputs whose phases are sequentially shifted by 90 degrees are obtained from the phase shifters 28, 29, 31, and 32, and these are rectified by a rectifier circuit 33 and supplied to a smoothing circuit 34.

この平滑出力は比較器27の非反転入力端子に供給され
てその反転入力端子の基準電圧と比較される。
This smoothed output is supplied to the non-inverting input terminal of comparator 27 and compared with the reference voltage at its inverting input terminal.

平滑回路34は比較的時定数が小さいものとされる。The smoothing circuit 34 is assumed to have a relatively small time constant.

このように移相器の使用によって多相交流とし、これを
整流しているため平滑回路34の時定数を小さくしても
そのリツプル分が小さなものとなる。
In this way, the phase shifter is used to create a multiphase alternating current, and since this is rectified, even if the time constant of the smoothing circuit 34 is made small, the ripple component becomes small.

よってこの平滑出力が基準電圧発生回路25の基準電圧
に対して僅かでも低下するとこれを誤動作なく検出する
ように構戒する事ができる。
Therefore, if this smoothed output drops even slightly with respect to the reference voltage of the reference voltage generating circuit 25, it can be ensured that this is detected without malfunction.

通常においては基準電圧が小さく、従って比較器27の
出力が高レベルにあるが、停電になると平滑出力が基準
電圧よりすみやかに低くなって比較器27の出力は低レ
ベルになる。
Normally, the reference voltage is small and therefore the output of the comparator 27 is at a high level, but when a power outage occurs, the smoothed output quickly becomes lower than the reference voltage and the output of the comparator 27 becomes a low level.

比較器27には抵抗器35により正帰還が掛けられてい
るため急速に反転が行われ、その出力低レベルによりト
ランジスタ36が駆動されその出力端子37より停電に
なった事、即ち電源の異常が検出される。
Since positive feedback is applied to the comparator 27 by the resistor 35, the inversion is performed rapidly, and the low level of the output drives the transistor 36, and the output terminal 37 indicates that there is a power outage, that is, there is an abnormality in the power supply. Detected.

このように電源異常が検出されると時計回路21におい
ては例えば第4図に示すように端子37よりの検出異常
信号によって単安定マルチバイブレータ38が駆動され
、その出力によりカウンタ39がリセットされ、更に端
子37.まりの異常検出出力はゲート41に与えられ、
これが開かれて発振器42よりのクロツク信号がゲート
41を通じてカウンタ39にて計数される。
When a power supply abnormality is detected in this way, in the clock circuit 21, for example, as shown in FIG. 4, the monostable multivibrator 38 is driven by the detection abnormality signal from the terminal 37, and the counter 39 is reset by its output. Terminal 37. The abnormality detection output of Mari is given to the gate 41,
This is opened and the clock signal from the oscillator 42 is counted by the counter 39 through the gate 41.

これ等単安定マルチバイブレータ38、カウンタ39、
発振器42は電源18と異なる電池43にて動作するよ
うにされ、電源18の異常にかかわらず常に動作するよ
うにされている。
These monostable multivibrator 38, counter 39,
The oscillator 42 is operated by a battery 43 different from the power supply 18, and is always operated regardless of any abnormality in the power supply 18.

第2図の構或において電源異常検出器19より異常が検
出されると割込線躬を通じてプロセッサ17に割込信号
を与え、その時の各種データ等を停電時に記憶が消失す
ることなく、記憶を保持する記憶装置にデータを退避さ
せる等の処理が行われると同時に時計回路21にて計時
が行われる。
In the structure shown in FIG. 2, when an abnormality is detected by the power supply abnormality detector 19, an interrupt signal is given to the processor 17 through the interrupt line, and various data at that time are stored in the memory without being lost in the event of a power outage. At the same time as processing such as saving data to a storage device is performed, the clock circuit 21 measures time.

電源の異常が復旧すると割込信号線劇を通じてプロセッ
サ17に対してこれがその通知されると同時に時計回路
21からその異常の期間を示すデータがプロセッサ17
に与えられる。
When the power supply abnormality is restored, the processor 17 is notified of this through an interrupt signal line, and at the same time data indicating the period of the abnormality is sent to the processor 17 from the clock circuit 21.
given to.

この時の割込動作によってプロセッサ17は先ず時計回
路21からの計時データを判断し、これに基いてどのよ
うなプロセス制御を行うかが決定される。
By the interrupt operation at this time, the processor 17 first judges the clock data from the clock circuit 21, and based on this, it is determined what kind of process control to perform.

この制御はその制御対象によってその電源異常時間及び
異常発生時期に応じてどのような制御特性に基づいた制
御が良いか予め知られており、これ等についてはそのプ
ログラムが記憶されており、これを異常時間、時期によ
り読出して制御するように復旧時における制御プログラ
ムを組んでおけば良い。
For this control, it is known in advance what kind of control characteristics should be used depending on the power supply abnormality time and abnormality occurrence time depending on the control target, and programs for these are stored and can be used. It is sufficient to create a control program at the time of recovery so as to read and control the abnormality time and period.

以上述べたようにこの考案によるデータ処理装置によれ
ばその電源が異常になった場合にその異常復旧時におい
てそのもつとも好ましい制御が、その異常時間に対応し
て行われる。
As described above, according to the data processing apparatus according to the present invention, when the power supply becomes abnormal, the most preferable control is performed at the time of recovery from the abnormality in accordance with the abnormality time.

従って電源異常時間に応じてプロセスが変化するような
場合の制御に対してこの考案は極めて有効であり、特に
比較的短かい停電は時々発生する事であり、そのような
短かい時間においてもプロセス変化が生じるような場合
に有効であって、その場合そのような短時間の異常を迅
速に検出するためには第3図に示した異常検出器が好ま
しい。
Therefore, this idea is extremely effective for control when processes change depending on the duration of a power outage.In particular, relatively short power outages occasionally occur, and even during such short periods, processes may change. The abnormality detector shown in FIG. 3 is preferable in order to be effective when a change occurs, and to quickly detect such a short-term abnormality.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は温度制御プログラムの例を示す図、第2図はこ
の考案にょるテ゛一夕処理装置の一例を示すブロック図
、第3図は電源異常検出器の一例を示す接続図、第4図
は時計回路の例を示すブロック図である。 15・・・・・・制御対象、16・・曲入出カ装置、1
7・・曲プロセッサ、18・・曲商用電源、19・・間
電源異常検出器、21・・・・・・時計回路。
Fig. 1 is a diagram showing an example of a temperature control program, Fig. 2 is a block diagram showing an example of an instantaneous processing device according to this invention, Fig. 3 is a connection diagram showing an example of a power abnormality detector, and Fig. 4 is a diagram showing an example of a power supply abnormality detector. The figure is a block diagram showing an example of a clock circuit. 15...Controlled object, 16...Music input/output device, 1
7... Song processor, 18... Song commercial power supply, 19... Power supply abnormality detector, 21... Clock circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 制御対象からの測定値をプロセッサに取り込み、このプ
ロセッサでデータ処理を行ない、そのテ゛一夕処理結果
に対応して上記制御対象を制御するようにした制御用の
テ゛一夕処理装置において、上記データ処理装置には上
記プロセッサに対する電源に異常が発生した時に、この
電源異常発生時刻及び電源異常継続時間の少なくとも一
方に対応して選択され実行される上記電源の正常時に実
行される制御手順とは異なる少なくとも一つの異常制御
手順が保持記憶され、上記プロセッサに対する電源の異
常を検出する電源異常検出器が上記電源に接続配設され
、この電源異常検出器の出力により動作した上記電源が
異常状態にある継続時間及び上記電源の異常状態の発生
時刻の少なくとも一方を計時データとして供給する時計
回路が上記電源異常検出器に接続配設され、上記電源の
異常状態の終了後に上記時計回路により供給される計時
データがデータ入力手段によって上記プロセッサに入力
され、その入力された上記計時データに基き、対応する
電源異常状態に応じた上記異常制御手順が選択実行手段
により選択されて実行されるように構或されてなること
を特徴とするテ゛一夕処理装置。
In an instantaneous processing device for control, the measured value from the controlled object is taken into a processor, the data is processed by this processor, and the aforementioned controlled object is controlled in accordance with the result of the instantaneous processing. When an abnormality occurs in the power supply to the processor, the processing device has a control procedure that is selected and executed in response to at least one of the time when the power supply abnormality occurs and the duration of the power abnormality, which is different from the control procedure executed when the power supply is normal. At least one abnormality control procedure is retained and stored, and a power abnormality detector for detecting an abnormality in the power supply to the processor is connected to the power supply, and the power supply operated by the output of the power abnormality detector is in an abnormal state. A clock circuit that supplies at least one of the duration time and the time of occurrence of the abnormal state of the power source as time measurement data is connected to the power abnormality detector, and the time is supplied by the clock circuit after the abnormal state of the power source ends. Data is input to the processor by the data input means, and based on the input clock data, the abnormality control procedure corresponding to the corresponding power abnormality state is selected and executed by the selection execution means. An overnight processing device characterized by:
JP1977023646U 1977-02-28 1977-02-28 data processing equipment Expired JPS5912642Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1977023646U JPS5912642Y2 (en) 1977-02-28 1977-02-28 data processing equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1977023646U JPS5912642Y2 (en) 1977-02-28 1977-02-28 data processing equipment

Publications (2)

Publication Number Publication Date
JPS53119832U JPS53119832U (en) 1978-09-22
JPS5912642Y2 true JPS5912642Y2 (en) 1984-04-16

Family

ID=28860639

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1977023646U Expired JPS5912642Y2 (en) 1977-02-28 1977-02-28 data processing equipment

Country Status (1)

Country Link
JP (1) JPS5912642Y2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57199001A (en) * 1981-06-01 1982-12-06 Nippon Denso Co Ltd Detecting circuit of starter signal
JPS5990102A (en) * 1982-11-15 1984-05-24 Sumitomo Rubber Ind Ltd Program controller

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5086936A (en) * 1973-12-01 1975-07-12
JPS50147253A (en) * 1974-05-15 1975-11-26
JPS512365A (en) * 1974-06-14 1976-01-09 Nippon Electric Co
JPS5126430A (en) * 1974-08-29 1976-03-04 Yamatake Honeywell Co Ltd
JPS5178953A (en) * 1974-12-31 1976-07-09 Fujitsu Ltd Dengenshogaijini okeru shorihoshiki

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5086936A (en) * 1973-12-01 1975-07-12
JPS50147253A (en) * 1974-05-15 1975-11-26
JPS512365A (en) * 1974-06-14 1976-01-09 Nippon Electric Co
JPS5126430A (en) * 1974-08-29 1976-03-04 Yamatake Honeywell Co Ltd
JPS5178953A (en) * 1974-12-31 1976-07-09 Fujitsu Ltd Dengenshogaijini okeru shorihoshiki

Also Published As

Publication number Publication date
JPS53119832U (en) 1978-09-22

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