GB2129242A

GB2129242A - A modular and demodulator apparatus

Info

Publication number: GB2129242A
Application number: GB08320338A
Authority: GB
Inventors: Gayle Russell Norberg; Dennis Michael Petrich
Original assignee: Control Data Corp
Current assignee: Control Data Corp
Priority date: 1980-03-10
Filing date: 1983-07-28
Publication date: 1984-05-10
Also published as: FR2477810B1; GB2071943B; GB2129242B; GB2071943A; GB8320338D0; AU6793681A; FR2477810A1; DE3108809C2; AU538426B2; DE3108809A1

Abstract

A modulator and demodulator apparatus comprises: a modulator consisting of an oscillator 202 for producing a pilot signal, a first pulse phase detector 200, e.g. an edge- triggered D-type flip-flop, with a first input directly connected to the output of the oscillator 202 and a second input connected thereto over a first variable delay device 210, 216, a first filter 214 connected to the output of the detector 200 and having an output connected to control the delay 210, 216, a signal to be modulated 218 being added to the delay control signal and a half-cycle one-shot flip-flop 212 connected with the output of the delay device 210 and providing the phase modulated output; and a demodulator consisting of a similar loop, without output flip- flop 212, with a filter (228, Fig. 10) of different characteristic from first filter (214) and an output which provides the demodulated output signal. The modulated input is applied over the variable delay (226, 230) to phase detector (220), the other input of which receives the pilot signal. <IMAGE>

Description

1 GB 2 129 242 A 1

SPECIFICATION A modulator and demodulator apparatus

This invention relates to a modulator and demodulator apparatus.

According to the present invention there is provided a modulator and demodulator apparatus comprising: a modulator consisting of an oscillator for producing a pilot signal, a first pulse edge detector means for detecting the edge of an input pulse and having a first and second input and having at least one input which is indicative of a pulse edge, said first input being connected to the output of said oscillator, a first variable delay device connected to the output of the oscillator and having an output connected to the second input of said first edge detector means, said first variable delay device having the characteristic of varying the delay time of signal transmission therethrough in response to a first control signal, first control means for said first variable delay device for producing the first control signal, a first filter having a filter characteristic connected to the output of said first edge detector means and having an output connected to said first control means, so that a signal to be modulated is added to the input signal to said first control means for said first filter, and a half cycle one shot flip-flop means connectd with the output of said first variable delay device and having, as its output, the output 95 signal of said modulator; and a demodulator consisting of a second pulse edge detector means for detecting the edge of an input pulse and having a first and second input and having at least one input which is indicative of a pulse edge said 100 first input being connected to receive said pilot signal from the modulator, a second variable delay device connected to receive the output signal of said modulator and having an output connected to the second input of said second pulse edge detector means, said second variable delay device having the characteristic of varying the delay time of saignal transmission therethrough in response to a second control signal, control means for said variable delay device for producing the second control signal, a second filter having a filter characteristic different from the filter characteristic of said first filter connected with the output of said second edge detector means and having an output connected 115 to said second control means, the output of said second filter being a demodulated output signal.

The invention is illustrated, merely by way of example, in the accompanying drawings, in which:

Figure 1 is a circuit diagram of a time differential delay meter having a delay lock loop according to the present invention; Figure 2 is a time domain waveform diagram showing the operation of the delay lock loop of 125 Figure 1, Figure 3 is a circuit diagram of a self-adjusting phase equaliser according to the present invention; Figure 4 is a circuit diagram of a self-adjusting delay device according to the present invention; Figure 5 is a circuit diagram of a single input frequency dependent demodulator according to the present invention; Figure 6 is a circuit diagram of a dual input frequency dependent demodulator according to the present invention; Figure 7 is another embodiment of a delay lock loop according to the present invention in which a digital feedback controls operation; Figure 8 is a graph showing the phasefrequency characteristics of a delay lock loop according to the present invention; Figure 9 is a circuit diagram of a phase modulator of a modulator and demodualtor apparatus according to the present invention; and Figure 10 is a circuit diagram of a phase demodulator of the modulator and demodulator apparatus of Figure 9. 85 Referring now to Figure 1, there is illustrated a time differential meter 10 having a delay lock loop according to the present invention. A first (or A) input 12 and a second (or B) input 14 are provided. The input 12 is connected to a differential amplifier 16 which shapes the input pulse to that it has a smooth characteristic and dose not cause false activation. A second amplifier 18 is provided in association with a transmission line 20 of a predetermined length so that a pulse travelling through the line 20 has a predetermined time delay. Any other fixed time delay device may be used in place of the transmission line 20. The line 20 is also labelled "line A" in Figure 1. The line 20 is connected to a first or data input of a D- type flip-f lop 22 which forms an edge transition detection device and acts in a way analogous to a phase detector although it is not identical to a phase detector. The flip-flop 22 is also an edge transition flip-flop and the sawtooth symbol on the f lip-f lop is used to indicate that as a matter of standard symbol notation. It is possible to arrange that the delay lock loop of Figure 1 operates on the leading edges of both A and B pulse trains or on the trailing edge of both pulse trains or on the leading edge of one pulse train with respect to the trailing edge of the other pulse train.

The input 14 is connected to a differential amplifier 24 which provides pulse shaping a smooth for the B pulse train. The output of the differential amplifier 24 is connected to a variable delay device 26 which has an output through a fixed length transmission line 28, also labelled "line B" in Figure 1. The line 28 is connected to a second or clock input of the flip-f lop 22. The line 28 should be of a slightly different length than line 20. Outputs 30, 32 corresponding to the respective states of the flip-f lop 22 are connected to a voltage divider network composed of resistors 34, 36 from which a single voltage output 38 is derived at a centre tap thereof. Resistors 40, 42 provide termination for the flipflop 22. A feedback loop is connected from the output 38 by way of a line 44 through an 2 GB 2 129 242 A 2 elementary filter 46 to a line 55 and then to the centre tap between a pair of resistors 48, 50. The filter 46 is merely provided to ensure that the line 44 has a direct current voltage thereon without various voltage spikes caused by switching of the flip-flop 22.

The resistor 50 is connected through a variable resistor 52 to a bus 54 which provides a fixed voltage reference to the second amplifier 18 and to both the differential amplifiers 16, 24. Another elementary filter 56 is provided with respect to the bus 54 to ensure that only direct current is present. The resistor 48 is connected to an input of vadable delay device 26 and, in combination with a capacitor 58, constitutes a filter.

A device 60 receives a first input from the line 44 and a second input from the bus 54. The output of the device 60 is used to drive a first switch 62 and a second switch 64. The switch 62 controls a light emitting diode 66 while the switch 64 controls a light emitting diode 68. The device 60 controls the switch 62 in its one state or condition and the switch 64 in its other state or condition, and the input emitting diodes thus provide an indication of which state or condition device 60 is in.

The operation of the circuit illustrated in Figure 1 will now be explained. The negative transition of A and B pulse trains at inputs 12, 14 respectively are measured and presented as a direct current voltage output at a pair of terminations 70, 72 for measurement purposes. The variable resistor 52 is used to adjust the calibration of the output so that the phase difference between the A and B pulse trains may be directly measured in time units. Naturally, the output may be displayed on an oscilloscope for example.

The differential amplifiers 16, 24 shape the A and B pulse trains to a smooth shape for measurement purposes and control purposes of the flip-flop 22 and also transform the voltage reference to that reference voltage appropriate to the circuit. This reference voltage is derived from the reference voltage on the bus 54.

In the A channel the second amplifier 18 in combination with the transmission line 20 simply introduces a constant delay in the A pulse train provided to the data input of the flip-flop 22 so that the adjustment of the delay or reference of the delay through the B channel in the circuit may 115 be both positive and negative. Without a fixed delay in the A channel, delay measurement could not be bilateral. If adjustment in only one direction was desired, this fixed delay would be eliminated.

Referring now to the signal in the B channel as 120 applied to the variable delay device 26, the feedback voltage developed by the flip-flop 22 is provided to an inverting input 73 of the variable delay device and then is connected to the clock input of the flip-flop 22.

The negative going edge of the pulses of the B pulse train at the clock input to the D-type flipflop 22 causes the pulses of the A pulse train to be clocked into the flip-f lop 22. A capacitor 74 is connected between reference ground potential and the line 28 and is adjusted to calibrate the circuit so that there is zero output when the A and B pulse trains have zero phase difference. The flipflop 22 has a Q and a Zi or not Q output previously referred to as outputs 30, 32 respectively. The feedback voltage on the line 55 is developed by the toggling, or switching, of the Q and not Q outputs of the flip-flop 22. The unfiltered voltage on the line 44 which is filtered by the filter 46 provides a variable voltage on the line 55 which controls the threshold level at which the variable delay device 26 output toggles or switches with respect to the input level on the positive input of the variable delay device. The amount of time delay in a signal passing through the variable delay device 26 is equal and opposite in magnitude to the delay between edge transitions of the A and B pulse trains. The amount of delay change through the variable delay device 26 is dependent on the input reference level thereof, the slope of the input transition and the amount of difference between the voltage Vbb and the voltage on the line 55.

The delay control circuit formed by the variable go delay device 26 and the flip-flop 22 causes the feedback voltage on the line 44 to go low when the not Q output 32 is low. A "low" output on the output 32 indicates the clock input of the flip-flop 22 was early with respect to the data input to the flip-flop 22. The going low transition voltage feedback to the variable delay device 26 causes the delay therethrough to increase. This increase in voltage, if sufficient, will delay the clock signal enough to cause the clock input to fall behind the data input at the variable delay device 26, thus setting the not Q output 32 of the flip-flop 22 to a high output. A "high" output at the output 32 will cause feedback to the variable delay device 26 and decrease the clock signal path delay time.

The average value of the filtered feedback on the line 55 provided to the variable delay device 26 is dependent on the amount of time the not Q output 32 of the D-type flip-f lop 22 is in the high state and in the low state. The maximum change in voltage for the filtered feedback is the ratio of the resistance value of the resistor 34 to the resistance value of the resistor 36. The resistor 34 and the resistor 36 limit the feedback voltage swing caused by the flip-flop 22 to be the linear portion of the input transition voltage level to the variable delay device 26 and to prevent latch-up or locking up of the flip-f lop 22 if the input to channel A is removed. Reference should also be had to Figure 8 for further understanding of this operation.

The feedback voltage on the line 44 is filtered first by the filter 46 and also by the filter constituted by the resistor 48 and the capacitor 58 to smooth the switching transitions of the output voltage of the flip-f lop 22 to provide a direct current level to the inverting input of the variable delay device 26. The time constant of these filters determines the lowest repetition rate which can be compared in A and B pulse trains.

The filter time constant also determines the speed S X 7 3 GB 2 129 242 A 3 at which a measurement output can be accurately determined. Obviously, these filters will be constructed to provide as fast a response time as is desirable which is consistent with providing a sufficiently filtered direct current level so that the delay lock loop operates properly.

The light emitting diodes 66, 68 are controlled by the device 60. The device 60 compares the unfiltered feedback level from the line 44 ahead of the filter 46 with the reference voltage level on 75 the bus 54 which is provided at the inverting input thereof. If the feedback voltage level is more positive than the reference voltage level, then this is an indication that the f lip-f lop 22 feedback is acting to decrease the delay through the variable 80 delay device 26 because the B channel input signal is arriving later than the A channel input signal. This condition will light the "long" light emitting diode 68 while the opposite condition will light the "short" light emitting diode 66.

If the flip-flop 22 and the variable delay device 26 combination is able to correct for differences in phase or more correctly in terms of the present invention, time differential, between the A and B channel inputs, both the light emitting diodes 66, 90 68 will be on indicating that the time differential delay meter is locked on the input signal and that a measurement is available at the output terminal 70, 72. When the time differential between the A and B channels is greater than the range of the circuit, then the long or short light will remain on while the other light will remain off. This is an indication that no output can accurately be derived. The lighting of only one signal light indicates phase difference between the A and B 100 channels is greater than the range of the time differential delay meter.

The resistor 50 and the variable resistor 52 constitute a voltage divider circuit which can be used to calibrate the output of the time differential delay meter to provide a convenient relationship between time intervals and voltage intervals. The ratio of the resistance value of the resistor 50 to the resistance value of the resistor 52 is a function of the transition time of the variable delay device 26 and the number of individual feedback controlled circuits in the B channel. For example, the circuit may be designed to show the relationship of one picosecond to 0.1 mV. Thus, the time differential delay meter may 115 be calibrated to that relationship.

Referring now to Figure 2, the waveforms are shown in the time domain and are labelled with respect to Figure 1. Figure 2 is self-explanatory showing the operation of the time differential delay meter in response to edge transitions on pulses in the A and B channels to provide increasing or decreasing delays through the variable delay device 26.

Referring now to Figure 3, a self-adjusting phase equaliser according to the present invention is shown. A clock input signal is received at input 100 and is provided to the data input of an edge transition flip-flop 102 similar to 65 that of the D-type flip-flop 22 shown in Figure 1. 130 The feedback output of the flip-flop 102 is passed through a filter 104 to a pair of delay control devices 106, 108 of the same type as the variable delay device 26 shown in Figure 1. The delay control device 106 controls a variable delay in a transmission path 110 while the delay control device 108 controls a variable delay in a transmission path 112. The clock input signal is connected through the path 112 through a fanout or feedback network 114 to the various operating or working ranks at various locations in a computer. This is represented generally by box 116. Time related feedback from individual working ranks is provided through a transmission line of exactly the same length to have the same time delay as the time delay through the transmission lines on the feedback network 114 in providing the clock signals to the working ranks of the computer. A feedback signal is provided to the path and provides the clock input to the flipflop 102.

The self-adjusting phase equaliser of Figure 3 uses the flip-flop 102 in a way analogous to a phase detector. Phase shift from a clock input signal to various individual working ranks in a computer undergo phase shift if the basic clock frequency changes in a high clock rate computer system. Clock frequency changes are made in order to test the clock frequency margins of the computer with respect to the individual working ranks of the computer which are controlled by a master clock oscillator. The self-adjusting phase equaliser of Figure 3 corrects for all oscillator frequency changes within the operating range of the variable delay transmission paths. Phase shifts as detected at the working rank 116 due to changes in the clock time delay through the feedback network 114 are significantly reduced. Both the clock delay in the feedback network and in the transmission paths are variable. A correcting voltage generated by the flip-flop 102 as passed through the filter 104 changes the time delay in both delay control devices 106, 108 to maintain a constant phase relationship in all clock circuits.

Referring now to Figure 4, a self-adjusting delay device 120 according to the present invention is shown. An edge detection flip-flop 122 receives a clock input signal on a data input channel. The voltage related output is passed through a line 124 to a filter 126 to provide a direct current to a delay control device 128. The clock input signal is connected through a variable delay channel 130 controlled by the delay control device 128 to a fan-out system 132 for a computer clock control system. The working rank of the computer is indicated by reference numeral 134. Feedback from the working rank is provided through an equal time delay channel to the clock input of the flip-flop 122. The delay lock loop of Figure 4 forms a self-adjusting delay device for deskewing the clock fan- out in a computer system. Clock fan-out skew can occur due to integrated circuit chip ageing, replacement of chips, replacement of circuit boards, changes in 4 GB 2 129 242 A 4 cabling, and other factors relating to ageing and operation of the computer system. The selfadjusting delay device shown in Figure 4 can correct for all phase differences within the range of the variable delay channel 130 and can also compensate for changes in clock frequency. The flip-flop 122 provides a correction signal voltage which is filtered by the filter 126 and connected to the delay control device 128. The correction voltage occurs if the signal phase at the data and clock inputs of the flip-flop 122 are not equal. If there is a phase difference the delay control device 128 corrects the delay by adjusting the variable delay channel 130 until the phase at inputs to the flip-flop 122 are equal. Because the working rank 134 is halfway between the delay control device 128 and the flip-fiop 122, clock frequency changes in phase are reduced by a factor of 2.

Referring now to Figure 5, a single input 85 frequency dependent demodulator 140 according to the present invention is shown. An input signal on a line 142 is provided to a data input A of an edge transition flip-flop 144 which produces an output correction voltage on a line 146 which is passed through a filter 148. The input signal on the line 142 is also passed through a fixed delay device 150 which may be simply a length of transmission cable to a variable delay channel 152 and finally to a clock input B of the flip-flop 144. A delay control device 154 controls the operation of variable delay channel 152 and is controlled by the voltage output from the filter 148. An output from the filter 148 is provided as the output of the demodulator in which phase shifts in the input signal on the line 142 and have been converted to amplitude shifts in the filtered signal for amplification or measurement. These phase shifts are created artificially by the fixed delay device 150 so that phase shifts in the input signal can be detected. The flip-flop 144, operating in a way analogous to a phase detector, locks onto a delayed cycle of the input pulse train at the data input A of the flip-flop. This is shown by the notch symbol on the transition of the signal. The clock input B of the flip-flop is locked on either the leading or trailing edge of the input pulse train with respect to the signal at the data input A. The delay of the signal clock input is shown by use of the symbol on a later pulse in the 115 pulse train to show the time delay.

Referring now to Figure 6, a dual input frequency dependent demodulator according to the present invention is shown. A reference oscillator 160 provides an input pulse train to a data input A of an edge detecting flipflop 162 operating in a way analogous to a phase detector. An input signal is provided on an input line 164 through a variable delay channel 166 to a clock input B of the flip-f lop 162. The variable delay channel 166 is controlled by a delay control device 168 which receives a feedback signal through a filter 170 from the output of the flipflop 162. An output of the filter 170 provides a voltage output in which phase shifts with respect 130 to the signal produced by the reference oscillator 160 of the input signal on the line 164 are converted to voltage amplitude shifts for measurement or detection purposes. Thus, the input signal on the line 164 may be controlled to lock on to the frequency of the oscillator 160.

Referring now to Figure 7, another embodiment of a delay lock loop according to the present invention in which a digital feedback control operation is shown. On A channel reference signal is input to an adjustable delay network 180 which is adjusted to zero the circuit. The output from the adjustable delay circuit 180 is connected to a data input D of an edge detecting flip-flop 182. A programmable delay circuit 184 provides an input to a clock input C of the flip-flop 182 and this also becomes the phase corrected output pulse of the circuit. A B channel input is provided to both the programmable delay circuit 184 and a sample rate device 186. The sample rate device 186 has an output connected to the input of an up-down counter 188. The updown counter 188 is, in turn, connected with the programmable delay circuit 184. A driver display circuit 190 monitors the output of the up-down counter as connected to the programmable delay circuit 184. The output of the flip-flop 182 is provided as an input into the up-down counter 188. A Q output of the flipflop causes a down count if it is one while a U or not Q output of the flip-flop 182 causes an up count if one. The operation of this embodiment of the present invention is similar to that where an analog feedback is provided except that, of course, the 100 feedback is a digital feedback.

To zero adjust the delay lock loop of Figure 7, signals are provided to the A and B channel inputs with a zero phase difference and the adjustable delay network 180 is adjusted for zero indication on the display device of the driver display circuit 190. This can be set to be in the middle of the range of the programmable delay circuit 184 if both positive and negative delay correction is desired or at either end of the range if only correction in one direction is desired.

If the signal at the input D of the flip-flop 182 is high at the time a clock signal at a clock input CK is received, the flip-flop will set placing a binary one at the down count enable on the up-down counter 188 and a binary zero at the up count enable. At the next edge of a pulse at the B channel input, the up-down counter will down count reducing the delay through the programmable delay circuit 184 by one time period. Once the signal has propagated through the programmable delay circuit 184 to the clock input of the flip-flop 182, which is at a time earlier than before, the B input is again detected. If the D input to the flip-flop is still a high on the next pulse at the B channel input, the up-down counter counts down one more time period and reduces the programmable delay to cause the B channel input to occur at an earlier time period. The delay through the programmable delay circuit 184 will keep reducing until at clock time in the flip-flop X GB 2 129 242 A 5 182 the input D is low. At that time, the flip-flop will clear, placing a binary one on the up count enable of the up-down counter and a binary zero at the down count enable, enabling the up-down counter to be up counted on the next pulse at the B channel input. In this case, the programmable delay circuit 184 will be increased by one count.

At this time, the delay lock loop is locked on the signal at the B channel inputs and the flip-flop 182 will toggle between set and clear causing the 75 up-down counter 188 to increase and decrease the delay through the programmable circuit 184 by one time unit. The output of the up-down counter can now be processed or displayed as the phase difference between the signals A and B 80 channel inputs or the output from the programmable delay circuit can be used to drive other circuits. The delay lock loop of Figure 7 can be used in all of the same configurations as the delay lock loops shown in Figures 1 to 6. The circuit shown in Figure 7 compares leading edges of pulses at the A and B channel inputs if the flip flop 182 is a leading edge triggered D-type flip flop. Similarly, the trailing edge may be detected if desired, or the circuit may be configured so that the leading edge of a signal at the A channel input is detected while the trailing edge of the signal at the B channel input is detected or vice versa.

There are several significant differences between the delay lock loop of Figure 7 and those 95 of Figures 1 to 6. Primarily, there is no analog feedback voltage. There are no low frequency locking limitations. Of course, a digital voltmeter is not required to measure feedback voltage. The delay inserted in the B channel input is digitized for display or processing purposes in further devices. The up-down counter and programmable delay circuit comprises a memory delay feedback circuit. In the absence of a signal at the B channel input, no correction occurs. Delay through the programmable delay circuit does not change.

When a signal at the B channel input does occur, the first pulse will be phase corrected as long as its phase relationship with the signal at the A channel input has not changed. No pulse narrowing or change of pulse shape occurs with the corrected output signal.

Figure 8 is a frequency phase relationship graph which explains the delay lock loop of Figure 1 and which serves to distinguish it from the 115 characteristics of a phase lock loop circuit.

Referring now to Figure 9, a modulator of a modulator and demodulator apparatus according to the present invention has an edge detection f lip-f lop 200 which receives a data input signal from an oscillator 202 and which provides a Q and a ?5 or not Q output to a voltage divider network composed of resistors 204, 206. The oscillator 202 also produces a transmitted output signal on a line 208 which is referred to as a pilot 125 signal. The output of the oscillator 202 is also connected as a signal input to a variable delay control device 210 which has its output connected to a clock input of the flip-flop 200.

The output of the variable delay control device 130 2 10 also forms the modulated signal output of the circuit after passage through a half cycle, one shot flip-flop 212 which produces a transmitted signal. The output of the voltage divider network is connected to a filter 214 having a first band pass frequency characteristic. The output of the filter 214 is connected as a control signal for a control device 216 for the variable delay control device 2 10. The signal to be modulated is provided on an input line 218 where it is summed together with the signal from the filter 214 and provides an input signal to the control device 216.

Referring now to Figure 10, a demodulator of the modulator and demodulator apparatus for demodulating the signal generated by the modulator of Figure 9 is shown. The pilot signal generated by the oscillator 202 in Figure 9 is provided as the data input to an edge detection f lip-flop 220 whichhas Q and U or not Q outputs connected to a voltage divider network composed of resistors 222, 224. The phase modulated signal generated as the output of the flip-flop 212 in Figure 9 is provided as an input data signal to a variable delay control device 226 as shown in Figure 10. The delay control device 226 has its output connected to the clock input of the flip-flop 220. The output of the voltage divider network is connected as an input to a filter 228 having a second band pass characteristic different from that of the filter 214 shown in Figure 9. The output of the filter 228 is connected with a control device 230 which controls the variable delay control device 226. The output of the filter 228 also comprises the demodulated output signal from the demodulator. It is desirable that the filters 214, 228 have completely different band pass characteristics although it is believed that the circuit would be functional if some overlap of band characteristics was to occur. For example, the filter 214 might have a frequency characteristic rolling off from direct current to attenuate at some given frequency. The filter 228 might therefore have a band pass characteristic above the predetermined frequency of the filter 214.

The pilot signal generated by the modulator of Figure 9 may be directly connected through appropriate signal lines to the demodulator of Figure 10 or various subcarrier relationships may be generated or the signals may be harmonically related and locked together except for the modulation deviations. Obviously many variations of conveying the two signals from the modulator to demodulator may be employed all within the scope of the communications art.

By way of explanation, the flip-flop 212 in the modulator of Figure 9 serves the function of stretching the phase modulated output so that the phase modulated output signals are outside the pass band of the filter 214. Signals falling within the pass band range of the filter 214 are rapidly attenuated or eliminated as a result of the basic operation of the delay lock loop. It is possible to generate phase modulated signals with the embodiment of the invention shown in Figure 9.

6 GB 2 129 242 A 6 The filter 214 does have the desirable effect of filtering out of the transmitted signal certain complements of the modulating signal failing within the pass band of the filter. Thus, the input signal to be modulated is merely added directly to the output of the filter 214.

Using the circuit configurations of Figures 9 and 10 but in which a digitally controlled feedback loop such as that shown in the embodiment of Figure 7 would provide for the additional feature of data coding. This would be implemented by adding additional logic gates in the feedback loop between the flip-flop 182 and the up-down counter 188 as shown in Figure 7 but in amodulator such as shown in Figure 9 to insert the coding functions in the feedback loop.

This could be implemented most simply by causing the up-down counter to have a nonlinear up and down count characteristic. For example, the counter could be made to increment by one unit and decrement by two in order to provide a nonlinear coding function. Then, a receiver would be required which would have the complementary nonlinear characteristic for demodulation. Another example of modulation coding could be to increment and decrement by two units for small deviations of signal output but to increment and decrement the counter by one unit for modulating signals above a threshold level, thus distorting the information carried if a linear demodulator were used. Only a demodualtor with a precise predetermined digital nonlinearity characteristic complementary to the 95 modulator characteristic would reproduce the modulated signal accurately.

Claims

1. A modulator and demodulator apparatus comprising: a modulator consisting of an oscillator for producing a pilot signal, a first pulse edge detector means for detecting the edge of an input pulse and having a first and second input and having at least one input which is indicative of a pulse edge, said first input being connected to the output of said oscillator, a first variable delay device connected to the output of the oscillator and having an output connected to the second input of said first edge detector means, said first variable delay device having the characteristic of varying the delay time of signal transmission therethrough in response to a first control signal, first control means for said first variable delay device for producing the first 115 control signal, a first filter having a filter characteristic connected to the output of said first edge detector means and having an output connected to said first control means, so that a signal to be modulated is added to the input signal to said first control means from said first filter, and a half cycle one shot flip-flop means connected with the output of said first variable delay device and having, as its output, the output signal of said modulator; and a demodulator consisting of a second pulse edge detector means for detecting the edge of an input pulse and having a first and second input and having at least one output which is indicative of a pulse edge said first input being connected to receive said pilot signal from the modulator, a second variable delay device connected to receive the output signal of said modulator and having an output connected to the second input of said second pulse edge detector means, said second variable delay device having the characteristic of varying the delay time of signal transmission therethrough in response to a second control signal, control means for said variable delay device for producing the second control signal, a second filter having a filter characteristic different from the filter characteristic of said first filter connected with the output of said second edge detector means and having an output connected to said second control means, the output of said second filter being a demodulated output signal.

2. A modulator and demodulator substantially as herein described with reference to the accompanying drawings.

New claims filed on 10 August 1983 and 18 November 1983 Superseded claims 1, 2 go New claims 1. A modulator and demodulator apparatus comprising: an oscillator for producing a pilot signal; a modulator consisting of: first pulse edge detector means connected to receive the pilot signal as a first input signal and for producing an output signal related to the time interval between an edge transition of a pulse of the pilot signal and a second input signal of the first edge detector means; first variable delay means connected to receive the pilot signal for providing a variable delay output pulse train with respect to the pilot signal, the output pulse train forming the second input signal of the first edge detector means; first control means for the first variable delay means for controlling the output pulse train thereof; a first filter having a filter characteristic connected to receive the output of the first edge detector means and having an output connected to the first control means; input means for receiving a signal to be modulated connected to the first control means so that the signal to be modulated is added to the output signal of the first filter; and half-cycle, one shot, flip-flop means connected to receive the output pulse train of the first variable delay means and producing, as its output, the output signal of the modulator; and a demodulator consisting of: second pulse edge detector means connected to receive the pilot signal as a first input signal and for producing an output signal related to the time interval between an edge transition of a pulse of the pilot signal and a second input signal of the second edge detector means; second variable delay means connected to receive the output signal of the modulator for providing a variable delay output pulse train with respect to the output signal of the modulator, the output pulse train forming the I "r 7 GB 2 129 242 A 7 second input signal of the second edge detector means; second control means for the second variable delay means for controlling the output pulse train thereof; a second filter having a filter characteristic different from that of the first filter connected to receive the output of the second edge detector means and having an output connected to the second control means; and output means connected to the output of the second filter for producing a demodulated output signal.

2. An apparatus as claimed in claim 1 in which the filter characteristic of the first filter is a band pass range from a very low frequency up to a predetermined frequency, and the filter characteristic of the second filter is a band pass range of frequencies above the said predetermined frequency.

3. An apparatus as claimed in claim 1 or 2 in which the modulator includes non-iinear coding means connected between the output of the first edge detector means and the input of the first filter to add coding signals to the output signal of the first edge detector means, and the demodulator includes complimentary non-linear decoding means.

4. A modulator and demodulator apparatus substantially as herein described with reference to Figures 5 and 6 of the accompanying drawings.

Printed for Her Majesty's Stationery Office by the Courier Press, Leamington Spa, 1984. Published by the Patent Office, 25 Southampton Buildings, London, WC2A lAY, from which copies may be obtained.