GB898495A - Electrical pulse synchronising equipment - Google Patents
Electrical pulse synchronising equipmentInfo
- Publication number
- GB898495A GB898495A GB4114858A GB4114858A GB898495A GB 898495 A GB898495 A GB 898495A GB 4114858 A GB4114858 A GB 4114858A GB 4114858 A GB4114858 A GB 4114858A GB 898495 A GB898495 A GB 898495A
- Authority
- GB
- United Kingdom
- Prior art keywords
- pulse
- train
- edges
- input
- delay
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000003111 delayed effect Effects 0.000 abstract 3
- 230000000630 rising effect Effects 0.000 abstract 2
- 238000001514 detection method Methods 0.000 abstract 1
- 238000004804 winding Methods 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
Landscapes
- Manipulation Of Pulses (AREA)
Abstract
898,495. Automatic frequency control circuits. STANDARD TELEPHONES & CABLES Ltd. Dec. 19, 1958, No. 41148/58. Class 40(5). Equipment for synchronizing first and second rectangular pulse trains having different mark/space ratios comprises variable time delay means TD for the first pulse train, a comparator CT which compares the times at which the pulse edges of the first, delayed, and the second, undelayed, pulse train occur, the width of the pulse (or space) following the compared edges of the first pulse train being greater than that of the pulse (or space) following the compared edges of the second pulse train, and control means CR for the delay means TD which, in response to detection by the comparator CT of a time difference between said compared edges adjusts the delay of TD to correct said detected difference. The variable time delay circuit comprises a transistor (Fig. 2, not shown). The combined circuit for CT and CR is shown in Fig. 3. PNP transistors X2, X3 are normally off and on respectively the collector of X3 being connected to the input of TD through an amplifier AMP and current generator CG thus raising the potential at said input and increasing the delay so that pulses of first train MO1 tend to be overdelayed with respect to those of the second train MA1. For comparing rising edges of the pulse trains the first (monitored and delayed) pulse train MO1 is applied at F and the second (master) pulse train MA1 at E. If the edges of train MO1 are early with respect to those of train MA1, the input at E will not rise above that at F and X2 will remain switched off and X3 on. But if the rising edge of MO1 is delayed by time tl with respect to that of MA1, the input at E will rise above that at F for time tl so that X2 turns on and X3 turns off owing to the charging up of C3 so that the potential at the input of TD is lowered and the delay of MO1 shortened. C3.R3 is made equal to T, the cycle time of MA1 so that X3 remains turned off until X2 does not turn on due to the time delay of MO1 having been so adjusted that it tends to be early with respect to MA1. The operation of the circuit when the falling edges of the pulses are compared is described with reference to Fig. 5 (not shown). In another embodiment of Fig. 3 (Figs. 6, 7, not shown) negative (or positive) spikes are derived from either the monitored or the master pulse trains and supplied as input, over an R.C. network to the base of a transistor equivalent to X2.A complete pulse generation system incorporating the synchronizing system according to the invention is described (Fig. 9, not shown). Other electrical switches such as thyratrons or two-winding relays may replace the transistors.
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB4114858A GB898495A (en) | 1958-12-19 | 1958-12-19 | Electrical pulse synchronising equipment |
FR813495A FR77110E (en) | 1958-12-19 | 1959-12-18 | electronic program equipment for data processing |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB4114858A GB898495A (en) | 1958-12-19 | 1958-12-19 | Electrical pulse synchronising equipment |
Publications (1)
Publication Number | Publication Date |
---|---|
GB898495A true GB898495A (en) | 1962-06-14 |
Family
ID=10418327
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB4114858A Expired GB898495A (en) | 1958-12-19 | 1958-12-19 | Electrical pulse synchronising equipment |
Country Status (1)
Country | Link |
---|---|
GB (1) | GB898495A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2477810A1 (en) * | 1980-03-10 | 1981-09-11 | Control Data Corp | DELAY LOCK LOOP |
GB2130450A (en) * | 1982-11-09 | 1984-05-31 | Del Norte Technology | Delay control circuit |
-
1958
- 1958-12-19 GB GB4114858A patent/GB898495A/en not_active Expired
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2477810A1 (en) * | 1980-03-10 | 1981-09-11 | Control Data Corp | DELAY LOCK LOOP |
GB2130450A (en) * | 1982-11-09 | 1984-05-31 | Del Norte Technology | Delay control circuit |
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