GB2130450A - Delay control circuit - Google Patents

Abstract

The delay between receipt of a pulse ("fire") and the output of a response ("main bang") in e.g. a radar transponder, is controlled automatically to obviate drift by comparing 28 the delay time with a stable reference period 26 also initiated by the input pulse and incrementally adjusting a variable delay device 38, 60 accordingly. The device includes an up/down counter 38 which, if flip-flop 28 is turned on, counts up if the period of single-shot 60 is to be increased, and vice versa. <IMAGE>

Description

SPECIFICATION Timer control circuit This invention relates to automatic control circuits and more particularly to control circuits for timers which must maintain a precise and known time delay.

There are many times and places for providing a known time delay. For example, the measurement of standard time periods is the crucial element in many electronic systems ranging from automobile ignition circuits to radar distance measurement systems.

One such system uses radio ranging and distance measurements for a trilateralization position location as taught in U.S. patents 3,810,179 (Merrick); 4,275,398 (Parker et al), and 3,938,146 (Dano), herein collectively called the 'Merrick' system.

In a trilateralization position location system, such as the Merrick system, an interrogation signal is sent from a master base station to a transponder which sends back a reply signal to the base station. If the reply signal is merely a mirror-like reflection, there could be a cross-talk response wherein the send signal immediately and directly trips the return signal response. This cross-talk may completely destroy the validity of all readings.

Therefore, in the Merrick system, the transponders introduce a turn around delay (TAD) period which enables the base station to block its own response capability long enough to prevent a cross-talk response to its own transmitter. The TAD time period must be measured and controlled with extreme precision because it is substracted from the total travel time required for a radio signal to makea round trip between the base station and the transponder. Since this travel time occurs at the speed of light, and since the turn around time is long relative to the travel time, any error in the TAD period is extremely important.

A difficulty is that time period measurements may vary with many things such as the aging of metal, changes in temperature, and the like. These time variations are an accumulation of respond times beginning with the firing of an SCR and ending with an emission (herein called the "main bang") of radio frequency energy from a magnetron. For example, a temperature change between -10 C and +30"C could cause a six meter range error in measurements in the Merrick system.

Heretofore, the typical solution to variations in time period measurement problems has been to use a component having characteristics which complement the drift, aging, temperature and the like of other components. However, this approach is designed to passively balance one error against another error. If the balancing components do not age at the same rate, for example, it is possible that the compensating component might introduce an error which is greater than the error that it is supposed to correct.

Accordingly, an object of the invention is to provide new and improved control overtime measurements by electronic components. Here, an object is to provide an active control for maintaining time period measurements. In particular, an object is to provide a precisely controlled turn around delay time in a radar ranging and measuring system.

A control circuit for a timer, said control circuit comprising timer means, reference means, means responsive to a start of timing signal forsimul- taneously starting said timer means to measure a timing period and starting said reference means for measuring a reference time period, comparing means jointly responsive to a detection of the end of said timing period and to the end of said reference time period for detecting whether said timing period is accurate, and incremental time period generating means operated selectively responsive to said comparing means for adjusting the duration on said timing period so that the terminations of said timing period and said reference time period coincide.

A preferred embodiment of the invention is shown in the attached drawing wherein: Figure lisa block diagram of the controlled timer with the inventive control circuit; Figure2 is a block diagram showing a further sophistication of the controlled timer circuit of Figure 1; Figure 3 is a simplified block diagram of the Merrick trilateralization position locating system; Figure 4 is a block diagram showing the details of the system of Figures 1 and 2, as installed in the Merrick system of Figure 3; and Figure 5 is a timing chart which explains the operation of the system of Figure 4.

The basic operation of the invention circuit is generically shown in Figure 1. Here, any suitable start of timing or "fire" signal is introduced at input terminal 20, delayed in a controlled timer 22, and delivers to an output terminal 24 as an output or "main bang" signal. This delay between the receipt of an input pulse at 20 and delivery of an output pulse at 24 is the turn around delay time or "TAD" time in the Merrick system. The delay in controlled timer 22 may change with age, temperature, and the like, and therefore, circuit 22 requires control of some kind.

According to the invention, when the input signal is received at terminal 20, it is fed simultaneously to both the controlled timer circuit 22 and a reference circuit 26. This reference circuit 26 is an extremely stable device, such as a counter driven by a quartz clock or a very high grade delay line. The reference circuit 26 measures a time period responsive to a stable circuit value and then releases a signal to a comparison circuit 28. The output of timer 22 is also delivered to comparison circuit 28. If the timer 22 correctly releases its delayed signal at exactly the proper time, there is a positive comparison at the two inputs of circuit 28, and nothing further happens. However, if the comparing circuit 28 finds that the output of the timer 22 is earlier or later than the signal from reference circuit 26 the adjusting circuit 30 is operated to adjust the timer 22.For example, a small segment of the total time period measured by timer 22 may be produced by one or more singleshot multivibrators. The adjusting circuit 30 may simply fire (or inhibit) a suitable number of such single-shot multivibrators to add (or subtract) their time period to the total time period measured by timer 22.

Figure 2 illustrates the construction of the controlled timer 22 and explains the control which is exercised over it. The input or fire signal received at terminal 20 triggers the initially controlled timer 36, which measures a fixed period of time. During any significant interval between the ends of the controlled and the reference time periods, a counter 38 counts a predetermined number of clock pulses.

When the timer 36 reaches the end of its fixed time period, it feeds a triggering control signal to a single shot multivibrator 40 in order to adjust the controlled time period by adding a variable width pulse to the total time measured by circuit 36.

When the counter 38 reaches its half count, a signal may be sent to the interface circuit 42 which sets up a condition corresponding to the half-time of the period being measured by timer 36. At this half-way point, it is possibleto determine whether the total time period being measured by timer 36 will be too long or too short and further to initiate a correction, if necessary.

If the delay period being measured by circuit 36 appears, at the half-count, to be either too long or too short, signals are applied to the up/down input of counter circuit 38 and counts are either added to or substracted from the count stored by the counter.

Since the controls are digital, it is easy to program the system to make the decision of whether the measured time period is too long or short on either an absolute basis or a tolerance basis. Also, since the timer 36 is a cyclic circuit, it is quite easy for the system to be programmed to make an after-the-fact decision which effects the next and upcoming timing cycle. Thus, degrees of correcion may be built into the timer 40.

Figure 3 is a simplified drawing of a distance measuring system (for example, the Merrick system) wherein a base station 44 transmits pulse signals at antenna 46 and receives signals at antenna 48. The remote transponder 50 receives the pulse signal on antenna 52 and transmits on antenna 54. The total transmission travel time represented by a round trip of these pulses indicates the distance between base station 44 and transponder 50.

If no precautions are taken, it is possible that base station receiver antenna 48 could pick up the send pulse directly after it is transmitted from the antenna 46. Accordingly, the base station blanks itself for a discrete period of time following each transmission of a pulse from the antenna 46. The blanking period is long enough to preclude the direct or cross-talk response, wherein antenna 48 picks up the signal transmitted by antenna 46. To further ensure a proper response, the blanking period may be made longer. Therefore, the transponder 50 inserts a turn-around delay at TAD circuit 56 which precludes a return of a signal during the self-blanking period.

The invention is used to control this TAD period, as taught in Figure 4.

In Figure 4, the pulses transmitted from the base station antenna 46 (Figure 3) are received at antenna 52 (Figure 4). The outgoing pulse is transmitted out of the wave guide 54 and back to base station antenna 48. The circuits of Figure 4 are a single shot multivibrator 60 which measures a standard period of time and then fires a silicon controlled rectifier (SCR) 62. The SCR triggers a transmitter 64 which generates a pulse that is transmitted through the wave guide and out the antenna 54. Each of these components adds a time delay period, which may fluctuate with aging, temperature, manufacturing tolerance, and the like.

A wave guide RF detector 66 detects the output signal of the transmitter circuit 64 and then supplies the power to that signal, which is the output signal, here called the "main bang". The circuit 68 is a logic circuit which provides interface functions.

The incoming pulse or "fire" signal is applied to the timer 26, which is as closely controlled as possible to minimize as much timing variation, as possible. It may be a high quality delay line. The output of the timer 26 is reference signal "REF" which is fed into a flip-flop 28, which may or may not operate in order to provide the comparison function.

If the "main bang" signal fed back from pick-up 66 arrives before the reference signal from circuit 26, the flip-flop 28 is turned on. This means that the period of timer 26 is too short; therefore, counter 38 must be forced to count up during an added period, which is the interval between the ends of the time periods measured by circuits 60,26. If the "main bang" signal arrives at circuit 28 after the "REF" signal from reference circuit 26, it means that the delay in timer 22 is too long. Therefore, the flip-flop 28 remains off and the counter 38 counts down.

Also responsive to the time out of the single shot timer circuit 26, an additional single shot multivibrator 40 is triggered to start a free-running flip-flop 72, which generates a train of clock pulses that are applied to drive the counter 38.

The binary outputs of the counter 38 are connected through a series of binary weighted resistors 74 to a control termination on the TAD circuit 60. At least one of these resistors is enabled and a coded combination of resistors may be enabled on each count depending upon the step of the counter Therefore, the counter 38 steps up or down as many steps as may be required to bring the "main bang" signal into synchronism with the output of the reference signal circuit 26. When this synchronism occurs, a control voltage is fed through a resistor or a coded combination of resistors 74 and into the control terminal of circuit 60 in order to adjust the period of its time cycle. Once the correct timing is established, only minor adjustments are required to maintain the synchromism.

Figure 5 explains the timing of the circuit. The arrival of the start of timing or "fire" pulse (Line A) at antenna 52 (Figure 3), signals the start of the TAD time period (Line B), as measured by circuit 60 (Figure 4) after which the SCR 62 fires (Line C). After inherent system delays, the "main bang" signal occurs and is detected by the wave guide detector 66. If the reference signal is delivered simultaneously (Line E) by the circuit 26, the timing is correct as shown at J. If the reference signal from circuit 26 is not delivered (Line F), the test flip-flop 28 does not respond. If the reference signal from circuit 26 occurs before the "main bang" signal (Line G), the test flip-flop 28 is operated, during which time the counter 38 counts (Line H). The counting determines how the timing cycle is adjusted. The various circuits are then reset (Line I).

Those who are skilled in the art will readily perceive how various modifications may be made.

Therefore, the appended claims are to be interpreted to cover all equivalent structures falling within the true scope and spirit of the invention.

Claims (14)

1. A control circuit for a timer, said control circuit comprising timer means, reference means, means responsive to a start of timing signal for simultaneously starting said timer means to measure a timing period and starting said reference means for measuring a reference time period, comparing means jointly responsive to a detection of the end of said timing period and to the end of said reference time period for detecting whether said timing period is accurate, and incremental time period generating means operated selectively reponsive to said comparing means for adjusting the duration on said timing period so that the terminations of said timing period and said reference time period coincide.

2. The control circuit of Claim 1 wherein said incremental time period generating means is a circuit for selectively adding a fixed period to the end of said timing period.

3. The control circuit of Claim 1 and counter means responsive to said comparing means for measuring the length of a period between the detection of the end of said timing period and the end of the said reference time period, said incremental time period generating means operating responsive to said counter means.

4. The control circuit of Claim 3 wherein said incremental time period generating means includes a circuit for adding a variable time period to the end of said timed period responsive to a count reached by said counter means.

5. The control circuit of any one of the Claims 1 4 and a radio distance measuring system comprising means for transmitting send and return pulse signals between a base station and a transponder, and means in said transponder responsive to said control circuit for measuring a turn around delay time period at said transponder, said turn around delay time period being inserted between the receipt of said send pulse and the transmission of said return pulse.

6. Atimercontrol circuit comprising controlled means and reference means each for measuring a fixed period of time, means responsive to a start signal for simultaneously starting said controlled means and said reference means, means responsive to said controlled means for transmitting an output signal at the end of the fixed period of time which is measured by said controlled means, means for detecting said output signal, comparison means jointly responsive to said detector means and to said reference means for comparing the ends of said fixed periods of time as measured by said controlled means and by said reference means, and means responsive to said comparison means for selectively adding an incremental time period to said fixed period of time as measured by said control means.

7. The timer control of Claim 6 and counter means driven by said comparison means for measuring any time interval which may occur between the ends of said fixed periods of time as measured by said controlled means and said reference means, and means repsonsive to said counter means for operating said incremental time period adding means.

8. The time control circuit of Claim 7 wherein said counter means is a binary counter, whereby the interval is measured with a resolution equal to one binary bit.

9. The time control circuit of Claim 8 and plurality of weighting resistors connected to the output of said binary counter, whereby at least one of said weighting resistors is selectively enabled depending upon the count reached by said counter, and means responsive to the enabled resistor for adjusting the incremental time period which is added to the period measured by said controlled means.

10. The timer control circuit of any of the Claims 6 - 9 and a radio distance measuring system comprising meansfortransmitting send and return pulse signals over a path between a base station and a transponder, and means in said transponder responsive to said timer control circuit for inserting a measured turn around delay time period timer between the receipt of said send pulse and the transmission of said return pulse at said transponder.

11. A control circuit for a timer substantially as described herein with reference to and as illustrated in Figure 1 ofthe accompanying drawings.

12. A control circuit for a timer substantially as described herein with reference to and as illustrated in Figure 2 of the accompanying drawings.

13. A control circuit for a timer substantially as described herein with reference to and as illustrated in Figure 4 of the accompanying drawings.

14. A control circuit as claimed in Claim 13, and substantially as described herein with reference to as illustrated in Figure 13 of the accompanying drawings.