GB2126832A

GB2126832A - Carrier chrominance signal forming circuit

Info

Publication number: GB2126832A
Application number: GB08323407A
Authority: GB
Inventors: Hiroyuki Sugiyama; Nobuaki Takahashi; Takeshi Shibamoto; Hideo Sato; Yoshiaki Amano; Koji Tanaka
Original assignee: Victor Company of Japan Ltd; Nippon Victor KK
Current assignee: Victor Company of Japan Ltd; Nippon Victor KK
Priority date: 1982-09-07
Filing date: 1983-09-01
Publication date: 1984-03-28
Also published as: DE3332211A1; GB8323407D0

Abstract

A carrier chrominance signal forming circuit comprises a circuit 52 for supplying burst flag pulses, a first adder 51 for adding a line-sequential color different signal and the burst flag pulses, a balanced modulator 53 supplied with an output signal of the first adder as a modulating signal, for balance-modulating a carrier by the modulating signal, a circuit 54, 55, 56 for alternately supplying first and second chrominance subcarriers to the balanced modulator as a carrier for every one horizontal scanning period, where the first and second chrominance subcarriers have the same frequency and have phases which mutually differ by 90 DEG , a delay circuit 57 for delaying an output modulated signal of the balanced modulator by substantially one horizontal scanning period, and a second adder 58 for adding the output signals of the delay circuit and the balanced modulator, and for producing a carrier chrominance signal in accordance with the NTSC system. A further circuit is described for producing a carrier chrominance signal in accordance with the PAL system. <IMAGE>

Description

SPECIFICATION Carrier chrominance forming circuit The present invention generally relates to carrier chrominance signal forming circuits, and more particularly to a circuit having a simple circuit construction, for forming a line-sequential color difference signal into a carrier chrominance signal which is in accordance with the NTSC system or the PAL system.

Conventionally, apparatuses have been proposed for reproducing recorded signals from a rotary recording medium (hereinafter simply referred to as a disc) which is recorded with a digital video signal comprising a color video information related to a still picture and the like together with a digital audio signal. In this type of a reproducing apparatus, the reproduced digital video signal is subjected to a predetermined signal processing to form an analog signal, to obtain a line-sequential color difference signal.

Thus, it becomes necessary to form a carrier chrominance signal which is in accordance with the NTSC system or the PAL system. For this reason, a carrier chrominance signal forming circuit is provided in the reproducing apparatus, in order to form the carrier chrominance signal.

As will be described hereinafter in conjunction with the drawings, the circuit construction of the conventional carrier chrominance signal was complex. Hence, the number of required circuit parts was large, and the manufacturing cost of the circuit was high. Moreover, the conventional circuit required adjustments at numerous parts of the circuit, and operations for making such adjustments were troublesome to perform.

Accordingly, it is a general object of the present invention to provide a novel and useful carrier chrominance signal forming circuit in which the above described problems of the conventional circuit have been eliminated.

The present invention provides a carrier chrominance signal forming circuit comprising, line-sequential color difference signal supplying means for supplying a line-sequential color difference signal in which a first color difference signal and a second color difference signal are alternately and time-sequentially multiplexed for every one horizontal scanning period, burst flag pulse supplying means for supplying burst flag pulses, first adding means supplied with said linesequential color difference signal and said burst flag pulses, for adding said line-sequential color difference signal and said burst flag pulses, a balanced modulator supplied with an output signal of said first adding means as a modulating signal, for balance-modulating a carrier by the modulating signal, carrier supplying means for alternately supplying a first chrominance subcarrier and a second chrominance subcarrier to said balanced modulator as a carrier for every one horizontal scanning period, said first and second chrominance subcarriers having the same frequency and having phases which mutually differ by 900 a delay circuit for delaying an output modulated signal of said balanced modulator by substantially one horizontal scanning period, and second adding means supplied with an output signal of said delay circuit and the output modulated signal of said balanced modulator, for adding the output signals of said delay circuit and said balanced modulator, and for producing a carrier chrominance signal.

Another and more specific object of the present invention is to provide a carrier chrominance signal forming circuit for forming a carrier chrominance signal which is in accordance with the NTSC system or the PAL system, which has a simple circuit construction, and only requires one balanced modulator and one 1 H (H indicates a horizontal scanning period) delay circuit. According to the circuit of the present invention, the number of required circuit parts is reduced, and the parts of the circuit which require adjustment are reduced. As a result, the circuit according to the present invention can be manufactured at low cost.

Other objects of and further features of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings.

Fig. 1 is a systematic block diagram showing an example of a conventional carrier chrominance signal forming circuit; Fig. 2 is a systematic block diagram showing an example of a circuit part for supplying a signal to a carrier chrominance signal forming circuit according to the present invention; Fig. 3 is a systematic block diagram showing a carrier chrominance signal forming circuit for forming a carrier chrominance signal which is in accordance with the NTSC system, as a first embodiment of the circuit according to the present invention; Figs. 4(A) through 4(F) are graphs, each showing a signal waveform at each part of the block system shown in Fig. 3; Fig. 5 is a concrete circuit diagram showing a part of the block system shown in Fig. 3;; Fig. 6 is a systematic block diagram showing a carrier chrominance signal forming circuit for forming a carrier chrominance signal which is in accordance with the PAL system, as a second embodiment of the circuit according to the present invention; Fig. 7 is a systematic circuit diagram showing a part of a circuit for supplying a signal to the block system shown in Fig. 6; Figs 8(A) through 8(G) are graphs, each showing a signal waveform at each part of the block system shown in Fig. 6; and Fig. 9 is a concrete circuit diagram showing a part of the block system shown in Fig. 6.

For example, the conventional carrier chrominance signal forming circuit was designed as shown in Fig. 1. In Fig. 1, a line-sequential color difference signal is supplied to switching circuits 12 and 13, through an input terminal 11.

The switching circuits 1 2 and 13 alternately open and close for every one horizontal scanning period (1 H) according to switching signals applied thereto through corresponding terminals 14 and 15, and repeat these opening and closing operations. That is, when one of the switching circuits 1 2 and 1 3 is open, the other of the switching circuits 12 and 13 is closed, and when the one switching circuit closes, the other switching circuit opens. These opening and closing operations are repeated for every 1 H.

Accordingly, a first color difference signal, that is, the (R-Y) signal or the / signal, for example, is obtained from the switching circuit 1 2. On the other hand, a second color difference signal, that is, the (B-Y) signal or the 0 signal, for example, is obtained from the switching circuit 1 3. These first and second color difference signals are alternately obtained from the switching circuits 1 2 and 13, for every 1 H.

The first color difference signal from the switching circuit 12 is directly supplied to an adder 17, and also indirectly supplied to the adder 17 after being delayed by 1 H in a 1 H delay circuit 1 6. As a result, the first color difference signal of each horizontal scanning period is obtained from the adder 17 in terms of 2H. Similarly, the second color difference signal is directly supplied to an adder 22, and also indirectly supplied to the adder 22 after being delayed by 1 H in a 1 H delay circuit 21. The output color difference signal of the adder 17 is supplied to a balanced modulator 18, to subject a carrier obtained through a terminal 1 9 having a predetermined phase and a frequency of 3.58 MHz, to a balanced modulation.The output color difference signal of the adder 22 is supplied to a balanced modulator 23, to subject a carrier obtained through a terminal 24 having a phase which differs with the phase of the carrier obtained through the terminal 1 9 by 900 and a frequency which is the same as the frequency of the carrier obtained through the terminal 19, to a balanced modulation. Output modulated signals of the balanced modulators 18 and 23 are supplied to a mixer 20 wherein the signals are mutually mixed, and a color burst signal obtained through a terminal 25 is also mixed to the signals in this mixer 20. Thus, a carrier chrominance signal which is in accordance with the NTSC system, is obtained through an output terminal 26.

However, in the above conventional carrier chrominance signal forming circuit having the design described heretofore, the circuit construction was complex because the circuit required two of each of the switching circuits, 1 H delay circuits, adder, and balanced modulators.

Hence, the number of required circuit parts was large, and the manufacturing cost of the circuit was high. Further, it was necessary to carry out adjustments so as to adjust the delay quantities of the 1 H delay circuits 1 6 and 21, the adding ratios of the adders 17 and 22, the carrier balances of the balanced modulators 18 and 23, and the mixing ratio of the mixer 10. That is, it was necessary to make adjustments at numerous parts of the circuit, and operations for making such adjustments were troublesome to perform.Therefore, the high manufacturing cost of the circuit was also caused from this necessity to perform these troublesome adjustments.

The present invention has eliminated the problems of the conventional circuit described heretofore, and description will hereinunder be given with respect to each embodiment of the present invention.

First, description will be given with respect to a circuit for supplying a signal to a first embodiment of a carrier chrominance signal forming circuit according to the present invention shown in Fig.

3, by referring to Fig. 2. In Fig. 2, a digital video signal which is reproduced from a disc, is supplied to an input signal processing circuit 32 as an input signal, through an input terminal 31. The input signal is subjected to a predetermined signal processing such as a serial-to-parallel conversion.

In addition, a write-in instruction code and a readout instruction code which are separated from the input signal in the input signal processing circuit 32, are respectively supplied to a write-in controller 34 and a read-out controller 36. The processed input signal from the processing circuit 32 is passed through a buffer and the write-in controller 34, and written into a memory 35. The signal written into the memory 35, is read out under the control of the read-out controller 36.

The signal read out from the memory 35, is supplied to a digital-to-analog (D/A) converter 37 and converted into an analog signal. As a result, line-sequential color difference signals (R-Y) and (B-Y) shown in Fig. 4(A), are alternately and timesequentially obtained through an output terminal 38a for every 1 H. In Fig. 4(A), only the color difference signals (B-Y)1 and (R-Y)j of the i-th scanning line, and the color difference signal (B Y)j+1 of the (i+ 1 )-th scanning line are shown, where iis an integer.

A horizontal blanking period signal and horizontal and vertical synchronizing signals from a standard signal generator 39, are respectively supplied to the write-in controller 34 and the read-out controller 36. Burst flag pulses shown in Fig. 4(B) which are obtained from the standard signal generator 39, are obtained through a terminal 40a. In addition, a flip-flop 41 is set and reset according to a signal from the standard signal generator 39. A symmetrical square wave switching signal shown in Fig. 4(C) which is in phase with the horizontal synchronizing signal and has a pulse width of 1 H, is produced from the flip-flop 41 and obtained through a terminal 42a.

The line-sequential color difference signals (R Y) and (B-Y) obtained through the terminal 38a, are supplied to an adder 51 through a terminal 38b shown in Fig. 3. The burst flag pulses obtained through the terminal 40a, are supplied to a gate circuit 52 through a terminal 40b.

Further, the switching signal obtained through the terminal 42a, is supplied to the gate circuit 52 and to a switching circuit 56 through a terminal 42b. The gate circuit 52 which is supplied with the burst flag pulses, only passes a burst flag pulse positioned immediately prior to the color difference signal (B-Y) among the two color difference signals (R-Y) and (B-Y), according to the switching signal supplied thereto. The burst flag pulses which are passed through the gate circuit 52, are supplied to the adder 51. The adder 51 adds the burst flag pulses from the gate circuit 52 with an opposite polarity with respect to color difference signal (B-Y).

A multiplexed signal shown in Fig. 4(E) comprising the burst flag pulses and the linesequential color difference signals, which is obtained from the adder 51, is supplied to a balanced modulator 53 as a modulating signal.

An oscillator 54 produces a signal having a frequency of 3.58 MHz which is the same as the chrominance subcarrier frequency of the NTSC system. The oscillation output of the oscillator 54 is directly supplied to the switching circuit 56, and also indirectly supplied to the switching circuit 56 after being shifted of its phase by 900 in a 900 phase shifter 55. As a result, the outputs of the oscillator 54 and the 90" phase shifter 55 are alternately supplied to the balanced modulator 53 as a carrier, for every 1 H, according to the switching signal obtained through the terminal 42b. Accordingly, the balanced modulator 53 is alternately supplied with a first carrier which is obtained by shifting the phase of the output of the oscillator 54 by 900, and a second carrier which is the output of the oscillator 54 which is not phase-shifted.

During a 1H in which a burst flag pulse and a color difference signal (B-Y) subsequent to this burst flag pulse are supplied to the balanced modulator 53, the first carrier is balancemodulated by these signals to obtain a first modulated color difference signal (hereinafter simply referred to as a first modulated wave). As described previously, the burst flag pulses and the color difference signal (B-Y) are multiplexed with mutually opposite polarities. Thus, the phase of the carrier which is balance-modulated by the burst flag pulses, is shifted by 1 800 with respect to the phase of the carrier which is balancemodulated by the color difference signal (B-Y).

This means that the modulated wave which is obtained by balance-modulating the first carrier by the burst flag pulses; is the regular color burst signal of the NTSC system. In addition, during a 1 H in which a color difference signal (R-Y) is supplied to the balanced modulator 53, the second carrier is balance-modulated by the color difference signal (R-Y) to obtain a second modulated color difference signal (hereinafter simply referred to as a second modulated wave).

As described before, the frequency of the second carrier is 3.58 MHz which is the same as the frequency of the first carrier, and the phase of the second carrier is advanced by 900 with respect to the first carrier. Thus, this means that the color difference signals (B-Y) and (R-Y) are respectively formed into a quadrature-modulated wave which is in accordance with the NTSC system.

Accordingly, a signal in which the first and second modulated waves are alternately and time-sequentially multiplexed for every 1 H as shown in Fig. 4(E), is obtained from the balanced modulator 53. In Fig. 4(E), the color burst signals which are the modulated waves obtained by balance-modulating the first carrier by the burst flag pulses shown in Fig. 4(D), are indicated by dl and d2. It should be noted that the phase of the first carrier which is balance-modulated by the burst flag pulses, is shifted by 1 800 with respect to the phase of the first carrier which is not balance-modulated. The time-sequentially multiplexed signal thus obtained from the balanced modulator 53, is supplied to an adder 58 with an inverted phase after being delayed by 1 H in a 1 H delay circuit 57.On the other hand, the time-sequentially multiplexed signal obtained from the balanced modulator 53 is also directly supplied to the adder 58. The adder 58 adds the input signals, and essentially subtracts an output delayed signal of the 1 H delay circuit 57 from the output time-sequentially multiplexed signal of the balanced modulator 53, to obtain a signal shown in Fig. 4(F) through an output terminal 59.

As is well known, the chrominance subcarrier frequency of 3.58 MHz of the NTSC system is 227.5 times the horizontal scanning frequency of 15.734 kHz. Because the multiple of 227.5 has a fraction of 0.5 in addition to its integer part, the phase of the chrominance subcarrierdiffers by 0.5 period, that is, by 1800, at the beginning and end of 1 H. Accordingly, because the time-sequentially multiplexed signal supplied to the 1 H delay circuit 57 is a modulated wave obtained by modulating the carrier having the frequency of 3.58 MHz, the input and output of the 1 H delay circuit 57 differ in phase by 1800. However, subtraction is carried out between the output modulated wave of the 1 H delay circuit 57 and the output modulated wave of the balanced modulator 53 in the adder 58.Thus, as a result, the output modulated wave of the 1 H delay circuit 57 is added to the output modulated wave of the balanced modulator 53, with the same phase as the phase of the input modulated wave of the 1 H delay circuit 57.

In the output signal of the adder 58 shown in Fig. 4(F), a multiplexed signal e1 is a signal in which the modulated wave obtained by balance modulating the first carrier by the color difference signal (B-Y)1, and a 1 H delayed modulated wave obtained by balance-modulating the second carrier by the color difference signal (R-Y),~,, are multiplexed. A multiplexed signal e2 is a signal in which a 1 H delayed modulated wave obtained by balance-modulating the first carrier by the color difference signal (B-Y)1, and a modulated wave obtained by balance-modulating the second carrier by the color difference signal (R-Y), are multiplexed. Further, a multiplexed signal e3 is a signal in which a modulated wave having the color difference signal B(B-Y)i+, as its modulating signal, and a 1 H delayed modulated wave having the color difference signal (R-Y)1 as its modulating signal, are multiplexed. The phase of each of the carriers of the modulated waves which constitute the multiplexed signals, e1, e2, and e3 is such that, if the phase of the carrier of the modulated wave having the color difference signal (B-Y) as its modulating signal is represented by < 0o, the phase of the carrier of the modulated wave having the color difference signal (R-Y) as its modulating signal can be represented by < 900. Therefore, the multiplexed signals e1, e2, and e3 are in conformance with the NTSC system.

In this case, the phase of the carrier of the modulated wave having the burst flag pulses as its modulating signal, can be represented by < 1800.

This modulated wave having the burst flag pulses as its modulating signal is repeated twice, and is produced through the output terminal 59 as the color burst signal. Hence, a carrier chrominance signal (including the color burst signal) in which the two color difference signals are subjected to quadrature modulation, and is in conformance with the NTSC system, is obtained from the output terminal 59.

An embodiment of a concrete circuit of an essential part of the block system shown in Fig. 3, is illustrated in Fig. 5. In Fig. 5, those parts which are the same as those corresponding parts in Fig.

3 are designated by the same reference numerals.

In Fig. 5, the time-sequentially multiplexed signal from the balanced modulator 53 is applied to an input terminal 61, and applied to a base of an NPN type transistor Q1. The transistor Q1 is connected as an emitter-follower. The timesequentially multiplexed signal obtained from an emitter of the transistor Q1, is supplied to the 1 H delay circuit 57 through a capacitor C1. On the other hand, the time-sequentially multiplexed signal obtained from the emitter of the transistor Q1 is also supplied to the adder 58, through a resistor R1 and a capacitor C2.

The 1 H delay circuit 57 comprises a 1 H delay line 62, a resistor R2 and a coil L1 respectively connected to an input side of the 1 H delay line 62, and a variable inductance element L2 respectively connected to an output side of the 1 H delay line 62. The 1 H delay circuit 57 delays the input time-sequentially multiplexed signal by 1 H, and applies the delayed signal to a base of an NPN type transistor Q3 through a capacitor C4.

Because the input time-sequentially multiplexed signal is a modulated wave with a carrier having the frequency of 3.58 MHz, it is possible to employ a delay line which uses glass as its medium for the 1 H delay line 62, which is the most generally available and inexpensive.

The adder 58 comprises NPN type transistors Q2 and Q3, base biasing resistors R3, R4, and R5 for the transistor 02, base biasing resistors R9 and R10 for the transistor 03, a resistor R6 connected to an emitter of the transistor 02, a resistor R8 connected to the transistor Q3, a resistor R7 and a capacitor C3 connected in series between the emitters of the transistors Q2 and 03, and the like.

The time-sequentially multiplexed signal obtained through the emitter of the transistor Q1, is subjected to impedance conversion and is obtained through the emitter of the transistor Q2 which constitutes an emitter-follower. This signal from the emitter of the transistor 02 is passed through a circuit comprising the resistors R6, R7, and R8 and the capacitor C3, and then supplied to the emitter of the transistor 03. On the other hand, the time-sequentially multiplexed signal which is delayed by 1 H, is supplied to the base of the transistor 03. Accordingly, a carrier chrominance signal which is obtained by subtracting the input signal to the base of the transistor 03 from the input signal to the emitter of the transistor Q3, is obtained through the collector of the transistor 03.

Next, description will be given with respect to a second embodiment of a carrier chrominance signal forming circuit according to the present invention, by referring to Fig. 6. In Fig. 6, those parts which are the same as those corresponding parts in Fig. 3 are designated by the same reference numerals, and their description will be omitted.

A line-sequential color difference signal shown in Fig. 8(A) is supplied to the adder 51, through the terminal 38B. Burst flag pulses shown in Fig.

8(B) are supplied to the adder 51 through a terminal 71 b, and are added with the iinesequential color difference signal.

A circuit for supplying the burst flag signal to the terminal 71 b in Fig. 6, is shown in Fig. 7. In Fig. 7, an output of a standard signal generator 81 obtained for every 1 H, is supplied to switchers 82 and 83. On the other hand, the output of the standard signal generator 81 is also supplied to a flip-flop 84 as set and reset signals. An output of the flip-flop 84 is applied to the switchers 82 and 83, to alternately put the switchers 82 and 83 in a conducting (passing) state for every 1 H.

Accordingly, pulses which have alternately passed through the switchers 82 and 83 for every 1 H (with a period of 2H), are respectively applied to an inverting input terminal and a non-inverting input terminal of an operational amplifier 85. As a result, burst flag pulses b1, b2, b3,. .. shown in Fig. 8(B) wherein the phase is inverted for every 1 H, are obtained through a terminal 71 a. These burst flag pulses obtained through the terminal 71 a, are applied to the terminal 71b shown in Fig.

6. In addition, one output of the flip-flop 84 is obtained through a terminal 74a, and applied to a terminal 74b shown in Fig. 6.

As clearly seen from Figs. 8(A) and 8(B), the color difference signals (R-Y) and the burst flag pulses b1, b3,. .. immediately prior to these color difference signals (R-Y), are added in the adder 51 with the same polarity. However, the color difference signals (B-Y) and the burst flag pulses b2, b4,. . . which are immediately prior to these color difference signals (B-Y) are added in the adder 51 with mutually opposite polarities. The output of the adder 51 is supplied to the balanced modulator 53.

An oscillator 54a produces a signal having a frequency of 4.43 MHz which is the same as the chrominance subcarrier frequency of the PAL system. The oscillation output of the oscillator 54a is directly supplied to the switching circuit 56, and also indirectly supplied to the switching circuit 56 after being shifted of its phase by 900 in the 900 phase shifter 55. As a result, the outputs of the oscillator 54a and the 900 phase shifter 55 are alternately supplied to the balanced modulator 53 as a carrier, for every 1 H, according to the switching signal obtained through the terminal 74b. Accordingly, the balanced modulator 53 is alternately supplied with a first carrier of the output of the oscillator 54a, and a second carrier having a phase which is shifted by 900 with respect to the first carrier, for every 1 H.

During a 1H in which a burst flag pulse and a color difference signal subsequent to this burst flag pulse are supplied to the balanced modulator 53, a first chrominance subcarrier is balancemodulated by these signals, and the balanced modulator 53 produces a first modulated wave.

As described before, the color difference signals (B-Y) and the burst flag pulses b2, b4, b6,. .. immediately prior to these color difference signals (B-Y) are added with mutually opposite polarities. Thus, the phase of the carrier which is balance-modulated by the burst flag pulses b2, b4, b6.... is shifted by 1 800 with respect to the phase of the first chrominance subcarrier which is balance-modulated by the color difference signals (B-Y). On the other hand, during a 1 H in which a burst flag pulse and a color difference signal (R-Y) subsequent to this burst flag pulse are supplied to the balanced modulator 53, a second chrominance subcarrier is balance-modulated by these signals, and the balanced modulator 53 produces a second modulated wave.As described previously, the color difference signals (R-Y) and the burst flag pulses b1, b3, b5, . . . immediately prior to these color difference signals (R-Y) are added with the same polarity. Accordingly, the phase of the carrier which is balance-modulated by the burst flag pulses b1, b3, b5,.. . and the color difference signals (R-Y), is in phase with the second chrominance subcarrier.

Hence, a signal shown in Fig. 8(C) in which the first modulated wave and the second modulated wave are alternately and time-sequentially multiplexed for every 1 H, is obtained from the balanced modulator 53. In Fig. 8(C), "B-Y < 0 " indicates the modulating signal (B-Y) of the first modulated wave and the phase of its carrier.

Similarly, "R-Y < 90 " indicates the modulating signal (B-Y) of the second modulated wave and the phase of its carrier with respect to the phase of the carrier of the first modulated wave. Further, an arrow illustrated above the modulated signal wave which is balance-modulated by the burst flag pulse, indicates the phase of its carrier in vector form, by taking the phase of the carrier of the first modulated wave as a reference. An arrow pointing upward indicates that the phase of the carrier of the modulated wave which is balancemodulated by the burst flag pulse, is shifted by 90" with respect to the phase of the carrier of the first modulated wave, and an arrow pointing leftward indicates that the phase is shifted by 1800 with respect to the phase of the carrier of the first modulated wave.This vector illustration of the phase is also employed in Figs. 8(D) through 8(G).

The output of the balanced modulator 53 is supplied to a phase inverter 72 wherein the phase is inverted and formed into a signal shown in Fig.

8(D). This output signal of the phase inverter 72 is applied to a contact p of a switching circuit 73.

On the other hand, the output of the balanced modulator 53 is directly applied to a contact q of the switching circuit73. A moving contact of the switching circuit 73 is switched for every 1 H to connect to one of the contacts p and q, according to the switching signal applied to the switching circuit 73 through the terminal 74b. Hence, during the 1 H in which the second modulated wave is applied to the contact q, the moving contact is connected to the contact q, and the switching circuit 73 seiectively passes the second modulated wave.On the other hand, during a 1 H in which the first modulated wave is applied to the terminal q, the moving contact switches over and connects to the contact p, and the switching circuit 73 selectively passes the phase-inverted signal of the first modulated wave within the output signal of the phase inverter 72.

Accordingly, a signal shown in Fig. 8(E) is obtained from the switching circuit 73, and this signal is supplied to a delay circuit 75 provided in a subsequent stage.

The delay-time of the delay circuit 75 is selected to a value which is exceedingly close to 1 H, and so that the phase of the carrier of an output delayed signal is shifted by substantially 1 800 (that is, the phase is inverted) with respect to the phase of the carrier of the input signal of the delay circuit 75. As is well known, the chrominance subcarrier frequency of the PAL system is (1135i4+1/625) times the horizontal scanning frequency fH. Thus, the chrominance subcarrier frequency cannot be described in terms of (integer+0.5)f,. For this reason, the phase of the carrier will not be shifted by 1 800 if the delay circuit 75 accurately delays the input signal by 1 H.This is the reason why the delay time of the delay circuit 75 is selected to a value which is exceedingly close to 1 H, and so that the phase of the carrier of the output delayed signal is shifted by substantially 1 800 with respect to the phase of the carrier of the input signal of the delay circuit 75. By selecting the delay time of the delay circuit 75 in this manner, the output delayed signal of the delay circuit 75 becomes as shown in Fig. 8(F).

The output delayed signal shown in Fig. 8(F) is a signal in which modulated waves f1 , f3, f5, . .. obtained by balance-modulating a carrier having a phase which is shifted by 1800 with respect to the phase of the carrier of the first modulated wave by the burst flag pulses, modulated waves obtained by balance modulating a carrier having a phase which is shifted by 0 with respect to the phase of the carrier of the first modulated wave by the color difference signals (B-Y), modulated waves f2, f4, .6.... obtained by balance-modulating a carrier having a phase which is shifted by 2700 with respect to the phase of the carrier of the first modulated wave by the burst flag pulses, and modulated waves obtained by balancemodulating a carrier having a phase which is shifted by 2700 with respect to the phase of the carrier of the first modulated wave by the color difference signals (R-Y), are time-sequentially multiplexed.

The output delayed signal of the delay circuit 75 is supplied to the adder 58 wherein the output delayed signal is added with the output signal of the balanced modulator 53. Hence, a signal shown in Fig. 8(G) is obtained from the adder 58.

In the signals shown in Fig. 8(G), a color burst signal g1 is a signal in which a modulated wave c1 within the time-sequentially mutliplexed signal shown in Fig. 8(C) obtained by balancemodulating a carrier having a phase which is shifted by 900 with respect to the phase of the carrier of the first modulated wave by the burst flag pulse, and the modulated wave f1 shown in Fig. 8(F), are multiplexed. The phase of the color burst signal g1 is shifted by 1350 with respect to the phase of the carrier of the first modulated wave.A signal subsequent to the color burst signal g1 is a signal in which the delayed modulated wave obtained by balance-modulating a carrier having a phase which is shifted by 00 with respect to the phase of the carrier of the first modulated wave by the color difference signal (B-Y), and an underlayed modulated wave obtained by balance-modulating a carrier having a phase which is shifted by 900 with respect to the phase of the carrier of the first modulated wave by the color difference signal (R-Y), are band-share multiplexed. A subsequent color burst signal g2 is a signal in which a modulated wave c2 within the time-sequentially multiplexed signal shown in Fig.

8(C) obtained by balance-modulating a carrier having a phase which is shifted by 1 800 with respect to the phase of the carrier of the first modulated wave by the burst flag pulse, and the modulated wave f2 shown in Fig. 8(F), are multiplexed. The phase of this color burst signal g2 is shifted by --1 350 with respect to the phase of the carrier of the first modulated wave.Further, a signal subsequent to the color burst signal g2 is a signal in which the delayed modulated wave obtained by balance-modulating a carrier having a phase which is shifted by 00 with respect to the phase of the carrier of the first modulated wave by the color difference signal (B-Y), and an undelayed modulated wave obtained by balance modulating a carrier having a phase which is shifted by 2700 with respect to the phase of the carrier of the first modulated wave by the color difference signal (R-Y), are band-share multiplexed. The color burst signal g1.the signal subsequent to the color burst signal g1. the color burst signal g2, the signal subsequent to the color burst signal g2, and the like are time-sequentially multiplexed in the signal shown in Fig. 8(G).

Color burst signals g3, g5.... are signals in which modulated waves c3, c5,... and the modulated waves f3,f5,... which are respectively in phase, are multiplexed. Thus, the phase of the color burst signals g3,g5.... are 1350 with respect to the phase of the carrier of the first modulated wave, as in the case of the color burst signal g1. On the other hand, color burst signals g4, .6.... are signals in which modulated waves c4,c6,... and the modulated waves f4, f6,. .. which are respectively in phase, are multiplexed. Therefore, the phases of the color burst signals g4, g6.... are --1350 with respect to the phase of the carrier of the first modulated wave, as in the case of the color burst signal g2.

Accordingly, the signal shown in Fig. 8(G) from the adder 58 which is obtained through the output terminal 59, is a carrier chrominance signal which is substantially in conformance with the carrier chrominance signal of the PAL system.

That is, in the signal shown in Fig. 8(G), the chrominance subcarrier having a frequency of 4.43 MHz is quadrature-modulated by the color difference signals (R-Y) and (B-Y), the phase of the carrier having the color difference signal (R-Y) as its modulating signal is inverted for every 1 H, and the phase of the color burst signal is shifted by 1350 or 1350 with respect to the phase of the carrier of the color difference signal (B-Y) in correspondence with this phase inversion.

In the embodiment described heretofore, the carrier chrominance signal of the PAL system is formed from a line-sequential color difference signal which is transmitted with the regular horizontal scanning frequency of the PAL system.

However, the horizontal scanning frequency fH itself may be slightly varied from its regular value so that the horizontal scanning frequency fH satisfies a relation (integer+0.5) fH with respect to the chrominance subcarrier frequency fsc In such a case, a 1 H delay circuit is used for the delay circuit 75.

An embodiment of a concrete circuit of an essential part of the block system shown in Fig. 6, is shown in Fig. 9. In Fig. 9, those parts which are the same as those corresponding parts in Fig. 5 are designated by the same reference numerals, and their description will be omitted. A collector output of the transistor Q1 is inverted of its phase in an NPN type transistor Q4 which constitutes the phase inverter 72. The phase-inverted output of the phase inverter 72 is then supplied to a switching transistor OS of the switching circuit 73 which is constituted by field-effect transistors (FETs) Q5 and 06. On the other hand, the emitter output of the transistor Q1 is supplied to the switching transistor Q6. The switching signal obtained through the terminal 74b is directly applied to a gate of the switching transistor 06, while this switching signal is applied to the switching transistor Os through an inverter 91.

The signal obtained from the switching circuit 73 is supplied to the delay circuit 75 including a delay line 92.

Further, the present invention is not limited to these embodiments, but various variations and modifications may be made without departing from the scope of the present invention.

Claims

1. A carrier chrominance signal forming circuit comprising: line-sequential color difference signal supplying means for supplying a line sequential color difference signal in which a first color difference signal and a second color difference signal are alternatively and times-sequentially multiplexed for every one horizontal scanning period; burst flag pulse supplying means for supplying burst flag pulses; first adding means supplied with said line sequential color difference signal and said burst flag pulses, for adding said line sequential color difference signal and said burst flag pulses; a balanced modulator supplied with an output signal of said first adding means as a modulating signal, for balance-modulating a carrier for the modulating signal;; a carrier supplying means for alternately supplying a first chrominance subcarrier and a second chrominance subcarrier to said balanced modulator as a carrier for every one horizontal scanning period, said first and second chrominance subcarriers having the same frequency and having phases which mutually differ by 900; a delay circuit for delaying an output modulated signal of said balanced modulator by substantially one horizontal scanning period; and second adding means supplied with an output signal of said delay circuit and the output modulated signal of said balanced modulator, for adding the output signals of said delay circuit and said balanced modulator,cuvd for producing a carrier chrominance signal.

2. A carrier chrominance signal forming cirCuit as claimed in claim 1 in which said first color difference signal is a color difference signal (B-Y), said second color difference signal is a color difference signal (R-Y), said burst flag pulse supplying means comprises generating means for generating a pulse for every one horizontal scanning period, and means for obtaining a pulse immediately prior to said first color difference signal (B-Y) among the pulses generated by said generating means for every two horizontal scanning periods and for supplying the obtained pulses to said first adding means, said first adding means adds the burst flag pulses supplied from said burst flag pulse supplying means to said linesequential color difference signal with an opposite polarity with respect to said first color difference signal (B-Y), said carrier supplying means comprises an oscillator for producing a standard signal having the same frequency as a chrominance subcarrier frequency of an NTSC system video signal, a phase shifter for shifting the phase of an output signal of said oscillator by 900 so that the phase of an output signal of said phase shifter lags the phase of an input signal of said phase shifter by 900, and a switching circuit for alternately supplying the output signal of said oscillator and the output signal of said phase shifter to said balanced modulator for every one horizontal scanning period, and said second adding means essentially subtracts the output signal of said delay circuit from the output signal of said balanced modulator and produces a carrier chrominance signal in conformance with the NTSC system.

3. A carrier chrominance signal forming circuit as claimed in claim 2 in which said switching circuit supplies a carrier which is shifted of its phase by said 900 to said balanced modulator while said first color difference signal (B-Y) is supplied to said switching means, and supplies a carrier which is not shifted of its phase to said balanced modulator while said second color difference signal (R-Y) is supplied to said switching circuit.

4. A carrier chrominance signal forming circuit as claimed in claim 1 which further comprises phase inverting means for inverting the phase of the output modulated signal of said balanced modulator, and a first switching circuit for alternately passing an output signal of said phase inverting means and the output signal of said balanced modulator for every one horizontal scanning period, in which carrier chrominance signal forming circuit, said first color difference signal is a color difference signal (B-Y), said second color difference signal is a color difference signal (R-Y), said burst flag pulse supplying means comprises generating means for generating a pulse for every one horizontal scanning period, and means for supplying pulse obtained for every one horizontal scanning period among the pulses generated by said generating means to said first adding means with the polarity of the pulses unchanged, and for supplying pulses obtained for every other one horizontal scanning period among the pulses generated by said generating means to said first adding means with the polarity of the pulses reversed so that the pulses have opposite polarities, said first adding means adds a burst flag pulse of said opposite polarity immediately prior to said first color difference signal (B-Y) to a burst flag pulse of said unchanged polarity immediately prior to said second color difference signal (R-Y), said carrier supplying means comprises an oscillator for producing a standard signal having the same frequency as a chrominance subcarrier frequency of a PAL system video signal, a phase shifter for shifting the phase of an output signal of said oscillator by go0 so that the phase of an output signal of said phase shifter lags the phase of an input signal of said phase shifter by 900, and a second switch ing circuit for alternately supplying the output signal of said oscillator and the output signal of said phase shifter to said balanced modulator for every one horizontal scanning period as first and second carriers, respectively, said balanced modulator produces a signal in which first and second modulated waves are time-sequentially multiplexed, said first modulated wave being obtained by balance-modulating said first carrier by said burst flag pulse and said first color difference signal immediately subsequent to said burst flag pulse, said second modulated wave being obtained by balance-modulating said second carrier shifted of its phase by said 900 by said burst flag pulse and said second color difference signal immediately subsequent to said burst flag pulse, said first switching circuit alternately passes said first modulated wave which is phase inverted by said phase inverting means and said second modulated wave within the output signal of said balanced modulator which has not passed through said phase inverting means, and said second adding means adds the output signal of said delay circuit with the output signal of said balanced modulator and produces a carrier chrominance signal in conformance with the PAL system.

5. A carrier chrominance signal forming circuit as claimed in claim 4 which further comprises switching signal supplying means for supplying a switching signal which reverses its polarity for every one horizontal scanning period, and said first and second switching circuits are each supplied with said switching signal from said switching signal supplying means.