GB2123605A

GB2123605A - MOS integrated circuit structure and method for its fabrication

Info

Publication number: GB2123605A
Application number: GB08303261A
Authority: GB
Inventors: Paul Richman
Original assignee: Standard Microsystems LLC
Current assignee: Standard Microsystems LLC
Priority date: 1982-06-22
Filing date: 1983-02-07
Publication date: 1984-02-01
Also published as: JPS58225670A; GB8303261D0

Abstract

An MOS semiconductor integrated circuit FET includes an active channel region between its source and drain regions. A doped surface region (34), which is self- aligned with an overlying thick field oxide layer (36), is controllably spaced with respect to the boundaries of the active channel region in the channel width direction. In the method for fabricating the structure a tapered silicon dioxide sidewall spacer is used as an implantation mask during the implantation of the doped surface region so as to achieve the selective location of the doped surface region with respect to the boundaries of the active channel region. <IMAGE>

Description

SPECIFICATION N-channel MOS integrated circuit structure and method for its fabrication The present invention relates generally to semiconductor integrated circuits, and more particularly to an improved integrated circuit with a self-aligned thick-field doped region.

Patent No. 3,751,722 by the present applicant and assigned to the same assignee as the present application discloses an MOS semiconductor integrated circuit n-channel structure in which p-type doped surface regions are formed under and self-aligned with the thick oxide field regions. The doped surface region, which is preferably formed by the implantation of boron ions into the upper surface of a p-type substrate, extends between and contacts the n+type regions of two adjacent unrelated MOS devices, such as the adjacent source and drain regions of two unrelated MOS FETs.

Particularly, when this structure is employed with a reverse substrate bias, it has been found to virtually eliminate parasitic field inversion and punchthrough mechanisms in high-speed, highdensity, n-channel MOS integrated circuits. In recent years, this structure has also been employed with equal advantage in CMOS n-well integrated circuits. Since its introduction in 1972, this structure, which is identified as the COPLAMOS structure, COPLAMOS being a registered trademark of Standard Microsystems Corporation, has been widely used in n-channel MOS integrated circuits.However, in recent years significant advances have been made in MOS processing techniques toward reducing the size, and thus in increasing the density, of n-channel integrated circuits, such that whereas in the early 1 970s line widths, or the widths of the active channel regions, in the range of 10 microns were typical, many n-channel MOS integrated circuits now being fabricated have line widths of between 1 and 4 microns.

In the structure disclosed in the aforesaid '722 patent, the boron impurities of the doped surface region may laterally diffuse, in the channel width direction, into the active channel regions of the MOS devices, particularly during the formation of the thermally grown overlying thick oxide field regions. In integrated circuits in which the active channel widths are in the order of 10 microns, this lateral diffusion of boron, which in such circuits is typically in the order of 1 micron, does not materially affect the operation of the MOS devices. However, in MOS integrated devices which have channel widths in the order of only 2-3 microns, and even less, lateral boron diffusion into the ends of the active channel by as little as 0.5 micron can increase the boron doping concentration in a significant portion of the active channel region.Thus, in the latter case, a much greater percentage of the entire channel experiences an increase in boron doping concentration, thereby resulting in a degradation of tfie performance of the transistor since the ends of the channel at which this occurs experience a reduction in mobility because of increased impurity scattering (and, thus, lower gain), an increase in threshold voltage and an increased amount of drain-to-channel and sourceto-channel parasitic capacitances. These effects will tend to degrade the characteristics of the integrated circuit, particularly with respect to its speed performance.

In recognition of the undesirable effects of the lateral diffusion of boron into the active channel region of narrow-channel MOS devices, several attempts have been made to eliminate or reduce this lateral diffusion and also to reduce the parasitic junction capacitances that occur between the heavily doped (n+) drain, source and diffused interconnection regions and the p-type thick field surface doping region. Two such attempts are described in K. Wang, S. Saller, W.

Hunter, P. Chatterjee and P. Yang, "Direct Moat Isolation for VLSI", presented at the 1981 International Electron Device Meeting, Washington, D.C.; and K. Kurosawa, T. Shibata and H. lizuka, "A New Bird's-Beak Free Field Isolation Technology for VLSI Devices", presented at the 1981 International Electron Device Meeting, Washington, D.C.

These prior attempts have not, however, proven to be successful in eliminating or reducing the lateral diffusion of the boron-field-doping region into the active channel regions of MOS devices while also maintaining the advantages of the COPLAMOS structure, and in particular, the high degree of surface planarity associated with that structure.

It is thus an object of the present invention to provide an MOS integrated circuit having narrow active channel regions in which parasitic field inversion is eliminated by the provision of a doped surface region.

It is another object of the present invention to provide an MOS integrated circuit of the type described which is amenable to effective veryhigh-speed operation in narrow-channel MOS FETs.

It is a further object of the present invention to provide an MOS integrated circuit in which lateral diffusion of the field doped surface region into the active channel regions of MOS devices is substantially reduced or eliminated.

To these ends, the MOS integrated circuit of the present invention includes an active channel region between source and drain regions. A doped surface region, which is self-aligned with an overlying thick oxide region, is selectively formed so as to lie outside or coincident with the active channel region. In the method for fabricating this structure, a tapered silicon dioxide sidewall is used as an implantation mask during the implantation of impurities into the substrate to form the doped surface region in a manner to produce the desired spacing of the doped surface region away from the active channel region.

To the accomplishment of the above and such further objects as may hereinafter appear, the present invention relates to an MOS integrated circuit structure and method for its fabrication substantially as defined in the appended claims and as described in the following specification, as considered along with the accompanying drawings in which:: Figure 1 is a cross-sectional diagram of a semiconductor integrated circuit as viewed in the channel-width direction in an intermediate step of its fabrication according to the prior art; Figures 2(a)-2(g) are cross-sectional diagrams illustrating an embodiment of the semiconductor integrated circuit of the invention at several stages of its fabrication; Figure 3 is a cross-sectional view of the semiconductor integrated circuit structure of Figure 2(9) as viewed in the channel-length direction as indicated by the arrows 3-3 in Figure 2(g); and Figures 4(a)-4(c) are cross-sectional diagrams of a semiconductor integrated circuit according to a second embodiment of the invention at various stages of its fabrication.

Figure 1 is a cross-sectional diagram of an MOS semiconductor integrated circuit field effect transistor (FET) fabricated in accordance with the process disclosed in MOS Field-Effect Transistors and Integrated Circuits by Paul Richman, published by John Wiley 8 Sons, Inc. in 1973, and also in U.S. Patent No. 3,751,722. Since the view of Figure 1 is in the channel width direction, the n+ source and drain regions of the FET are not shown.

The FET structure shown in Figure 1 includes a p-type silicon substrate 10, which is typically between 5 and 100 Q -cm resistivity and of (100) orientation. Thick oxide regions 12, which are thermally grown typically to a thickness of between 4,000A and 1 2,000A, overlie and are self-aligned with a doped surface region 14 of ptype impurities, e.g. boron. The doped region 14 extends between n+ doped regions of neighboring active MOS devices or interconnections formed in "mesas" such as 16 formed on the substrate by means of the localized thermal growth of the oxide layer into the substrate. The doped region 14 prevents the formation of parasitic field inversion in the substrate between neighboring MOS devices, as described in greater detail in the aforesaid patent.The MOS FET of Figure 1 also includes a doped polysilicon gate electrode 18.

and the structure is typically covered by a dielectric layer 20, which is typically a phosphorus-doped silicon dioxide layer.

In the conventional integrated circuit structure of the type illustrated in Figure 1 , the boron impurities from the doped p-type surface region 14 diffuse laterally into the edges of the active channel region between the source and drain regions and along the sidewalls of the mesa 1 6, as seen in the cross section of Figure 1. This diffusion of the boron into the ends of the active channel region was of little significance in the past when the widths of the active channels nchannel FETs of this configuration were in the order of 10 microns. However, in more recent years, when channel widths of such devices are typically between one and four microns, the diffusion of boron impurities into the much more narrow active channel has been found to have an appreciable adverse effect on the gain, threshold voltage, and parasitic capacitances of the MOS device.

The integrated circuit MOS device of the present invention, as shown in Figures 2(g), 3, and 4(c) maintains the advantages of the use of the doped surface region to prevent parasitic field inversion, as in the prior art configuration, while also limiting or preventing the diffusion of the boron impurities of the surface region into the active channel region by selectively and controllably locating the innermost extension of the doped surface region away from or adjacent to the active channel region.

The semiconductor integrated circuit of the invention according to one embodiment thereof is fabricated by initially forming and selectively patterning on a p-type substrate 10 a dielectric layer consisting neither of silicon nitride (Si3N4) or, as shown in Figure 2(a), a layer 22 of silicon nitride of between 500A and 2,000A in thickness over a thin (200A to 1 ,000A) layer 24 of silicon dioxide (SiO2). A layer of a material such as silicon dioxide may, as is known, be used as an etching mask to enable the selective etching of the silicon nitride; this layer may be removed after the etching of the nitride film is accomplished.

A thick (3,000A to 6,000A) layer 26 of chemically-vapor-deposited silicon dioxide is then deposited over the surface of the wafer. As can be seen in Figure 2(b), the thickness of the deposited silicon dioxide layer 26 is greatest where it extends over the upper corners of the silicon nitride-silicon dioxide dielectric, 22, 24.

Thereafter, as shown in Figure 2(c), the silicon dioxide layer 26 is exposed to a directional reactive ion-etching (RIE) procedure of the type described in a paper entitled "Elimination of Hot Electron Gate Current by the Lightly Doped Drain Source Structure" by Ogura et al, presented in December, 1981, at the International Electronic Device Meeting. The directional reactive ionetching step removes all of the deposited silicon dioxide layer 26 from the flat or horizontal portions of the structure, that is, those portions of layer 26 overlying the substrate surface and the upper plane of the silicon nitride-silicon dioxide dielectric. However, a part of the relatively thick portions of the silicon dioxide layer 26 at the outer edges of the dielectric layer will remain after the reactive ion-etching step in the form of tapered sidewalls 28, which extend downward and outwards from the upper surface of the dielectric layer 22, 24 to the surface of the substrate.

Next, a thin layer 30 of silicon dioxide is thermally grown over the upper surface of the silicon substrate 10, and the structure is thereafter subjected to an implantation of boron ions, as indicated by the arrows 32 in Figure 2(d), at an energy typically between 20KeV and 200KeV. The dose of the implant varies with the required boron surface concentration. The dielectric layer 22, 24 and the relatively thick portions of the tapered silicon dioxide sidewalls 28 act as an implantation barrier and mask so that the boron ions pass into the substrate only through the relatively thin portions of the sidewalls and the thin silicon dioxide layer 30, thereby to form the p-type doped surface regions 34, as shown in Figure 2(d).

Next, as shown in Figure 2(e), all exposed areas of either chemically vapor-deposited or thermally grown silicon dioxide are etched away leaving the selectively etched silicon nitride-silicon dioxide layer 22, 24 positioned over selected regions of the silicon substrate 10. At this stage in the fabrication of the MOS semiconductor integrated circuit structure, the p-type doped surface region 34 formed by the selectively masked boron ionimplantation is present in the upper surface of the substrate except around the peripheral edges of the dielectric layer 22, 24 from which it is controllably separated by a distance w. This distance is, in turn, a function of the width of the silicon oxide tapered sidewall 28, and is typically in the order of 0.3 to 1.5 microns.

Next, as shown in Figure 2(f), thick oxide regions 36 are selectively thermally grown, using the dielectric layer as an oxidation barrier, so that a mesa 38, as it is designated in United States Patent No. 3,751,722, is formed in the substrate by the movement of the thick oxide regions 36 and the self-aligned underlying p-type doped surface region 34 into the upper surface of the substrate. A specific combination of diffusion (drive-in) time and temperature and subsequent oxidation time and temperature can be selected by the process engineer to achieve a structure in which the p-type region 34 in the final structure either is separated from the active mesas, adjacent the active mesas, or just slightly extending into the active mesas, as desired by the process engineer.The selection of these process parameters is within the competence of the process engineer having ordinary skill in the art such that those parameters are not further specified in this specification.

The improvement in minimizing the lateral spreading or diffusion of the p-type doped region 34 as attained in this manner can be seen by comparing the structure shown in Figure 2(f) with the cross-sectional diagram of Figure 1 of a conventionally fabricated MOS FET along the channel-width direction in which, as noted, the boron doped region 14 has laterally diffused well into the active channel areas at the edge locations.

The structure shown in Figure 2(f) is then completed along conventional lines such as by a process similar to those disclosed in the aforesaid patent and in the aforesaid Richman publication.

Namely, the silicon nitride layer 22 is removed as by etching in a hot phosphoric acid, thereby exposing the thin layer of silicon dioxide which is also removed chemically. The structure is cleaned and a new thin layer of silicon dioxide is grown that will be used as the gate insulator. Thereafter, the wafer is given a high-temperature anneal and a thin layer of polycrystalline silicon (not shown in the drawings) is deposited over the entire surface of the wafer. That polycrystalline silicon layer is selectively etched away by a known procedure to leave polysilicon gate areas such as 40, which are then used as an implantation mask, in conjunction with the thick oxide layers, to mask against the effects of an implantation of n-type impurities to selectively form the drain, source, and n+ connection regions.

A layer of heavily phosphorus-doped silicon dioxide 42 is then pyrolitically deposited over the entire surface of the wafer (Figure 2(g)), and the wafer is heated at a high temperature in a dry nitrogen ambient. At this point in the process, the n+ source and drain regions 44 and 46 and n+ silicon interconnections (not shown in the drawings) exhibit a junction depth typically in the order of one quarter to one micron.

Since Figure 2(g) is viewed in the channelwidth direction, the source and drain regions 44, 46 are not seen in this view. These regions are, however, shown in the cross section of Figure 3, which is viewed in the channel-length direction along a plane 90C displaced from the channelwidth plane along which Figures 2(a)--2(9) are viewed. As seen in Figure 3, openings are selectively made in the phosphorus-doped silicon dioxide layer 42 and a metal, such as aluminum, is deposited and selectively etched to make metallization contacts 48 to the source and drain regions 44, 46 and to the doped polycrystalline silicon gate electrode 40.As viewed in the channel-length direction, as in Figure 3, the ptype doped surface regions 34 may extend sufficiently to contact the source and drain regions, as in the aforesaid patent while terminating at a point spaced from the active channel regions as viewed in the channel-width direction, as seen in Figure 2(g).

Figures 4(a)-4(c) illustrate several intermediate steps in the fabrication of an integrated circuit MOS device according to an alternative process of the present invention. In this process, as shown in Figure 4(a), a dielectric layer consisting of, as in the prior embodiment, a layer 22 of silicon nitride overlying a thin layer 24 of silicon dioxide is selectively formed on the upper surfaces of a silicon substrate 10.

Alternatively, the dielectric layer may consist solely of silicon nitride. Next, the silicon nitridesilicon oxide dielectric layer is used as an oxidation barrier to selectively thermally grow a thick (4,000A to 1 2,000A) layer of silicon dioxide (not shown in the drawings). That layer is subsequently etched away, leaving a mesa-like structure 50 on which is formed the silicon nitride dielectric layer. Alternatively, instead of growing the thick silicon dioxide layer and etching it away, the structure shown in Figure 4(a) can also be achieved by selectively etching away the surface of the silicon substrate to a depth of, for example, 2,000A to 6,000A using the patterned silicon nitride layer as a mask through the use of an isotropic chemical etch such as, for example, hydrofluoric and nitric acids.

Next, a further thick layer of silicon dioxide is chemically vapor deposited over the structure and, in the same manner as in the first embodiment, the structure is exposed to a directional reactive ion-etching procedure to remove the chemically-vapor-deposited silicon dioxide layer overlying the flat portions of the structure, leaving, as shown in 4(b), silicon dioxide tapered sidewalls 28 at the edges of the mesas, such as mesa 50, that exist at this stage of the processing sequence. A thin layer of silicon dioxide 30 is then thermally grown on the exposed (flat) portions of the silicon substrate and a boron implantation is performed through the thin oxide layer into the regions of the silicon directly under the thick oxide.During this implantation step, the thicker dielectric layer 22, 24 and the tapered sidewalls 28 act as implantation barriers, separating the implanted boron regions 34 formed as a result of this implantation step from the active mesas. The resulting structure at this point of the fabrication sequence is shown in Figure 4(b).

Next, a thick silicon oxide layer 52 is selectively grown (or regrown) to a thickness of between 4,000A to 1 2,000A, resulting in the structure shown in Figure 4(c), which is similar to the structure shown in Figure 2(f), except that the top surface of the thick silicon dioxide layer 52 in Figure 4(c) is approximately at the same level of the top surface of the silicon mesa in the active channel area, as opposed to being slightly higher, as it is in Figure 2(f). The characteristics of the structure of Figure 4(c) are, however, similar to the characteristics of the structure of Figure 2(f), and both structures have the advantage of allowing the process engineer to adjust the position of the edge of the doped surface region relative to the edge of the active mesas.The structure of Figure 4(c) can subsequently be finished into a completed integrated circuit through the use of the same or similar techniques as employed to complete the fabrication of the first embodiment.

It will thus be appreciated that by virtue of the present invention a semiconductor integrated circuit is provided in which the doped surface regions, which prevent the formation of parasitic field inversion, as taught in the aforesaid U.S.

patent, are spaced by a controllable extent away from or adjacent to the active channel regions or mesas of active MOS devices. In this manner, the significant advantages obtained by the structure taught by said patent are maintained and are in addition now amenable for use in integrated circuits in which the channel widths are significantly reduced.

It will also be appreciated that whereas the invention has been disclosed with respect to several embodiments thereof, modifications may be made in those embodiments without necessarily departing from the spirit and scope of the invention.

Claims

1. A semiconductor circuit MOS structure comprising a substrate of a first conductivity type, source and drain regions of an opposite conductivity type formed in an upper surface of said substrate, an active channel region between said source and drain regions, a thick oxide region selectively overlying portions of said substrate adjacent said active channel regions, a doped surface layer of said first conductivity type underlying and aligned with said thick oxide region, said doped surface layer, as viewed in cross section in the channel-width direction, substantially lying outside or adjacent to said active channel region.

2. The integrated circuit of claim 1, in which said doped surface layer contacts at least one of the source and drain regions as viewed in cross section in the channel-length direction.

3. The integrated circuit structure of claim 2, in which said first conductivity type is p-type, and said doped surface layer is formed by selectively implanting boron ions into the upper surface of said substrate.

4. The integrated circuit structure of claim 2, in which the width of said active channel region is less than 4 microns.

5. The integrated circuit structure of claim 3, in which said doped surface layer is spaced from or adjacent to the outer borders of said active gate region, as viewed in the channel-width direction.

6. The integrated circuit structure of claim 3, in which said doped surface layer extends to but not inside the outer borders of said active channel region, as viewed in the channel-width direction.

7. A method for fabricating an MOS integrated circuit structure comprising the steps of forming a patterned dielectric layer over selected portions of a major surface of a silicon substrate of a first conductivity type; forming a tapered sidewall extending downward from said dielectric layer to said substrate major surface; employing said dielectric layer along with the relatively thick part of said tapered sidewall as a mask, implanting ions of said first conductivity such that ions pass through only the relatively thin outer part of said tapered sidewall into said substrate to selectively form a doped layer of said first conductivity type in the major surface of said substrate, the width of said dielectric establishing the width dimension of an active channel region of an MOS device, the inner end of said doped layer being spaced away from or terminating adjacent to the outer width limits of said active channel region.

8. The method of claim 7, in which said step of forming said tapered sidewall includes the steps of depositing a layer of silicon dioxide over said patterned dielectric layer and the upper surface of said substrate, and thereafter selectively removing portions of said deposited oxide layer to leave said tapered sidewall.

9. The method of claim 8, in which said selective removal of said deposited oxide layer includes a directional reactive-ion-etching step.

10, The method of claim 8, further comprising the step of thermally growing a thin layer of silicon oxide over the remaining portions of said major surface of said silicon substrate that extends from the lower end of said tapered sidewall prior to said implantation step.

11. The method of claim 10, further including the step of thermally growing a thick oxide layer self-aligned with and overlying said doped layer at pre-selected parameters and conditions such that the lateral diffusion of said doped layer is limited to terminate at a preselected distance from the borders of or adjacent to said active channel region, as viewed in the channel-width direction.

12, The method of claim 7, in which the formation of said tapered sidewall includes the steps of forming an active mesa region, depositing a thick layer of oxide over said mesa and substrate, and subjecting the substrate to an etching procedure to selectively remove portions of said thick oxide layer.

13. The method of claim 12, further comprising the step of thermally growing a thin layer of silicon oxide that extends from the lower end of said tapered wall prior to said implantation step.

14. The method of claim 13, further including the step of thermally growing a thick oxide layer self-aligned with and overlying said doped layer at preselected parameters and conditions such that the lateral diffusion of said doped layer is limited to terminate at a preselected distance from the borders of or adjacent to said active channel region as viewed in the channel-width direction.

1 5. A method for fabricating an MOS integrated circuit structure comprising the steps of forming a mesa on a surface of a substrate of a first conductivity type, with a dielectric layer being formed on an upper surface of said mesa, forming a varying-thickness-oxide sidewall extending downward from said dielectric layer to the surface of said substrate, employing said dielectric layer along with the relatively thick part of said sidewall as a mask, implanting ions of said first conductivity such that ions pass through only the relatively thin part of said tapered sidewall into said substrate to selectively form a doped layer of said first conductivity type in said surface of said substrate, the width of said dielectric layer establishing the width dimension of an active channel region of an MOS device, the inner end of said doped layer being spaced away from or terminating adjacent to the outer width limits of said active channel region.

16. The method of claim 15, in which the step of forming said sidewall includes the steps of depositing a thick layer of oxide over said mesa and said substrate and subjecting the substrate to an etching procedure to selectively remove portions of said thick oxide layer.

17. The method of claim 15, further comprising the step of thermally growing a thin layer of silicon oxide that extends from the lower end of said sidewall prior to said implantation step.

18. The method of claim 17, further including the step of thermally growing a thick oxide layer self-aligned with and overlying said doped layer at preselected parameters and conditions such that the lateral diffusion of said doped layer is limited to terminate adjacent to or at a preselected distance from the borders of said active channel region, as viewed in the channel-width direction.

1 9. The invention claimed in any of the preceding claims and substantially as herein described with reference to the accompanying drawings.