GB2121627A - Direct digital synthesiser - Google Patents

Abstract

To minimise generation of spurious signals, the direct digital synthesiser arrangement of Fig. 1 is modified by switching in a random or pseudo-random fashion between two DACs, or between two function generators (with similar control of the DAC reference voltage), or between two function-generator-DAC pairs, or by randomly or pseudo- randomly varying a scaling factor applied prior to the DAC (with similar control of the DAC reference voltage). <IMAGE>

Description

SPECIFICATION Direct digital synthesiser This invention relates to direct digital synthesisers.

There are various kinds of synthesiser but the present invention is concerned exclusively with direct digital synthesisers. This kind of synthesiser includes means for producing a digital representation of a required signal and a digital-to-analogue converter responsive to the digital representation for providing the signal required.

Direct digital frequency synthesisers comprise a clock pulse generator and a digital number generator which provides a digital number K effectively representing the frequency of a signal to be synthesised. In operation, the number K is added each clock cycle of the system to an accumulator which fills progressively and linearly during each cycle so as effectively to give the phase of the waveform 8 = ZK. This number XK is used as the input to a digital function generator, which may be a read only memory (ROM), the output of which is a further digital number which is fed to a digital-to-analogue converter (DAC) which generates the required output waveform samples.

Thus when XK reaches a number representing 0 = 2'r, the accumulator empties and starts to recharge so that the phase continues to change at the required rate. Because the set of numbers EK is bounded and integral, then after some period of time a particular value of K must recur, and an overall repetition then occurs at a subharmonic of the frequency being synthesised. For the generation of an unmodulated sinewave the set of numbers fed to the DAC repeats with this overall repetition period.

Now there is a limitation to the accuracy of the DAC in generating the required waveform and also there are transients (glitches) between samples which are equivalent to errors in the DAC output. Since the errors due to the limited accuracy of the DAC and from the glitches repeat with the overall periodicity described above, then the energy falls into a line pattern in the spectrum of the synthesised signal. These lines are unwanted spurious signals and very careful engineering is required to minimise the magnitude of these spurious signals relative to the wanted carrier signal, and in practice it may not be possible to make the spurious signals sufficiently small.

It is an object of the present invention to remove these spurious signals or at least reduce them to an acceptable level.

According to the present invention a direct digital sythesiser arrangement comprises, a digital number generator, a clock pulse generator, a digital accumulator responsive to the digital number generator and to the clock pulse generator for accumulating a digital number generated at the clock pulse rate, a function generator responsive to the digital accumulator for providing in dependence upon the accumulated digital number a predetermined digital wave form function, a digital-to-analogue converter (DAC) effective to convert the predetermined digital waveform function to a corresponding analogue waveform function, and random control means operable randomly to control operation of the DAC thereby to avoid or miminise generation of spurious signals.

According to one embodiment of the invention two DACs may be provided in operative association with switch means operable randomly under control of the random control means so that one or other of the DACs are connected in circuit at any instant.

The switch means may be arranged to switch one or other of the DACs into circuit or to control the clock signal or DAC reference voltage for the same purpose.

Since no two DACs are precisely the same.

Operating variations occur in operation of the foregoing embodiment, which break up regularly occuring signal patterns responsible for the production of spurious signals.

According to another embodiment of the invention the arrangment may include variable scaling means via which digital signals are fed from the function generator to the DAC, the scaling means and the DAC being responsive synchronously to a control signal from the random control means so that the scaling factor introduced by the scaling means is changed randomly and the operation of the DAC is changed synchronously therewith so as to compensate for the scaling factor changes.

With the arrangement according to this embodiment of the invention, regularly occuring signal patterns responsible for the production of spurious signals are suppressed.

As a variation of the foregoing embodiment, two function generators respectively affording different functions may be used in association with switch means responsive to the random control means for randomly connecting one or other of the two function generators in circuit, and for changing synchronously the operating characteristics of the DAC to compensate for the function differences between the function generators, whereby regularly occuring signal patterns responsible for the development of spurious are suppressed.

According to a further embodiment of the invention two function generators and two DACs may be provided in operative association with switch means thereby to provide alternative parallel digital signal paths, the switch means being operated randomly in operation of the arrangement under control of the random control means so that the said paths participate in the circuit alternately.

Thus it will be appreciated that with this embodiment also, regularly occuring signal patterns responsive for the production of spurious signals are suppressed.

Since the errors in a DAC output signal for different steps are largely independent (i.e.

not directly related to each other) then by making appropriate changes to the DAC operation in accordance with the foregoing embodiments of the invention, the periodic nature of the errors are disturbed so that the line structure spurious content of the signal is broken up into a more generally noise like form. The peak level of spurious content in the signal in a small bandwidth (typically noise power in spectrum of a synthesiser is measured or specified in bandwidths of 1 Hz to 3 Khz) is very much reduced.

Some embodiments of the invention will now be described solely by way of example with reference to the accompanying drawings in which: Figure 1 is a generally schematic block diagram of a direct digital synthesiser; Figure 2 is a somewhat schematic block diagram showing a part of the circuit of Fig. 1 modified to effect random DAC control; Figure 3 is a generally schematic block diagram of a part of the diagram shown in Fig. 1 modified to effect random control of the DAC in an alternative manner; Figure 4 is a block schematic diagram showing parts of the diagram shown in Fig. 1 modified to effect random control of a DAC in an alternative manner; and Figure 5 is a block schematic diagram showing parts of the diagram of Fig. 1 modified in a further alternative manner to effect random control of the DAC.

Referring now to Fig. 1, a direct digital synthesiser comprises a digital number generator 1, an accumulator 2 and a clock pulse generator 3. Digital numbers generated in the number generator 1 are fed to the accumulator 2 at the clock frequency produced by the clock pulse generator 3. The digital number accumulated in the accumulator 2 thus increases linearly until the accumulator is full.

The process is continuously repeated and each cycle represents one cycle of the signal to be synthesised. Since the accumulator 2 has a finite capacity it will be appreciated that the frequency produced will be dependent on the number produced by the number generator 1. An output signal from the accumulator 2 representing the accumulated digital number is fed to a digital function generator 4 which in the present example is arranged to receive the accumulated digital signal and to produce a sin function but any other function could be produced. In practice the function generator may comprise a digital look up table including a ROM.Thus it will be appreciated that if the number produced hy the number generator 1 is K the accumulated digital number in the digital accumulator 2 will represent the phase of the signal to be generated and is hereinafter referred to as 0 = T.K. If the function generator 4 is arranged to produce a sin wave then the function generator will produce a digital signal equivalent to sin Q. An output signal from the function generator 4 is fed to a digital-to-analogue converter 5 to produce on a line 6 an equivalent analogue signal which is fed to a low pass filter 7 to produce an output signal on an output line 8.

As hereinbefore explained, various synthesiser embodiments are proposed which seek to randomise operation of the DAC. Since true randomness is difficult to achieve in a controlled wave the requirement can be effectively met with a pseudo-random change in which repetition of the pseudo-random pattern is over a very much longer time than any measurement integration time to be applied to characterising spurious signals. Thus where random changes are referred to in the present specification such changes are intended to include pseudo-random changes.

As hereinbefore explained, the limited number of bits in the DAC 5 limits the accuracy with which samples are generated and transients occur between voltage steps. These error voltages recur at rates which lead to spurious signals within the band of frequencies which it is desired to synthesise. Since the errors produced due to a limited number of bits would be the same from one DAC to another, if the voltage generated corresponded exactly to the digital number there would be no advantage in changing from one DAC to another in a random fashion. However the voltages do not correspond exactly and typically they may be in error by a voltage equivalent to plus or minus half of a least significant bit, and these errors are different from one DAC to another. Also the transients will not correspond precisely between the two DACs.Hence it will be appreciated that random switching between two or more DACs will give some measure of benefit. An arrangement which switches between two DACs is shown in Fig. 2.

The arrangement of Fig. 2 comprises a pair of ganged switches 9 and 10 which are operated randomly by a random control unit 1 1 so that either a DAC 12 or a DAC 13 is connected in circuit between the function generator 4 and the low pass filter 7.

With the foregoing arrangement the inherent error from the limited number of bits remains repetitive and the transients will tend to be simiiar since each DAC will be making the same bit transitions at a given point in the overall repetition cycle. The improvement obtained will therefore be limited by these factors. Nevertheless this improved system is relatively simple and the choice of DAC is made externally of the DAC as shown in Fiq.

2, by the switches 9 and 10. Alternatively however the DACs may be selected by controlling a DAC reference voltage or clock signal inputs to the DAC as appropriate.

Many DACs have the facility for the provision of a reference voltage or current from an external source and this reference voltage or the clock signals may be used as just before explained to switch a DAC on or off.

Alternatively if this reference is changed by a controlled amount from step to step randomly between two (or more) known levels, then the digital word required to generate the given output voltage must be changed accordingly, e.g. by digital multiplication in a scaling circuit. An arrangement which operates on this principle is shown in Fig. 3 and comprises a scaling circuit 14 which together with a DAC 1 5 is serially connected between the function generator 4 and the low pass filter 7.

The scaling circuit 14 and the DAC 1 5 are operated by signals applied on lines 16 and 1 7 respectively from a random control unit 1 8. With this arrangement the scaling factor provided by the scaling circuit 1 6 is changed randomly and the operating characteristics of the digital-to-analogue converter 1 5 are also changed by controlling the reference voltage to compensate for the scaling factor changes and the signals- applied to the lines 1 6 and 1 7 for synchroniously effecting these changes are produced by the random control unit 1 8. This mode of operation it will be appreciated, is made possible by the provision on the DAC of a voltage or current reference terminal to be fed from an external source. This terminal is connected to line 1 7 and by changing the reference signal on line 1 7 the characteristics of the DAC may be changed. However with the system as just before described there still remains a repetitive reoccurance of the errors due to rounding truncation or approximation in the function generator 4 which in practice is a look up table which includes a ROM.

These errors due to rounding truncation or approximation are however normally quite small compared with errors introduced by the DAC. In order however to cope to some extent with these small errors an arrangement may be provided as shown in Fig. 4 wherein two function generators 1 9 and 20 are provided operatively associated with switches 21 and 22. The switches 21 and 22 are operated sequentially so as to select either the function generator 1 9 or the function generator 20.

The selected function generator is arranged to feed a DAC 23 which feeds the low pass filter 7.

By providing separate function generators 1 9 and 20 and thus separate look up tables which are randomly selected due to operation of the switches 21, and 22 under control of a random control unit 24, small spurious signals due to periodicity in the function generators are largely removed. To compensate for difierences between the function generators 1 9 and 20 the operating characteristics of the digital-to-analogue converter 23 are changed synchrnnously by means of a signal applied from the random control unit 24 to the DAC 23 via a reference voltage line 25.

In the systems using one DAC as shown in Fig. 3 and Fig. 4, if a small change in the reference signal on the line 1 7 or the line 25 is made, the coding and errors for low values of the output signal will be unchanged because the resolution will not be sufficient to permit fine enough changes to represent those required for the change of reference. So although a change in the output will occur because of the change of reference, the errors will still be the same and so a periodic residual spurious content will remain. Alternatively if the change in reference is made large to avoid this then the effective number of bits for the larger reference input is reduced and this means that the errors in generating output waveform samples are increased with consequent increase in overall noise.

These effects can be removed or reduced by using a separate function generator with each of a number of DACs with random switching between these circuits. Such an arrangement is shown in Fig. 5 and comprises two circuits connected between a pair of switches 26 and 27. One circuit comprises a function generator 28 and a digitial-to-analogue converter 29 and the other circuit comprises a function generator 30 and a digital-to-analogue converter 31. The switches are operated synchronously under control of a random control unit 32 and an output signal from one circuit or the other is fed to the low pass filter 7. The two DACs 29 and 31 should preferably be of different construction and utilise a different form of coding or should be run with different reference voltages.The function generators 28 and 30 should be matched to the characteristic of the DAC with which they are associated to give minimum error for each sample generated. This system permits reduction of overall errors and of elements of periodicity so that the level of spurious signals and of noise is correspondingly reduced. It will be appreciated by those skilled in the art that the particular system chosen to implement ran dorusness will depend upon the characteristics of the devices available including any switching or control and upon whether the switching can be carried out within the function of the other blocks or whether separate switches are required. It will also be appreciated by those skilled in the art, that various types of random control unit digitial-to-analogue converter, function generator, number generator and low pass filter are readily available and the type chosen will vary in accordance with requirements of design.

Claims (7)

1. A direct digital synthesiser arrangement comprising a digital number generator, a clock pulse generator, a digital accumulator responsive to the digital number generator and to the clock pulse generator for accumulating a digital number generated at the clock pulse rate, a function generator responsive to the digital accumulator for providing in dependence upon the accumulated digital number a predetermined digital wave form function, a digital-to-analogue converter (DAC) effective to convert the predetermined digital waveform function to a corresponding analogue waveform function, and random control means operable randomly to control operation of the DAC thereby to avoid or minimise generation of spurious signals.

2. A direct digital synthesiser as claimed in claim 1 comprising two DACs in operative association with switch means the switch means being operable randomly under control of the random control means so that one or other of the DACs are connected in circuit at any instant.

3. A direct digital synthesiser arrangement as claimed in claim 2 wherein the switch means are arranged to switch one or other of the DACs into circuit or to control the clock signal or DAC reference voltage for the same purpose.

4. A direct digital synthesiser as claimed in claim 1 including variable scaling means via which digital signals are fed from the function generator to the DAC, the scaling means and the DAC being responsive synchronously to a control signal from the random control means so that the scaling factor introduced by the scaling means is changed randomly and the operation of the DAC is changed synchronously therewith so as to compensate for the scaling factor changes.

5. A direct digital synthesiser as claimed in claim 1 comprising two function generators respectively affording different functions and operatively associated with switch means responsive to the random control means for randomly connecting one or other of the two function generators in circuit and for changing synchronously the operating characteristics of the DAC to compensate for the function differences between the function generators whereby regularly occurring signal pattern responsible for the development of spurious signals are suppressed.

6. A direct digital synthesiser as claimed in claim 1 comprising tllJo function generators and two DACs in operative association with switch means thereby to provide alternative parallel digital signal paths, the switch means being operated randomly in operation of the arrangement under control of the random control means so that the paths participate in the circuit alternately.

7. A direct digital synthesiser substantially as hereinbefore described with reference to the accompanying drawings.