GB2119606A - Improvements in and relating to television type displays - Google Patents
Improvements in and relating to television type displays Download PDFInfo
- Publication number
- GB2119606A GB2119606A GB08200612A GB8200612A GB2119606A GB 2119606 A GB2119606 A GB 2119606A GB 08200612 A GB08200612 A GB 08200612A GB 8200612 A GB8200612 A GB 8200612A GB 2119606 A GB2119606 A GB 2119606A
- Authority
- GB
- United Kingdom
- Prior art keywords
- display
- sequence
- storage device
- pictures
- static storage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/76—Television signal recording
- H04N5/907—Television signal recording using static stores, e.g. storage tubes or semiconductor memories
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
- G09G5/39—Control of the bit-mapped memory
- G09G5/395—Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/02—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the way in which colour is displayed
- G09G5/024—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the way in which colour is displayed using colour registers, e.g. to control background, foreground, surface filling
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Controls And Circuits For Display Device (AREA)
Abstract
A system for displaying on a television a picture containing moving picture content corresponding to the display of a sequence of pictures in a moving picture display, comprises:- a. a television monitor b. a static storage device mounted on a card or in a frame or similar to allow for carriage and/or postage and the like, c. means for recording in binary form electrical signals in the static storage device, corresponding to the first of a sequence of pictures which together make up a so-called moving picture display together with further information in a series of discrete locations, which further information corresponds to the differences only between the current picture and the next in the said sequence so as to produce a modified version of the current picture for display next in turn, d. the static storage device having provision for the storage of information concerning the time to lapse between the display of the current and the next picture in the said sequence, e. reading means adapted to receive the static storage device having signals stored thereon and for reading same so as to produce the electrical output signal corresponding to the first and subsequent of a sequence of pictures, and f. connection means for connecting the output of the reading means to the television monitor to display the output signals in the form of a sequence of pictures. Conveniently the static storage device is a solid state storage device in the form of an erasible programmable memory (EPROM). <IMAGE>
Description
SPECIFICATION
Improvements in and relating to television type
displays
Field of the Invention
This invention concerns television based
display systems, particularly for displaying a
sequence of pictures or words for example for advertising or tuition purposes. However, it is to be understood that the invention is not limited to this particular type of application and may be used for the display of information corresponding to any sequence of pictures which can then appear as a sequence of moving pictures as in a cinematographic film.
Background to the Invention
It is known to store signals corresponding to television type pictures on a magnetic tape or disc and to obtain the signals by replaying the stored information from the disc or tape. By storing a sequence of pictures and displaying them in sequence in rapid succession so a moving picture display is obtained.
It is also known to digitise a static television picture and code the digitised signal in binary form and store this in a static binary store such as a shift register based storage device.
It is an object of the present invention to provide a system and device by which a moving picture television display can be obtained from a so-called static storage device.
It is a further object of the present invention to provide a system by which different moving picture television-type displays can be supplied in package form to remotely located television display units.
Summary of the Invention
According to one aspect of the present invention a system for displaying on a television a picture containing moving picture content corresponding to the display of a sequence of pictures in a moving picture display, comprises:~
a. a television monitor
b. a static storage device mounted on a card or in a frame or similar to allow for carriage and/or postage and the like,
c. means for recording in binary form electrical signals in the static storage device, corresponding to the first of a sequence of pictures which together make up a so-called moving picture display together with further information in a series of discreet locations, which further information corresponds to the differences only between the current picture and the next in the said sequence so as to produce a modified version of the current picture for display, next in turn,
d. the static storage device having provision for the storage of information concerning the time to lapse between the display of the current and the next picture in the said sequence,
e. reading means adapted to receive the static storage device having signals stored thereon and for reading same so as to produce the electrical output signal corresponding to the first and subsequent of a sequence of pictures, and
f. connection means for connecting the output of the reading means to the television monitor to display the output signals in the form of a sequence of pictures.
Conveniently the static storage device is a solid state storage device in the form of an erasible programmable memory (EPROM).
Preferably information is stored in the storage device corresponding to the colour required in any region irl the displayed pictures and the television monitor is a colour television monitor.
Where the monitor is a standard broadcast television receiver (as will commonly be the case#) signal generating and modulating circuit means is conveniently provided for generating a modulated
RF signal for application to the ariel input socket of the receiver.
The invention will now be described by way of example with reference to the accompanying drawings in which:~
Fig. 1 is a general layout diagram of a complete system for generating signals corresponding to a sequence of pictures and storing same on an
EPROM and EPROM reading means for converting stored signals for display on a television monitor.
Fig. 2 is a block circuit diagram of the overall system,
Fig. 3 illustrates the relationship between the signals defining address and the data for the address in a memory,
Fig. 4 is a circuit diagram of the central processor unit based on a Z80 micro-processor,
Fig. 5 is a circuit diagram of the system random access memory and read only memory,
Fig. 6 is a circuit diagram of the video encoder,
Fig. 7 is a circuit diagram of the multiplexer for producing a signal known as HRST,
Fig. 8 is a circuit diagram of the video random access memory,
Fig. 9 is a circuit diagram of the address decoder circuits, and
Fig. 10 is a circuit diagram of the auto address circuits.
Detailed Description of the System and Drawings
The colour display system described here is a (Z80) controlled 15 colour graphic display system.The video output can drive any domestic colour t.v. set, of any size.
Information describing the display is fed to the processor from either an E.P.R.O.M. (erasable read only memory) card or alternatively from another (Z80) based computer.
The end user only requires the display unit fitted with an EPROM card to display any pre written sequence, the sequence will automatically be repeated.
The program that is held on the EPROM card is produced from an internal process, as shown on sheet 1.
A production program is loaded into a computer such as the TRS 80 that is connected to a display system.
The production program enables the operator to draw shapes and produce text in any of the available colours and styles very quickly, each individual part of the display can be altered. The method is similar to making a flip book cartoon, each image that is different from the previous one is 'saved' into a memory area along with other data such as time before displaying the next "page". A page can be any part of the display thus only differences between images need to be 'saved'. The data required for the sequence is then program into an EPROM(S). The programmed
EPROM is fitted into an EPROM card, the EPROM card is in turn put into the display system. The display will begin when a reset button is pressed after powering up the system, it will only stop when the system is switched off.
The main sections within the display system are shown on sheet 2. The following is a step by step description of how the data on the EPROM card becomes a recognisable image on the television set.
After applying power to the system via the
P.S.U., the reset button is depressed this forces the C.P.U. (central processing unit) to get its first instruction from the system ROM (box A). The system ROM is an EPROM that has the same program in all display systems, unlike the EPROM card which contains different programs for different displays. The program on the system
ROM contains routines that are commonly used by the display system time delays etc etc.
In the same box as the system ROM is the system RAM this is the area in which the CPU stores temporary data or any data that is not part of the display image.
The instruction that the CPU gets from the system ROM is then executed and the CPU gets its next instruction, this may tell the CPU to get the first piece of data from the EPROM card and to put that data into the video R.A.M. (box B).
Address lines from the CPU and the auto add (box C) go to a section called the multiplexer (box
D) this is acting as a selector choosing which address lines to let out the other side and into the video RAM. The address decoder (box E) helps define which part of the video RAM is being written to or read from.
The purpose of the auto address is to count from 0 to 12288 in an exact relationship with the spot moving across the television screen. Each number uniquely defines a single point in the video RAM. Any data that has been put into this unique location is then read from the RAM and fed to the video encoder this combines the data that is being sent to the television and so any changes in this data will be reflected by changes of colour on the television screen.
Sheet 3 shows in a very simplified way this process.
Location (3, 5) of the video RAM has a number 3 in it, this was put here by the CPU, the auto add will then be counting first 00 then 01, 02, 03, 04, all the way to 5,7, any data that is in these locations will be outputted to the video encoder which combines this data with the signals that the television will need.
The number that each address holds tells the video encoder what colour that location on the screen is to be.
If the number changes then the colour of that part of the screen changes and so a combination of numbers when read from the video RAM will produce a recognisable shape on the television.
All the timing signals are fed to the auto add and the CPU sections from the video encoder.
The main sections within the display system are shown on sheet 2. The following is a step by step description of how the data on the EPROM card becomes a recognisable image on the television set.
After applying power to the system via the
P.S.U. the reset button is depressed this forces the
C.P.U. (central processing unit) to get its first instruction from the system ROM (box A). The system ROM is an EPROM that has the same program in all display systems, unlike the EPROM card which contains routines that are commonly
used by the display system time delays etc etc.
In the same box as the system ROM is the system RAM this is the area in which the CPU
stores temporary data or any data that is not part
of the display image.
The instruction that the CPU gets from the
system ROM is then executed and the CPU gets its
next instruction, this may tell the CPU to get the
first piece of data from the EPROM card and to put
that data into the video R.A.M. (box B).
Address lines from the CPU and the auto add
(box C) go to a section called the multiplexer (box
D) this is acting as a selector choosing which
address lines to let out the other side and into the
video RAM. The address decoder (box E) helps
define which part of the video RAM is being
written to or read from.
The purpose of the auto address is to count
from 0 to 12288 in an exact relationship with the
spot moving across the television screen. Each
number uniquely defines a single point in the
video RAM. Any data that has been put into this
unique location is then read from the RAM and fed
to the video encoder this combines the data that is
being sent to it from the video RAM with the
signal that is being sent to the television and so
any changes in this data will be reflected by
changes of colour on the television screen.
Sheet 3 shows in a very simplified way this
process.
Location (3,5) of the video RAM has a number
3 in it, this was put here by the CPU, the auto add
will then be counting first 00 then 01, 02, 03, 04,
all the way to 5, 7, any data that is in these
locations will be outputted to the video encoder
which combines this data with the signals that the
television will need.
The number that each address holds tells the
video encoder what colour that location on the
screen is to be.
If the number changes then the colour of that part of the screen changes and so a combination of numbers when read from the video RAM will produce a recognisable shape on the television.
All the timing signals are fed to the auto add and the CPU sections from the video encoder.
The graphic pictures that this system will produce are each made up of small squares. There are 12,288 individual squares to use. Any of these can be illuminated in any of the 1 5 colours available. If every square is given the same value in the video RAM then the entire screen of the television set will be all one particular colour.
The ability to give an impression of movement is achieved because of the very fast speed that the system operates at. Every time a new piece of information is put into the video RAM an immediate change is reflected on the television screen.
The internal program that was mentioned earlier is the tool by which pictures are drawn. In conventional computer displays the picture is built by a single program that has to be written for that particular image. This internal program gives the ability to cut out long, time consuming methods by giving the operator a system that can already print letters, squares, triangles, lines, circles etc and only requires parameters such as how big, what colour, and where.
Description of Circuit Parts C.P.U.
The central processing unit is a Z80 (A) type (iC 35) this is run at 3.54 MHz, the clock is supplied from the video circuits described later.
Address lines, data lines and some control signals from the C.P.U. are fed through buffers the outputs from these buffers are capable of driving further circuits which would normally put a greater work load onto the C.P.U.
An or gate is used to combine WR, RD, and
MREQ signals from the C.P.U. to produce two new signals called WRx and RDx. These two signals define the direction the data is travelling.
The watt input of the C.P.U. is controlled by
HRST, a signal which is supplied from the video circuit this ensures that the C.P.U. is not working during a displayable part of T.V. line and so ensures that the T.V. picture itself is not contaminated by the C.P.U. moving data during this time.
System RAM/ROM
The 2716 2Kx8 bit eraseable read only memory contains a short program that instructs the C.P.U.
immediately the system is switched on.
Two 1 Kx4bit random access memories are arranged to provide bits this area memory is available to the C.P.U. to store temp values or results of calculations.
Auto Address
The HRST signal from the video circuits this is used to control a high frequency oscillator formed by R5, R6, Dl, C20, and IC 14, the control from
HRST ensures that the phase of the clock is always the same at the start of each line.
The output from this oscillator is very precise 2.45 MHZ which is fed to a dual four bit counter the outputs from this counter is passed through a 241 type buffer to provide BO-B6. HRST is also applied to an AND gate this inverts the HRST and applies this signal to a decade counter. The decade counter is configured to count every three lines the pulse from this is fed to another dual 4 bit binary counter this provides counting from 0 to 96 and after going through the buffer IC20 the output at PIN 7 is changed to provide the correct start address code when the signals BO to B14 are decoded.
HRST is applied to the counter providing B0-B6 to reset the counters at the end of each line.
VRST a signal from the video circuits is applied to the other counter at the end of each frame.
Address Decoder
The purpose of the address decoder is to turn certain specific circuits on or off. This is accomplished by the 74us138 3 to 8 line decoders. The first two decode the signals Ol 0-Ql 3 the combinations of these lines will allow one of the lines E0~E11 to be active each one of these enables a particular video RAM.
The other 74us138 is used to decode the address lines A12 to A14 from the C.P.U. The outputs are used to select one of the four E.P.R.O.M.S. ENPRA, ENPRB, ENPRC, ENPRD, or further decoding to select the system R.A.M. or the system R.O.M.
The signals select and ANBR are used to select various buffer combinations of buffers.
Video RAM
The video RAM portion of the system consists of twelve random access memories. Each memory will hold enough data for 128x8 PICELLS. The individual IC8S are enabled by the signals from the address decoder when enabled data can be read from or written to a specific address within that l.C.
Data from the video RAM can be passed to and from the C.P.U. or alternatively via the buffer to the video circuit.
Multiplexer
Inputs AO--A13 from the C.P.U. address bus and inputs B0-B 13 from the auto address bus are selected to be output as Q0-Ql 3 depending on the state of the invhrst signal This allows the
C.P.U. access to the video RAM only during a
nondisplayable part of a line.
Video Encoder
This circuit accepts the INV, R, G, and B signals from the video RAM and combines them with the synchronizing signals the video signal is then
passed to the modulator via level control circuitry
and finally to the television.
The signals HRST, VRST, and clock are all
synchronized with the T.V. signals.
Claims (4)
1. A system for displaying on a television a picture containing moving picture content corresponding to the display of a sequence of pictures in a moving picture display, comprising;
a. a television monitor
b. a static storage device mounted on a card or in a frame or similar to allow for carriage and/or postage and the like,
c. means for recording in binary form electrical signals in the static storage device, corresponding to the first of a sequence of pictures which together make up a so-called moving picture display together with further information in a series of discreet locations, which further information corresponds to the differences only between the current picture and the next in the said sequence so as to produce a modified version of the current picture for display next in turn,
d. the static storage device having provision for the storage of information concerning the time to lapse between the display of the current and the next picture in the said sequence,
e. reading means adapted to receive the static storage device having signals stored thereon and for reading same so as to produce the electrical output signal corresponding to the first and subsequent of a sequence of pictures, and
f. connection means for connecting the output of the reading means to the television monitor to display the output signals in the form of a sequence of Dictures.
2. A system as claimed in claim 1 wherein the static storage device is a solid state storage device in the form of an erasible programmable memory (EPROM).
3. A system as claimed in claim 1 or claim 2 wherein information is stored in the storage device corresponding to the colour required in any region in the displayed pictures and the television monitor is a colour television monitor.
4. A system as claimed in either of claims 1 and 2 wherein the monitor is a standard broadcast television receiver (as will commonly be the case) and the signal generating and modulating circuit means is conveniently provided for generating a modulated RF signal for application to the ariel input socket of the receiver.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB08200612A GB2119606B (en) | 1982-01-09 | 1982-01-09 | Improvements in and relating to television type displays |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB08200612A GB2119606B (en) | 1982-01-09 | 1982-01-09 | Improvements in and relating to television type displays |
Publications (2)
Publication Number | Publication Date |
---|---|
GB2119606A true GB2119606A (en) | 1983-11-16 |
GB2119606B GB2119606B (en) | 1985-07-10 |
Family
ID=10527557
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB08200612A Expired GB2119606B (en) | 1982-01-09 | 1982-01-09 | Improvements in and relating to television type displays |
Country Status (1)
Country | Link |
---|---|
GB (1) | GB2119606B (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2157925A (en) * | 1984-03-22 | 1985-10-30 | Ace Coin Equip | Video display apparatus |
EP0184138A2 (en) * | 1984-12-04 | 1986-06-11 | Energy Conversion Devices, Inc. | Display system |
-
1982
- 1982-01-09 GB GB08200612A patent/GB2119606B/en not_active Expired
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2157925A (en) * | 1984-03-22 | 1985-10-30 | Ace Coin Equip | Video display apparatus |
EP0184138A2 (en) * | 1984-12-04 | 1986-06-11 | Energy Conversion Devices, Inc. | Display system |
EP0184138A3 (en) * | 1984-12-04 | 1988-09-07 | Energy Conversion Devices, Inc. | Display system |
Also Published As
Publication number | Publication date |
---|---|
GB2119606B (en) | 1985-07-10 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PCNP | Patent ceased through non-payment of renewal fee |