GB2113387A - Method of measuring thermal neutron characteristics - Google Patents

Abstract

The thermal neutron decay characteristics of an earth formation are measured by detecting indications of the thermal neutron concentration in the formation during first and second measurement intervals following irradiation of the formation with a burst of fast neutrons. These measurement intervals may be selected from a sequence of discrete time gates which begins following a predetermined time delay after the preceding neutron burst and extends over substantially the remainder of the interval between neutron bursts. The particular set of two measurement intervals used is selected from among a number of possible sets as a function of a previously measured value of the decay characteristic. Measurements of detected radiation, averaged over a plurality of first intervals following respective neutron bursts, and averaged over a greater plurality of second intervals, are used to provide a background-compensated measure of the average level of induced radiation. <IMAGE>

Description

1

SPECIFICATION

Method and apparatus for measuring thermal neutron characteristics GB2113387A 1 The present invention relates in general to nuclear well logging and, more particularly, to new 5 and improved methods and apparatus for detecting the decay, or capture, of thermal neutrons in earth formations in a manner affording more accurate and reliable measurements of thermal neutron capture characteristics of the formation.

Heretofore, pulsed-neutron capture logs have provided measurements of thermal neutron capture characteristics of earth formations, e.g. the thermal neutron decay time constant (,r) and 10 its correlative the macroscopic capture cross section (1), which have proven useful in differentiating between oil or gas-bearing formations and water-bearing formations. Such logs are especially useful in recognizing the presence of hydrocarbons in cased formations, and to detect changes in water saturation during the production life of a well.

Thermal neutron characteristic measurements are typically made by irradiating a formation with bursts of fast (e.g. 14 Mev) neutrons and following the decay of the thermal neutron concentration in the formation by counting the gamma rays emitted by formation nuclei upon the capture of thermal neutrons during discrete time intervals, or gates, following each neutron burst. In one prior tool disclosed in U. S. Patent No. 3,379, 882 to A. H. Yournans, the capture gamma rays are measured during two gates which are fixed both in time of occurrence after the 20 burst and in duration. Although affording useful information in formations of average decay time, the Yournans fixed-gate system tends to yield unreliable measurements where the decay time of the formation is either very long or very short. Moreover, the gamma ray count rate measurement during the second fixed-gate is sometimes subject to excessive statistical variation, particularly in short decay time formations. In an important advance over the fixed-gate system, W. B. Nelligan in U. S. Patent No. 3,566,116 (now Re. 28,477) patented a sliding-gate system in which three measurement gates are utilized and in which the time-after- burst occurrence and duration of all of the gates are automatically varied, in a feed-back loop operation, according to the currently measured value of the decay time constant. The first two gates are timed to detect capture gamma rays from the formation and the third gate is timed to detect background gamma rays. This system operates properly to position the gates for optimum background corrected measurements over a wide range of decay times r and cross sections 1, thereby avoiding the deficiencies in respect of unreliability and statistical variation encountered in the fixed-gate system in cases of extreme decay rates. For still better results, Nelligan further provides that the duration and repetition rate of the neutron bursts could also be varied as a function of the currently measured decay time value. This affords the added advantage of maximizing the duty cycle of the neutron generator in a manner consistent with accurate measurement of the decay time value of the formation being logged. Later embodiments of the Nelligan sliding-gate concept are described in U. S. Patent No. 3,662,179, granted May 9, 1972 to Frenchtop et al., and U. S. Patent No. 3,890,501 granted June 17, 1975 to C. W. 40 Johnstone. Thermal neutron decay time logging, in accordance with the Nelligan sliding-gate technique as described in the aforementioned patents, and has become a widely accepted and important cased-hole service.

It is therefore an object of the invention to provide an improved method and apparatus for measuring thermal neutron decay time constants and related capture cross sections of earth 45 formations traversed by a well bore.

According to this invention there is provided a method for providing a background compensated measurement of the level of induced radiation within an earth formation, comprising:

(a) irradiating an earth formation with a discrete burst of neutrons during each of a succession of irradiation intervals; (b) detecting indications of the level of radiation in the formation during at least a first detection interval occurring at a first time within each irradiation interval; (c) detecting indications of the level of background radiation during a second detection interval occurring at a second time within each irradiation interval; (d) measuring the average level of said first detected indications over a first plurality of said 55 irradiation intervals; (e) measuring the average level of said second detected indications over a second, greater plurality of said irradiation intervals; and (f) combining said first and second measurements to provide a first background-compensated measurement of the average level of induced radiation in the formation.

For a better understanding of the invention, reference may be made to the following description of exemplary embodiments thereof, taken in conjunction with the figures of the accompanying drawings, in which:

Figure 1 is a schematic view of a representative well logging tool construction in accordance with the invention; 2 GB2113387A 2 Figure 2 is a graphical representation of illustrative thermal neutron concentration decay curves in three different formations and showing superimposed thereon a preferred neutron generator and detector gating regime in accordance with the invention; Figure 3 is a block diagram of the downhole control, gating, memory and telemetry circuits of 5 Fig. 1; Figure 4 is a schematic view of the command signal decoder of Fig. 3; Figure 5 is a schematic view of an embodiment of the command signal generator of Fig. 3; Figure 6 shows the details of the timing generator of Fig. 3; Figure 7 depicts in detail the near (or far) detector pulse counter circuit of Fig. 3; Figure 8 is a schematic view of the memory address generator of Fig. 3; Figure 9 shows an embodiment of the near (or far) detector memory circuit of Fig. 3; Figure 10 shows an illustrated telemetry frame for transmitting data on the surface; Figure 11 is a schematic view of the sync/status circuit of Fig. 3; Figure 12 is a schematic view of the telemetry interface circuit of Fig. 3; Figures 13A and 13B illustrate two generalized time gates for measuring thermal neutron 15 concentrations; and Figure 14 is a graphical comparison of an exemplary empirical relationship for computing r in accordance with the invention wieht the true relationship for r for the example portrayed.

In the exemplary embodiment of Fig. 1, a well logging tool constructed in accordance with the invention includes a fluid-tight, pressure-and-temperature resistant sonde or tool 10 that is 20 adapted to be suspended in and moved through a well bore 12 by an armored cable 14. The well bore 12 is illustrated as containing a borehole fluid 16 and as including a steel casing 18 and surrounding cement annulus 20. Although no tubing is shown in the borehole, the tool 10 may if desired be sized for through-tubing use.

The downhole tool 10 includes a pulsed neutron generator 22 and two radiation detectors 24 25 and 26 that are located at different spacings from the neutron generator 22. The detector 24 spaced closest to the neutron generator is designated the---near-detector and the detector 26 located farther from the neutron source is designated the---far-detector. For the purpose of the present invention, the neutron generator 22 is preferably of the type which generates discrete pulses of fast neutrons, e.g. 14 Mev., and may for example be of the types described in more 30 complete detail in U. S. patent No. 2,991,364 to C. Goodman, dated July 4, 1961, and U. S.

patent No. 3,546,512 to A. H. Frentrop, dated December 8, 1970. Operation of the neutron generator 22 is controlled in part by a neutron generator control circuit 30, and this circuit may also be of the types described in the aforementioned patents. The detectors 24 and 26 may be of any construction suitable for the detection of the thermal neutron concentrations in the surrounding earth formation and, to that end, may be of the thermal neutron sensitive type, e.g.

helium 3 filled proportional counters, or of the gamma ray sensitive type, such as thallium activated sodium iodide detectors. In the preferred embodiment, the detectors 24 and 26 preferably comprise sodium iodide scintillation detectors and, in this respect, will be understood to include the usual photomultiplier tubes, photomultiplier high voltage supplies, and amplifier- 40 discriminators (not shown). It will also be understood that other downhole power sources (not shown) are provided as required to drive the neutron generator 22 and other downhole circuits.

Power for the well tool 10 is supplied over the cable 14 from a surface power supply (not shown), as is conventional.

Output pulses from the near detector 24 and the far detector 26, representative of the 45 concentration of thermal neutrons in the irradiated formation, are applied to signal gating circuits 32. The signal gating circuits 32 are controlled by gate timing circuits 33, which also control the operation of the neutron generator control circuits 30. From the signal gating circuits 32 the detector signals are counted and stored in memory circuits 35 and thence, under control of telemetry logic circuits 37, are applied to downhole telemetry circuits 34 for transmission to 50 the surface over the cable 14. The overall operation of the neutron generator control circuit 30, the signal gating circuits 32, the gate timing circuits 33, the memory circuits 35, and the telemetry circuits 34 is described in detail hereinafter in connection with Figs. 3-12.

The downhole telemetry circuits 34 may be of any known construction for encoding, time division multiplexing, or otherwise preparing the data-bearing signals applied to them from the 55 telemetry logic circuits 37 and for impressing such data on the cable 14. At the earth's surface, the data-bearing signals from the near and far detectors 24 and 26, respectively, are amplified, decoded, demultiplexed and otherwise processed as needed in the surface telemetry circuits 36, which may also be conventional. The telemetry circuits 34 and 36 also include circuits for the receipt and transmission, respectively, of command messages from the surface for the purpose 60 of selection of the scale factor value F to be used, as is described more fully hereinafter.

Suitably, therefore, the circuits 34 and 36 comprise a bi-directionai data telemetry system useful for these purposes and having a 10 K bit per second upward data rate.

Following circuits 36 the near-detector and far-detector signals are separately counted in signal counting circuits 38 to acquire the thermal neutron decay curve data over a desired 65 2 3 GB 2 113 387A 3 accumulation interval At. Upon termination of the data accumulation time At, which may be selected, for example, to correspond to a desired interval of depth in accordance with logging speed of the tool, the count rate data accumulated in the signal counting circuits 38 are transferred to buffers 40 and the signal counting circuits 38 are reset to zero. 5 From storage 40, the count rate data are processed in a computer 42, which may suitably comprise a microprocessor. As is described more fully hereinafter, the computer 42 processes the count rate data from the respective detectors to develop various desired outputs, including, for example, the decay time constantS T,, and r, for the near and far detectur, respectively, the corresponding macroscopic capture cross sections 1, and YEF, and various other selected outputs such as a ratio 10 (N/F) of count rates from the near and far detectors, background counting rates (13, and B,) from the respective detectors, and the net count rates from certain time gates, e.g. N, and F,, for both detectors. All of these outputs may be recorded in conventional fashion as a function of tool depth in a recorder 44. The usual cable-following mechanical linkage, indicated diagramma tically at 46 in Fig. 1, is provided for this purpose. As is illustrated by line 48 in Fig. 1, the computer 42 transmits an appropriate scale factor command signal to the surface telemetry circuits 36 for transmission downhole to the gate timing control circuits 33 for real time adjustment of the timings and durations of the detection gates for the near and far detectors 24 and 26 and, if desired, for the duration and repetition rate of the neutron bursts as well.

In the graphical representation of Fig. 2, three decay curves 50, 52 and 54 respresent, 20 respectively, the variation with time of the logarithmic counting rate of thermal neutron capture gamma rays following irradiation of earth formations having short, medium and long decay times (rates of decay) of thermal neutron concentration. For purposes of comparison, the curves 50, 52 and 64 are shown as normalized to approximately the same peak counting rate although, as will be appreciated, this is not normally the practice. The variable tailing portion 56 25 of each curve represents background, and this too has been shown as being at approximately a constant level of intensity for purposes of illustration.

As is well known, the slope of the thermal neutron decay curve for a formation is indicative of the thermal neutron decay time constant r of the formation, and it is a feature of the present invention that the decay curve, and thus r, may be more precisely detected or measured than 30 has been possible heretofore. In furtherance of this object, sixteen discrete time intervals or gates G,-G,, are provided between successive neutron bursts. As illustrated in Fig. 2, the gates G,-G,, constitute a sequence of discrete time gates, which sequence begins after a finite time delay following the termination of the preceding neutron burst and extends over the entire, or substantially the entire, remainder of the interval between neutron bursts. Advantageously, though hot necessarily, the gates are contiguous in time. The purpose of the time delay between the preceding neutron burst and the beginning of the gating sequence is to permit gamma rays emanating from the immediate borehole environment, e.g. borehole fluid, easing, cement annulus, tool housing, etc., to die out before detection of the count rate data from the formation is commenced. As indicated in Fig. 2, the discrete time gates G,-G16 are divided into four groups 1, 11, Ill and IV of four gates each, i. e. time gates G,-G, comprise gate group 1, time gates G,-G, comprise gate group 11, time gates G,-G,, comprise gate group Ill, and time gates G13-G16 comprise gate group IV. Within each gate group, the discrete time gates are of equal duration. Hence, each of gates G,-G, has the same duration, e.g. 25 microseconds "), and, similarly, the individual time gates of each of gate groups 11, Ill and IV are also of equal duration. However, the duration of the time gates increases progressively from gate group to gate group in the sequence. The increase is incremental, i.e. by a finite factor, and preferably the degree of increase is a multiple of the time gate duration of the next preceding gate group.

A multiple of two has been found advantageous. Thus, the duration of the discrete time gates G,-G, in gate group 11 is preferably twice the duration of the discrete time gate G,-G, in gate group 1, i.e. 50 gs. The duration of the individual time gates G,-G12 in gate group Ill is then twice the duration of the individual time gates G,-G, in gate group 11, i. e. 100 gs, and the duration of the individual time gates in gate group IV is twice that of the Group Ill gates, i.e.

gs. It will be understood that either or both the specific durations of the gates within each group and the amount of increase in gate durations between groups may be varied as desired from the values shown. Also, both the number of gate groups and the number of discrete time gates within each gate group may likewise be varied from the four-four scheme shown in Fig. 2.

By thus employing narrow gates early in the gating sequence and wider gates later in the gating sequence, the narrowest gates are concentrated in the early regions of the thermal neutron decay curves 50, 52 and 54 where the rate of change in counting rate is the greatest. 60 Further, not all of the time gates need be included in the T computation, but rather only those containing significant decay signal. Thus not only is a degree of data compaction achieved through the use of detection time gates of variable duration with time after the neutron burst, but greater precision is provided by excluding from the 7. computation counting rates from time gates which are subject to undue statistical variation, such as the later gates in short r 4 GB2113387A 4 formations. As described more fully hereinafter, the particular gates to be employed in computing r are selected on the basis of a prior measurement of r during the same logging run, and are those gates which have been determined empirically to give the minimum statistical variation in the measured value of 7. over a finite r range spanning the previously measured 5 value.

It has been found, in accordance with the invention, that in addition to providing time gates G,-G,, which increase in width as a function of time after the neutron burst, even better results are obtained by providing for selected, incremental adjustment of the durations of the discrete time gates G,-G,,, and, if desired, also of the durations and repetition period of the neutron burst and the duration of the discrete time delay between the end of the burst and the beginning of the gating sequence, as a function of a previously measured value of 7. The object is to so position the gates G,- G,,, neutron burst, etc., that the counting rates in all of the gates used in the T computation, i.e., the early gates, the mid-range gates and later gates as the case may be, will be sufficiently high for reliable statistical precision in the 7 measurement. It is desirable, therefore, in effect to shift the time placement of the detection time gates, neutron 15 burst, etc. as the r of the formation, and thus the rate of decay of the thermal neutron concentration curve, varies. Such time interval adjustment is accomplished by multiplying each time interval to be adjusted in duration by a common selected value of a finite number of discrete scale factor values F. This is illustrated in Fig. 2, where the duration of the neutron burst is shown as F X 200 gsec, the duration of the delay as F X 200 Asec, the duration of each 20 of gates G,-G, as F X 25 ttsec, and so on. As also shown in Fig. 2, the next succeeding neutron burst is preferably contiguous in time with the end of time gate G,,, whereby not only the duration of the neutron burst may be adjusted by the scale factor value F but also the repetition period between successive neutron bursts, as indicated by the value F X 1900 ttsee. Hence, it will be appreciated that by changing the value of the scale factor F the counting rate times for 25 the various gates may be uniformly changed relative to the neutron burst in a manner to optimize the detection of the thermal neutron concentration decay in the particular fomation at hand. That is to say, by selection of the scale factor F the individual gates G,-G,, may be expanded or contracted along the time base of the thermal neutron decay curve as the rate of change of the curve, and thus r, varies.

By providing for a finite number of incremental changes in the widths of the detection time gates, it is possible to locate the time gates properly relative to the portion of a thermal neutron decay curve that is most representative of decay of the thermal neutron concentration in the earth formation, namely the straight line portion of the curve appearing on a semi-log plot such as that of Fig. 2, so that to maximize counting rates within the gates and thereby improve precision in the measurment of the r, while at the same time avoiding the necessity for the infinitely variable electronic gates used in prior logging tools. It has been found, for instance, that if three or less F values are used, the later gates used to compute r include too much background. This results in greater statisitical uncertainty, necessitates measurement of back ground over unduly long accumulation periods, and requires a separate background computa- 40 tion for nearly all T computations. These deficiencies can be largely, if not entirely, eliminated by use of a higher number, e.g 5 or 6, of scale factor values F. Generally the more incremental values of the scale factor F provided, the greater the statistical reliability achieved. On the other hand, tool complexity increases with increased numbers of scale factor values. Accordingly, it has been determined in accordance with the invention that 4 incremental values of F will afford 45 improved statistical performance over the full r range of interest, commensurate with a minimum of tool complexity.

The amount of incremental change between F values should be selected, in conjunction with the specific durations assigned to the gates in gate groups 1, 11, Ill and W, to enable accurate detection of the decay curves over the full range of r's expected to be encountered in the earth 50 formations, e.g., from < 50 Msec to > 600 jusec. For the gate widths of 25 ttsee, 50 gsec, 100 gsec and 200 gsec shown in Fig. 2, it is preferred in accordance with the invention to change F by increments of V/_3. The preferred values of F, therefore, are 1 / V,3, 1, X/73 and 3. Also, as described hereinafter, incrementing F by a factor of V13 affords circuit advantages in implement- ing the F factor procedure in the logging tool.

In order to avoid changing F merely as a result of statistical variation in the measured value of,r, the criteria for determining whether the F value need be changed, based on the current measurement of r, are established such that there is an overlap between adjacent r ranges for which either of the two F values associated with those ranges is appropriate. For the exemplary case of F = 1 /N/-3, 1, NA and 3, suitable criteria for changing F based on a new r measurement are:

0 t GB2113387A 5 TABLE 1

Fold rnew Change F to 1 -13 3 10 V-3 1 V/_3 > 120 gsee > 210 jusec >365 gsec <285 gsec < 165 gsec < 9 5 jusec 1 vr3 3 V1,3 1 1 /V.3 f These criteria permit the use with r's within the range of from 95 ttsec to 120 gsec of F values of either 1 INA or 1, within the range of from 165 gsec to 210 gsec of F values of either 1 or the \/-2, and within the range of from 285 gsec to 365 gsec of F values of either \/-2 or 3.

Generous overlap regions are thereby provided with in which F need not be changed from the previous value. This avoids the -jitter- sometimes encountered in gating control in the prior art infinitely-variable gate tool.

At the beginning of each logging run, or where a previously measured value of r is otherwise 20 unavailable, the initial scale factor F is set based on fictitious 7-, e. g. F = 1 for r = 200 gsec. The tool will then automatically change F in accordance with the appropriate criteria, e.g. those of Table 1, as the currently measured value of r changes in the course of the run. Before discussing the procedures for computing r and thereafter for using the new r value to determine whether or not a change in the scale factor value F is required, reference may be made to Figs. 3-12 of 25 the drawings where the manner in which the change in F value and the consequent change in the time durations of the time gates G,-G16, neutron burst, etc., are implemented in the downhole tool 10 is shown.

Fig. 3 is a block diagram showing the interconnections between the neutron generator control circuit 30, the gate timing control circuit 60 which, as illustrated, combines the signal gating circuit 32, the gate timing control circuit 33, the memory circuits 35, and the telemetry logic circuits 37. The interface between these circuits and the telemetry circuits 34 is also indicated.

When the tool is powered-up to begin a run the inputs H and L to the gate timing control circuit 60, are automatically set equal to logic 0. The timing control circuit 60 generates four discrete clock frequencies, each corresponding to one of the scale factor values F = 1 1, N/_2 and 35 3. By changing the logic state of the H and L inputs, selection may be made of the particular frequency, and hence F value, that is to be used. It is assumed here that the logic state 0 corresponds to F = 1. As described more fully hereinafter in connection with Fig. 6, the output frequency signal is then sent to a series of scalers, i.e. counter/divider circuits, and decoders within circuits 60 and is used to generate all of the timing signals for controlling the operation 40 of the neutron generator 22 and the gating of the near and far detectors 24 and 26.

Thus, the timing circuit 60 produces a neutron burst signal NB that is applied to a command signal circuit 64, which in response thereto generates two ion source pulses (ISP, and ISPj that drive the neutron generator control circuits 30 (see also Fig. 1) thus causing the neutron generator 22 to produce bursts of neutrons of the desired duration and repetition rate. The detectors 24 and 26 are preferably blanked during and immediately following each neutron burst to isolate the downstream electronics against excessively huge instantaneous count rates.

To that end, the timing generator 60 also generates an appropriate blanking pulse to block the detector outputs for a specific period, e.g., twice the duration of the burst. This is described in more detail in connection with Fig. 6.

The timing gate signal generated by timing generator 60 is denoted DCLK, and this signal is used to gate the detectors in accordance with the regime of Fig. 2. In general, this is done by supplying four frequencies related to each other by a factor of two to a multiplexer under the control of a count-by-four circuit. The multiplexer output is supplied to the counter so that four pulses of the highest frequency are passed through the counter before it switches to pass four 55 pulses of a frequency half that of the highest frequency, until all of the timing gate signal, DCLK, is generated. The timing gate signal DCLK in turn creates memory control pulses WT, SET, and RDY for use elsewhere in the system. The manner in which the DCLK, WT, SET and RDY signals are generated is explained in detail with reference to Fig. 6.

The gated near and far detector signals, NG and FG, are supplied to near detector pulse 60 counter circuit 68 and far detector pulse counter circuit 70, respectively. In these circuits, the pulses from each detector for each gate period G,-G,, are counted and a binary number representing that value is transferred in parallel to near and far memory circuits 72 and 74.

Each pulse counter circuit acutally has two counters. While one of the counters is counting the pulses in one time gate, the other is transferring the results of the previous count to the 65 6 GB2113387A 6 memory. Two counters are necessary because the time gates are contiguous and there is not enough time for one counter to do both operations. A typical detector pulse counter circuit is shown in more detail in Fig. 7.

Each of the memory circuits 72 and 74 store sixteen 8-bit words which represent the accumulated count for each time gate G,-G,, over a number of neutron irradiation intervals. This is done by addressing the memories via an address generator circuit 76 so that the previous value of the accumulated counts for the time gate in question is presented at the input of an adder circuit. The memory output is then added to the current count for that gate and the result is again stored in the memory at the address for that time gate. The manner in which the address generator 76 controls the memory circuits is discussed in more detail in connection with 10 Figs. 8 and 9.

At a predetermined time a signal FCLK, from the telemetry circuits 34 informs the tool that the accumulated counts for the sixteen gates G,-G,,, are to be sent uphole. The FCLK signal is received in telemetry interfacecircuit 78, which generates an E signal and a TCLK signal that are applied to the memory address generator 76 for use in generating signals LDD in address 15 generator circuit 76 that are in turn applied to the memory circuits 72 and 74 to effect transfer of the contents of each memory location, along with generated parity bits, into parallel-to-serial shift registers (not shown in Fig. 3). The TCLK signal then causes the data to be serially shifted from near memory circuit 72 through far memory circuit 74 so that the far detector count rate data for each gate is placed in front of the near detector data for that gate. This string of data is 20 then passed through sync/status circuit 80 which positions a 4-bit sync code and status information word at the beginning of the information to form the DATA signal. The DATA signal is in the form of a binary signal, arranged according to Fig. 10, which is sent to the telemetry interface circuit 78 and thence as signal SIG to the telemetry circuits 34 for transmission uphole. In this respect, the interface circuit 78 functions primarily to make sure that the 25 telemetry circuits 34 are ready to receive the data before it is sent. The operation of sync/status circuit 80 and telemetry interface circuit 78 are set forth more precisely with respect to Figs. 11 and 12 below.

As described hereinafter, when the count rate data is received uphole the computer calculates r, and if it fails outside the limit for F = 1 according to Table 1, a two bit binary code to change 30 the scale factor is generated. There are four commands that specify the scale factor and three other commands making a total of seven. The scale factor commands result in the generation of H and L signals in the command signal circuit 64 which, as aforementioned, are sent to the timing generator 60 to change the scale factor. The available commands are listed in Table ll:

TABLE 11

COMMAND H.L. CODE F REMARKS 1r 01 00 1 Always 40 01 Always 06 10 If the previous F is 1 (05)+06 11 3 If the previous F is N/_2 02 - - Positive plateau cheek 03 - - Negative plateau check 45 04 - - Calibration test 01-07-06-01 - - Neutrons on With reference again to Fig. 3, the binary coded comman signals CMCD are received from the 50 telemetry circuits 34 by the command decoder circuit 82 (Fig. 4). As indicated in Table 11, the tool can be commanded to perform certain tests, e.g. plateau check of calibration test, in addition to changing the F value. It can also be commanded to bring the neutron generator to a ready state, requiring only the NB signal to initiate a burst. In the decoder circuit 82, the command signal is analysed and the appropriate output, i.e. 2 to 7 or CUR, is activated. The 55 command lines all go to command signal circuit 64, wherein the signals to carry out the command are generated. This is described in detail in connection with Fig. 5.

In order to demonstrate the detailed working of the various circuits depicted in Fig. 3, it can be assumed that the results of the first r calculation resulted in a value Of T less than 95 [Lsec.

From Table 1 it can be seen that the uphole computer 42 will require a change in scale factor 60 from F = 1 to F = 1 /-X/3. Thus the computer will generate the command 06 (binary bits), corresponding to HL code 10, as shown in Table 11. It should be noted that in Figs. 4-9 and 11-12 the numbers in the circuit blocks represent the model numbers of CMOS integrated circuits that can perform the indicated functions. These integrated circuits are available from a variety of manufacturers, including Motorola, Fairchild, National Semiconductor, and others. 65 m GB2113387A 7 7 Fig. 4 illustrates the details of the command decoder 82. In Fig. 4, the F-command signal from the telemetry circuits 34 is received by a one-shot 84, Ee. a monostable multivibrator, which has a time delay of 250 ttsec and which functions to generate a downhole clock signal from the CIVIC1) signal. For this purpose, the CIVIC1) signal is in the form of a pulse width- encoded signal having a positive-going transition at the boundary between each bit, e.g., every 400 gsec. This positive-going transition clocks the one-shot 84 to produce an output clock signal with a positive-going transition in the middle of each bit period. The one-shot transition clocks a shift register 86 which has the CIVIC1) signal applied to its input. Hence if the CIVIC1) signal is low in the bit period a zero is entered in the, shift register 86 and a one is entered if it is high. After six clock pulses from the one-shot 84, the serial data in the CIVIC!) signal is 10 available in parallel form at the outputs of the shift register 86. The three most significant bits of the ouput of reigister 86 are applied to an OR-gate 88. If any of these three outputs contains a one, it will be passed to the input D of a binary-to-decimal decoder 90 via an OR-gate 92. This enters an 8 into the decoder 90 so as to prevent any ouput therefrom less than 8. Thus, a bit in one of the higher order places of the CMCD signal indicates an invalid code which is above the 15 legitimate command codes 01 to 07. Accordingly, the command code should not be applied to the decoder 90 until all of the CIVIC1) signal has been entered into the shift register 86. To that end, the CIVIC1) signal is also applied to a re-triggerable one-shot 94 having a nominal pulse duration of 750 ttsee, the output of which goes high when the first CMCD pulse arrives and stays there until 750 gsec after the last one arrives. As shown in Fig. 4, this output is also applied to the D input of the decoder 90 through the OR-gate 92 and functions to block the decoder output until the command code has been completely loaded into the shift register 86.

When the output of one-shot 94 finally goes low, the decoder 90 decodes the command signal and activates one of its ouput lines depending on the command code contained in the CMCD signal. In this case it will be output 6 for the command 06 (see Table 111). The command remains in the shift register 86 until receipt of a reset RST pulse from the telemetry interface circuits 78.

The RST signal is also applied to a scaler or divider circuit 96. Scaler 96 produces a command clear CCLR signal through an OR-gate 98 upon receipt of eight RST signals without being reset by the ouput of one-shot 94. Thus if the CIVIC1) pulses stop for some reason the 30 CCLR signal is still generated. The CCLR signal is also generated through the OR-gate 98 by the ---1---output of the decoder 90, i.e. an 01 command resets the circuits so as to produce F = 1.

The six outputs from the decoder 90 and the CCLR signal are applied to a set of six latch circuits 1 OOA- 1 OOF in the command signal circuit 64, shown in detail in Fig. 5. The CCLR signal can reset all of the latches either directly, as in the case of latches 1 OOA and 1001), or 35 through OR-gates 102A-1 02B and 104A-1 0413, as in the case of latches 10013-1 OOC and 1 OOE and 1 OOF, respectively. Latches 1 OOE and 1 OOF control a plateau check. When the command 02 is decoded in circuit 82 (see Table il), it puts a high level on the set input of latch 1 OOE and resets latch 1 OOF through OR-gate 10413. This causes the output of these latches to drive the output of amplifier 106 to approximately + 15 volts, which voltage is applied to the 40 detector voltage supplies through resistors in order to make the positive plateau check. If command code 03 were received instead, latch 1 OOE would be reset through OR-gate 104A and latch 1 OOF would be set, thus causing amplifier 106 to deliver - 15 volts to the detector voltage supplies for the negative plateau check. In the case where the command code is 01, a CCLR signal is created, as described in connection with Fig. 4, and this signal resets both latches 1 OOE and 1 OOF causing the amplifier 106 output to be zero. The outputs of latches 1 OOE- 1 OOF are also applied to NOR-gate 108, which supplies through inverter 110 a plateau check status signal, PCS, to the sync/status circuit 80 whenever either a positive or negative plateau check is being done.

The command code 04 sets latch 1001), thereby turning on the calibration tests by allowing 50 WT' pulses from the timing generator circuit 60 to pass through NAND-gate 112. The output C of gate 112 goes to the amplifier inputs of both detectors. During the calibration test, one count per detection gate cycle is added to each of the 16 gate channels for both detectors. If detector background is low (i.e. the tool is on standby) the test counting rates in all gates should be close to the same. The output of latch 1001) is the calibration test status signal, i.e. CTS, and it also is applied to the sync/status circuit 80.

The latches 1 OOB and 1 OOC control the scale factor F in response to commands 0 1, 05 and 06. The outputs of these latches go to a pair of D flip-flops 11 4A and 11413 which are clocked by an E, pulse from the address generator circuit 76. The outputs of the flip-flops 11 4A and 11 B are the H and L lines which go to the timing generator circuit 60 (see Fig. 3) to control the 60 selection of time operating frequency and hence the scale factor F. For the assumed case of a command code of 06, it is known from Table 11 that the H, L code should be 10. A high level on input line 6 in Fig. 5 accomplishes this by setting latch 1 OOC and flip-flop 1 14A. However, command 06 does not reset latch 1 OOB since that command is valid only if F was equal to 1, and F is equal to 1 only with an 01 command which resets all the latches as a CCLR signal and65 8 GB2113387A 8 makes both H and L low. Command 05, therefore, sets latch 1 OOB and resets latch 1 OOC through OR-gate 10213. This is necessary because that scale factor change does not depend on the previous value of F. (See Table 11) The capacitors to ground on the latch inputs prevent them from being triggered by arcs in the neutron generator.

As indicated in Table 11, the process of turning on the neutron generator 22 requires that the sequence of commands 01 -07-06-01 be received by the command signal circuit 64. The first 01 command initializes the status of the latches 1 OOA-1 OOB and flip- flop 11 6A by resetting all of them, flip-flop 11613 not being reset. The 07 command sets latch 1 OOA, thereby connecting a high signal to the D input of flip-flop 11 6A. When this is followed by an 06 command which sets latch 1 OOC, the high input on flip-flop 11 6A is clocked in that flip-flop, making its Q output 10 high and its (1 output low. The output of latch 1 OOC also resets flip- flop 11 6B. When the final 0 1 command is decoded, a set pulse reaches latch 118 via NAN D-gate 120 and inverter 122 because flip-flop 11 6A is set. The output of latch 118 resets flip-flop 11 6A, closes NAND-gate and ends the set pulse to latch 118. With latch 118 set, neutron burst pulses NB from the timing generator circuit 60 can pass through NAN D-gate 124 and inverter 126 to form the ion 15 source pulse ISP, and 1SP2 (see Fig. 5) which drive the neutron generator control circuit 30.

As the beam current in the neutron source rises, a relay in its control circuit closes. This connects a supply voltage to the output line BC of the latch 118 and makes it impossible to turn off the neutron source without turning off the tool power. It can be seen that flip-flop 11613 holds latch 118 in the reset condition until the proper time. Also, the set input to flip-flop 11613 20 is activated when power is first applied to the tool because it is connected to the + voltage through a capacitor. This capacitor and a resistor will pull the set input low to flip-flop 11613 after the power has been on for about 10 seconds.

With reference now to Fig. 6, two crystal oscillators 128 and 130 in the timing circuit 60 have divide-by-three scalers built into them. Thus both the crystal frequency and the divided-by- 25 three frequency are available from each oscillator circuit, providing a total of four discrete clock frequencies f, f2 f, and f, According to the invention, each of these frequencies is made to correspond to one of the F values 1 INA, 1, V1-3 and 3. This may readily be done by selecting the crystal frequency fl of oscillator 128 such that it is V/_3 times lower than the crystal frequency f, of oscillator 130. Then divided-by-three frequency f2 from oscillator 130 will be 30 related by a factor of the -,/3 to divided-by-three frequency f, from oscillator 128, and it may be seen that the frequencies fl, f21 f3, and f, are separated by the factor V1-3 and that, therefore, they may correspond respectively to the scale factor values F of 1 /X/-8, 1, X/_3 and 3. The clock frequencies fl-f, are supplied to a 4-channel data selector or multiplexer 132. The logic levels of signals H and L applied to the inputs A and B of the multiplexer determine which of the four input frequencies is connected to the output of the unit. The operation of multiplexer 132 may be summarized succinctly as follows:

TABLE Ill

A B Selected Output Command Input Freq.

Lo Lo X0 fl 01 1 Hi Lo X, f2 06 1 /V.3 45 Lo Hi X2 f' 05 r3 Hi Hi X, f4 05+06 3 In accordance with the invention and as has already been referred to previously, all of the 50 timing waveforms required to operate the neutron generator 22 and the detectors 24 and 26 in accordance with the regime of Fig. 2 are derived in common from the output of the multiplexer 132. Hence, a change in the F value can quite simply be implemented in all the timing circuits of the tool. The actual generation of the various timing signals is achieved by use of a scaler 134 coupled to the output of the multiplexer 132. Scaler 134 is implemented by utilizing the 8 55 lower frequency outputs of A 12 stage binary ripple counter.

As seen in Fig. 6, when the Q. and Q, l outputs of scaler 134 are high and the Q7 Output starts to go high, the RSET pulse is generated in NAND-gate 136 and resets the scaler through resistor 138. This marks the beginning of the neutron burst pulse NB generated in gate 140, which pulse lasts as long as the Q, Q91 Q101 Q1 l outputs of scaler 134 are all low. As previously 60 described in connection with Fig. 5, the NB pulse is used in the command signal circuit 64 to generate the ion source pulses ISP, and ISP, Returning to Fig. 6, negative pulses (N and F) from the near and far amplifier-discriminators of the near and far detectors 24 and 26 pass through capacitors 142 and 144 en route to gates 146 and 148. There they are blocked during the neutron burst and for an equal time afterwards by the output of NOR- gate 150, whose 65 9 9 GB2113387A 9 output is high as long as Q,, Q,,, and Q,, of scaler 134 are all low. When the output of gate goes low, the near and far pulses N and F are allowed to pass to the near detector pulse counter 68 and far detector pulse counter 70, respectively. (See Fig. 3) The Q, output of scaler 134 is designated ECLK and is sent to address generator 76. The Q4, Q11 Q6, and d, outputs are also uses as inputs to a 4-channel data selector or multipliexer 152 5 to generate the detector gating signal DI-CK, which signal has the form shown by gates G,-G,, in Fig. 2. The A and B inputs to multiplexer 152 are controlled by the third and fourth stages of a scaler 154. The waveform at the output of gate 150, when high, holds scaler 154 reset and at the same time blocks the output of gate 156, i.e. it holds DCLK low during the neutron burst and the delay period thereafter, as illustrated in Fig. 2. When the output of gate 150 goes low, 10 the reset action on scaler 154 lasts a few more microseconds due to the time constant of the R-C circuit 158 so that scaler 154, which is clocked by DCLK, does not trigger on the first positive edge of DCLK. As long as A and B of the multiplexer 152 remain low, the DCLK looks like an inverted version Of G4 from scaler 134, which has the period T/8. The period T is equal to the duration of the widest gate in the regime of Fig. 2, i.e., 200 Msec for each of gates 1 G,,-G,,. This lasts for the first four DCLK cycles counted by scaler 154, thereby generating the first four gating signals of 25 gsee duration each. The G, output from scaler 154 then goes high, placing a high level on the A input of multiplexer 152 and results in DCLK being controlled by the G5 output of scaler 134, with a period T/4 or 50 gsee. At the end of four T/4 cycles as counted by scaler 154, which cycles represent the gating signal for gates G,-G8, the 20 scaler 154 next selects the Q, output of scaler 154. This output has twice the period of the Q.

output, i.e., T/2, and results in the generation of the gating signals for the 100 ttsec gates G,-G,,. Finally_four cycles later, the (1, output of scaler 134 with a period T is selected. When four cycles of G, are passed, the circuit goes into the blanking period established by gate 150, as aforementioned.

Memory control pulses WT, WT', SET and RDY are generated in a Johnson counter 160 that is clocked by the output of multiplexer 132 via the gate 162. However, these memory control pulses are generated only when DCLK is high (DCLK low), since the DCLK signal inverted by gate 164 is applied to the reset input of counter 160. This is done because there is no need for -30 memory pulses during the blanking period. As illustrated in Fig. 6, the RDY signal is the Q, 30 output of counter 160, the SET signal is the Q, output, the WT signal is Q,, and the WT' signal is the Q, output. When the waveform WT' goes high, it blocks further clocking because it is connected to the clock enable input C, of the counter. Thus, WT' will stay high until the counter is reset the next time DCLK goes high.

The near and far detector pulse counter circuits 68 and 70 (see Fig. 3), which receive the 35 gated detector signals NG and FG from the timing circuit 60 (see Fig. 6), are identical. Hence, the operation of only one of these circuits will be described in connection with Fig. 7. The pulse counter circuits each include a scaler 166 that receives detector pulses from the even-numbered gates, G,, G,, etc., and a scaler 168 that receives the pulses from the odd-numbered gates, G,, G3, etc. While scaler 166 is counting, scaler 168 holds its counts until reset by the WT pulse, 40 and vice-versa. By the time the WT pulse arrives, the counts being held have been stored in the memory circuits 72, in the case of the near detector, and 74, in the case of the far detector (see Fig. 3). Flip-flop 170 controls the action in accordance with the DCLK signal. After sixteen DCLK pulses, the RSET signal insures that the flip-flop 170 is in a reset condition to repeat the operation for the next irradiation interval.

The gated detector pulses NG (or FG) are positive and suitably about 0.4 tisec in width. They are directed to NAND gates 172 and 174, which are alternately opened and closed by the Q and G outputs, respectively, of flip-flop 170. Two additional gates 176 and 178 receive WT pulses, following the inversion thereof in gate 180, and are likewise controlled by the d and a outputs of flip-flop 170. As will be appreciated, when the scaler 166 is being clocked by NG (or 50 FG) signal pulses, it is not reset by WT, but scaler 168 is so reset.

Upon completion of counting for a time gate, the total count accumulated therein appears in parallel form at the Q outputs of the scalers 166 and 168 and is thereafter applied to one of two quad 2-channel data selectors 182 and 184, the A and B inputs of which are driven by the flip-flop 170 such that they select the outputs from whichever scaler 166 or 168 is holding its 55 counts and ignore the outputs from the scaler that is counting. As seen in Fig. 3, data selector outputs are delivered to the memory circuit 72, for the near detector counts, and to the memory circuit 74, for the far detector counts.

Before discussing the memory circuits, however, it is useful to review the operation of the address generator circuit 76 which controls the memory circuits. This circuit, shown in Fig. 8, 60 must control the storing of the count rate data after it has been detected and the reading out of the data in response to telemetry requests. Although the data storing and the data read operations are synchronous, the memory where the data is temporarily accumulated must be accessible both for storing new counts quickly at the correct address and for reading out the accumulated counts at another address when required by telemetry. Accordingly, two address 65 GB2113387A 10 scalers are provided to keep track of the separate addresses required for storing and reading and provision is made to give priority to storing new data. The telemetry, then, may read out data between storage operations.

In Fig. 8, the RSET pulse from the timing generator circuit 60 initially presets all the outputs of the---store-address counter 188 high and holds them high until the beginning of a new detection interval. The first DCLK pulse at the beginning of a new interval clocks counter 188 to all zeroes, and this is the address where the gate G, counts, from the previous detection interval, are stored while the gate G, counts in the new interval are being accumulated in one of the detector pulse counter circuits 68, 70 (see Fig. 3). As previously described in connection with Fig. 7, the counts from odd-numbered gates go to to one scaler in the counter circuits and 10 those from even-numbered gates to to the other. During the DCLK cycle, one scaler is actively counting while the other is holding the counts from the previous gate so that they can be added to the memory. Thus the G, count for each detector is held in the -evennumbered- scaler for that detector until it is stored in the memory during the next succeeding G, period. The address fixed in the memory during this store operation is the output of scaler 188, which is passed 15 through a quad 2-channel data selector 190 to the memory circuits. As each DCLK pulse arrives, indicating a new gate, scaler 188 is incremented thereby changing the storage address.

As noted a separate address scaler 192 is provided for telemetry readout. Its clock and reset inputs are controlled by a system of gates 194, 196 and 198 which in turn are controlled by a Johnson counter 200. This is done so that the telemetry address scaler 192 is clocked only for 20 the data words read out, and not for the sync/status part of the information supplied to telemetry. The counter 200 is clocked by all positive-going edges of E and is reset by the telemetry reset signal RST, which should not be confused with the reset RSET from the timing generator 60. The E pulse is generated in the telemetry interface circuit 78 (Fig. 3) and goes positive a desired number of times per telemetry frame, e.g. 5, and is followed by the telemetry 25 reset signal RST. The NOR gate 194 keeps one input of the NAND-gate 196 low until the second time E goes positive in order to prevent the generation of memory address signals while the sync/status words are generated and transmitted. Then the output of gate 194 goes high and stays high for all of the data words in each telemetry frame, e.g. 4 (see Fig. 10), thus allowing counter 192 to be clocked a corresponding number of times per frame to generate the 30 memory read out address. After being clocked 16 times (4 frames) ouput Q, of the counter 192 goes high, thereby enabling the output of NAN D-gate 198 to go low the next time the---1-- output of counter 200, i.e. E signal, goes high. This resets counter 192 through gate 198 and keeps it in step with the E pulses. The Q. and Q, outputs of counter 192 control the frame identification bits in the sync/status word and are delivered to the sync/status circuit 80 (Fig. 35 3).

Flip-flop 202 controls data selector 190 such that the proper address counter, i.e., counter 188 or counter 192, has control of the memory address lines, AO --- A3. Flip-flop 202 is set by the RDY signal and reset by WT, both from the timing generator 60. When flip-flop 202 is in the set condition, the data selector 1190 selects the---store-address, and when it is in the reset 40 condition, the selector 190 selects the -read-out- address. As can be seen in Fig. 6, the RDY signal is the G, output of counter 160 and the WT' signal is the Q, output. Hence store occurs during one part of a cycle and transmission during the other part.

In addition to controlling the memory address lines, the circuit of Fig. 8 generates the LDS, I-DD, READ and CLR pulses. The LDS signal loads sync and status bits into a shift register in the 45 sync/status circuit 80. Shift registers in the memory circuits 72, 74 are located with data from memory at selected read- out addresses by the I-DD signal. The READ signal causes the memory output to correspond to data at a selected address and the CLR signal sets the memory contents to zero at a selected address. The READ signal starts at the same time as I-DD, but is of shorter duration. CLR occurs at the end of LDD. When READ and RDY are mixed together, they become 50 CS (Chip Select). When CLR and WT are mixed, they become WRT.

Interference between store and readout are prevented since LDS, LDD, and READ are not generated directly by a positive-going edge of E, but are generated by the first positive-going ECLK edge after E goes positive. The ECLK is applied to the Cp input of flip-flop 204. The D input is normally high, so Q is normally high. When E goes high, it is inverted by gate 206, differentiated by R, and C, and coupled to the D input of flip-f16p 204 through an RC delay, R, and C, When the D input of flip-flop 204 is low, the first positive ECLK edge will make the Q output go low. This output is differentiated by R4 and C4 and is applied to two gates 208 and 210. If the---1---output of counter 200, designated E, is high, and LDS pulse will appear at the output of gate 210. If E, is low, there will be an LDD pulse at the output of gate 208. R, and 60 C, determine the duration of these pulses. A simultaneous positive pulse occurs at the output of inverter 212, which is then differentiated by R31 C3 to become the READ pulse. The READ pulse and RDY pulse are combined in gate 214 to generate signal CS.

A flip-flop 216, which acts as a one-shot because its Q output is connected to its reset input R through time delay network R6, Cl. It is triggered by the trailing edge of I-DD after the latter is 65 r._ 11 GB2113387A inverted and slightly delayed by a time delay network formed by-R7 and the input capacitance at clock input CP of flip-flop 216. The CLR pulse is taken from the Q output of this flip-flop. Its duration is controlled by R6 and C6. The CLR and WT signals are combined in NOR-gate 218 to create the WRT signal.

Flip-flop 220 plays a part in setting the parity bit in each word. It is triggered by the TCLK 5 signal from telemetry interface circuit 78 and is set by the output of gate 222. A PRT 1 signal from the far memory circuit 74 and the I-DD signal control the inputs to gate 222. The operation of this gate and flip-flop 220 will be explained in more detail in connection with the memory circuit shown in Fig. 9.

The memory circuits 72 and 74 are the same and hence only one of them is shown in Fig. 9. 10 Each memory circuit includes two random access memories (RAM) 224 and 226, each capable of storing 4 data bits at 16 different addresses. The address lines A,-A, for these memories come from the address generator circuit 76, shown in detail in Fig. 8. When read out, the complement of the data appears at the outputs. The outputs of the RAMs 224 and 226 and data inputs from the pulse counter circuits are applied to adders 228 and 230, respectively, 15 which are each able to add two 4-bit binary numbers. When these adders are connected in series as shown, they can add these two 8-bit binary numbers. The result of this addition is stored in Quad D flip-flops 232 and 234. With this arrangement, the complement of the adder 228 and 230 outputs appears at the flip-flop 232 and 234 outputs when the SET pulse from timing generator 60 goes positive. Thus it can be seen that the current gamma count in a 20 particular gate is added to the previous total count for that data. Memories 224 and 226, therefore, store the total count for each gate for a number of neutron bursts, i.e., over a number of irradiation intervals. Incoming data from a pulse counter circuit 68 or 70 goes to the B,---B,

inputs of the adders, and the memory 224 and 226 outputs are connected to the A,-A, inputs. To store new data a succession of RDY-SET-WT pulses is generated. The RDY pulse arrives on the CS line (shared with READ) and the WT pulse is on the WRT line. At the end of RDY, the memories latch on the new address supplied from the address generator 76. The data contained at that address appears at the (1 outputs of the RAM's 224 and 226 and the binary number it represents is added to the number supplied by the associated pulse counter circuit. After a short 30 delay, the SET pulse latches the sum into the D flip-flops 232 and 234. The SET pulse is followed by the WT pulse which writes the complement of the sum into the memories, at the same address. In this connection it should be noted that the memory output is the complement of the number stored.

A shift register 236 is used for parallei-to-serial conversion of the data in the memory, when 35 required by telemetry with the arrival of an I-DD pulse followed by the TI-CK signal. A parity tree 238 is also provided for generating the parity bit that is part of each gate detector word (See Fig. 10).

Readout for telemetry requires a succession of LDD, READ, and CLR pulses. Data at the desired address appears on the memory output lines at the end of the READ pulse. The READ 40 pulse is overlapped by I-DD, which loads this data into the shift register 236. At the end of LDD, the CLR pulse occurs, resetting the D flip-flops 232 and 234 so as to set all the (1 outputs to 1 and simultaneously supplying a negative pulse on the WRT line so as to write the l's into the memory. This is the same as clearing that memory address, because the next time it is read out the result will be all zeroes.

Fig. 3 shows how the shift register and parity trees of the near and far memory circuits 72 and 74 are interconnected with each other and also with the SO (Shift Out) output of flip-flop 220 of the address generator circuit of Fig. 8. Both memory circuits 72 and 74 store data from a given detection gate simultaneously and both are read-out at the same time. As shown, the shift registers of the two memory circuits 72 and 74 are connected in series, with the SO output 50 from the near detector memory circuit 72 connected to SI (Shift In) input on the far detector memory 74. The SI input of the near memory circuit 72 comes from the SO ouput of flip-flop 220 in the address generator 76. This output controls the parity bit. The parity trees 238 in the memory circuits are also connected in series to form a single parity bit for the combined near and far word. The resulting output of the far detector memory parity tree (PRT 1) determines 55 whether flip-flop 220 in the address generator will be set by the I-DD pulse or will remain zero.

Following I-DD, the TCLK signal arrives from the telemetry interface 78 and causes the data to be shifted out. The first serial data bit is the most significant bit from the far memory 74. After the 8 far bits are sent, the 8 near bits are shifted out, followed by the parity bit.

As can be seen from Fig. 3, the data bits from the memory circuits are shifted in series 60 through the sync/status circuit 80 which adds the sync and status bits to the front of the data words. (See Fig. 10) Fig. 11 shows the details of the sync/status circuit with the data words applied to the SI input which leads to NAND-gate 240. The sync/status bits are applied to NAND-gate 242 and these two signals are combined in gate 244 to create the DATA signal output. To generate the sync/status bits the LDS pulse loads the shift registers 246 and 248 12 GB2113387A 12 with parallel data, which is then shifted out by the TCLK signal while the E, signal is high. The LDS signal also triggers a flip-flop 250 which acts as a one-shot and resets the scaler 252 that has control of the four---spare-bits at the end of the sync/status word.

Flip-flop 254 is loaded via gate 255 by the LDS signal with the G output of the parity tree 256, which is the parity bit for the sync/status bit in Fig. 10. Inputs P5 --- P, of shift register 5 248 are connected to + 5V. They control the first 4 DATA bits that are the sync signal. The other bits are the status signals and are applied to the rest of the shift register 248 inputs and the inputs of shift register 246 as follows:

TABLEIV

Circuit Input Signal 248 P4 Plateau Check Status 248 P, High Voltage Status 15 (Neutrons On) 248 P2 L= Command 05 in effect 248 P, E = Command 06 in effect 246 P, Q4-Higher order Frame 1. D. bit 20 246 P, G3 = Lower order Frame I.D. bit 246 P, BC = Burst Control (ISP On) 246 P5 CTS = Calibration Test 25 Status 246 P,-P, Spares 254 D Parity Bit The status signals applied to these shifting circuits come from the command signal circuit 64 and the address generator 76. Following the sync/status word, E, goes low. This connects the SI input to the DATA output so that the serial data from the memory circuits 72 and 74 can be shifted onto the end of the sync/status word.

The DATA signal which includes the data words and the sync/status word is sent to the 35 telemetry interface circuit 78, 3hown in detail in Fig. 12, for transmission uphole. This circuit establishes the number of words to be sent in each telemetry frame and the number of bits in each word. There are only two input lines to the telemetry interface circuit, i.e. the FCLK signal from the telemetry circuit 34 and the serial data, or DATA, signal from the sync/status circuit.

The outputs of the interface circuit are SIG and RST which go to the telemetry circuits 34, the E 40 signal which goes to the address generator 76, and TCLK which goes to the address generator 76, the memory circuits 72 and 74 and the sync/status circuits 80.

The telemetry circuits 34 starts sending FCLK signals when it is time to send data uphole.

Before FCLK arrives, E and E' (the output of flip-flop 260 as described below) are low and TCLK is high. The first half cycle of FCLK makes the E high because one input of an NAND-gate 258 45 goes low after a short delay due to the R-C network on that input. The first time RCK goes low, flip-flop 260 is clocked, causing its output E' to go high. The (1 output of flip-flop 260 going low maintains E high by locking-up gate 258. The E signal is made to go high as soon as possible because the LDD signal in the address generator circuit 76 can occur as late as one ECLK cycle after E goes high.

With the E' signal high, the A1 signal at the ouput of NAND-gate 262 starts by going low and then follows the other input FCLK. The positive-going edges of A1 clock a flip-flop 264 whose Q output is TCLK. The TCLK signal also clocks the scaler 266 on negative-going edges.

The purpose of scaler 266 is to count the njumber of bits per word, including the sync word.

After being clocked 19 times, the outputs B,, B,, and B, of scaler 266 are all high and as a result the output B, of a NAND-gate 268 goes low. One-half FCLK cycle later, A] goes low, causing the output A, of gate 270 to go high. The A2 pulse resets flip- flop 260 through gate 272 and, hence, it resets E. Signal A2 also causes an A3 pulse to be generated in gate 274 and an A4 pulse to be generated in gate 276. The latter pulse resets flip- flop 264 and counter 266. In addition, the signal A2 adds a count to a word counter 278. The next time FCLK goes 60 low, E' goes high again and the process is repeated. At the end of 5 words, the G, and G3 outputs of word counter 278 cause the output D5 of gate 280 to go low. The next positive FCLK edge will pass through gate 282 and will trigger the one-shot comprised of gates 284 and 286 to produce the RST pulse. The RST pulse stops the FCLK from the telemetry circuits 34 and resets all the flip-flops and scalers in the interface circuit 78.

7 ' 0 13 GB2113387A 13 The output C2 of gate 288 is a series of 18 negative pulsps, whose leading edges mark the boundaries of the 17 bits in a word. For C2 to go low, the output B6 of gate 290 must be high, i.e. either the B2 or B5 ouputs of counter 266 must be low, TCLK must be high, and Al must be low. The 136 output provides the word sync interval by going low to stop the C2 pulse. The DATA, KT and TUIL-K signals are applied to gate 292 to create the Cl signal. For Cl to occur, 5 DATA must be high while Al and TCLK are both low. The Cl signal, when it occurs, is half-way between the C2 pulses. A signal C3 is an inverted mixture of Cl and C2 pulses, produced in inverter 294 and goes to the collector of a transistor 296. Waveform E' goes to the transistor base. The output (SIG) of the transistor at its emitter Is connected to the emitter of a similar transistor in the telemetry circuits 34. When the telemetry is using the SIG line, the E' signal is 10 low so the transistor 296 will look like an open circuit. Likewise, when the interface circuit is sending SIG, a similar transistor in the telemetry circuit 34 is cut off.

Thus, it can be seen that an FCLK signal from the telemetry circuits 34 generates the TCLK signal that shifts the data from the memories and the sync/status circuit through the telemetry interface transistor 296 to the telemetry circuit 34 itself. During this time, the number of bits in15 each word is counted and controlled as are the numbers of words in each frame.

The preferred procedure for computing r from the near detector count rates N1-N,, will now be described.

As previously mentioned, the signal counting circuits 38 at the surface accumulate the count rate data for a time At before transferring the data to the buffer storage 40 and being reset to 20 begin a new counting sequence. Accordingly, the counts per time gate, i.e. , N1-1\11, for the near gates NG,-NG1,3, respectively, and F,-F,6 for the far gates FG1-M,,, respectively, as transmitted to storage 40 and to the computer 42, are not actually count rates but are simply the counts accumulated within each gate over the data accumulation period At. Thus, where the data symbols N,-N16 and F,-F,, are referred to in the following discussion concerning the computation of r, it will be understood that these represent total counts over the time At, as the case may be, as distinct from the count rates generated for the respective time gates in the downhole scalers. To than end, an internal clock is provided in the surface equipment to measure the duration At of each accumulation period in order to obtain accurate count rates for each gate.

In broad terms, the procedure followed in computing r, and thereafter in selecting the scale factor F, is as follows: New values of T are calculated periodically for each detector based on ratios R formed for each detector from the respective net (background- corrected) count rates, as accumulated at the surface over the period At, from selected sets of time gates. These values are hereinafter designated T, for the near detector values and r, for the far detector values. As is 35 explained more fully hereinafter, there are preferably seven sets of gates, each corresponding to a different ratio R, for each of the four scale factors F. The particular combination of gates making up each ratio R is that combination which has been found to minimize the dispersion of T on a given interval of r, chosen as the interval of validity of the corresponding ratio. Although the same set of gates is used in computing both r, and rF, it is selected on the basis of a previously measured value of 7-, only and is that set which is valid for such value of rN for the F value then in use. Using the gates thus identified, the ratios RN and RF are computed. The new values of r, and -rF are then calculated from linear equations in the form:

r = a + b R - 1 (1) where a and b are coefficients which establish a linear relationship between R - 1 and r over the interval of validity for that particular ratio R. The values of a and b for each ratio are computed beforehand and stored in the computer as a look-up library. Thereafter, the criteria for determining whether a change in the scale factor F is required are examined based on the new 50 value r, from Eq. (1). If it is determined that the scale value F must be changed, the appropriate command is sent downhole to the control circuits 33 to select the new F value as above described. Preferably commands to change F are sent only at the beginning of a new data accumulation period At in order to avoid mixing data taken with two different F values.

This procedure, of course, is carried out repetitively in the course of a logging run, with new 55 values of r, and 'rF being calculated at the end of each accumulation interval At and new values of the scale factor F being selected as required. Since, as noted, commands to change F are sent only at the beginning of an accumulation period and since the r computation and F selection procedure might well require an appreciable fraction of an accumulation period, commands to change F might be sent downhole at the beginning of every other accumulation 60 period. For instance, for a typical logging speed of 1800 feet per hour, the accumulation time At at the surface might be approximately 1 second, to provide accumulation times At and hence,r measurements, corresponding to 6 inch depth intervals. Changes in F could therefore be made as frequently as once per foot of depth, which is quite adequate to follow the most rapid r changes normally encountered, i.e. approximately 1 00jusec per foot.

14 GB2113387A 14 With reference now to Figs. 1 3A, 1313 and 14, the manner in which a library of gate sets for determining the ratios R, and R, and the corresponding values of the coefficients a and b for use in calculating r in accordance with Eq. (1) are developed may be seen. As a principal object of the i-computation procedure is to optimize the statistical precision of the value of r obtained therefrorn, it is desirable to use, as many ratios as possible in order to decrease the statistical uncertainty of the result, but to use each ratio only over its r range of validity. In order to ascertain which ratios afford optimum statistical precision in r over the range of interest, some preliminary determinations must be made. First, it is desirable to allow for early non-exponential decay of the thermal neutron concentrations. This is done by choosing the first gate in each set as the one which begins most nearly at a time equal to twice the previous r, from the end of the 10 neutron burst. Second, the gates used in the numerator and the gates used in the denominator are preferably contiguous in time. This is equivalent to using counts from only one gate for each of the numerator and denominator, such as the gate AT, in Fig. 1 3A and the gate AT, in Fig. 1 3B, respectively. Following this, the number and identity of the gates included in each term of the ratio is determined empirically. As the initial step, the mean count rate in each gate is 15 determined from the expression:

T_ 1, t. - L)4 T cl ' - GoTR (T. 20 TC e Tel r) T2- (2) Cl - r where: Nij represents the means number of counts/see in a gate which begins at a time T, and 25 ends at a time Tj with respect to the end of the neutron burst; T, and TP are, respectively, the duration and repetition period of the neutron burst; and (where the times are expressed in units of seconds) A. is the total number of decay signal counts that would be detected following a single long burst of neutrons (T,> >,r) and BO is the total background counts/sec if a steady neutron flux with the same intensity as that occurring during the neutron burst T, is assumed. 30 A,, depends upon peak neutron yield and detector size, efficiency and spacing, as well as on tool environment. B. depends on all of the foregoing and additionally upon time, since the major contributor to B,, with a Nal detector is the 25 minute neutron activation of 1 in the detector crystal. Typical observed values of A. range from 50-100 counts for the near detector and from 9-25 counts for the far detector. B,, builds up to approximately 5 X 104 counts/sec and 35 0.6 X 104 counts/sec for the near and far detectors, respectively.

Using Eq. (2), the gate counting rates are calculated for a given F value. For example, for the case of F = 1, r = 137.5 Asec, A,, = 50 counts and B. = 4 X 104 cps and using the gate times and durations of Fig. 2, the following counting rate table is obtained:

TABLE V

Gate Net cps Background cps Gross cps

4 453.9 55.4 509.3 45 693.9 110.8 804.7 6 482.4 110.8 593.2 7 335.2 110.8 446.0 8 233.0 110.8 343.8 9 274.6 221.7 496.3 50 132.8 221.7 354.5 11 64.1 221.7 285.8 12 31.1 221.7 252.8 13 22.2 443.3 465.5 14 5.2 443.3 448.5 55 1.3 443.3 444.6 16 0.2 443.3 443.5 in Table V, the background counting rate is taken as the sum of the counting rates from gates 60

G,, and G,,, as applied proportionately to each gate. Since the gates G,, and G,, are each 200 gsec long, the background counting rate for gates G,, and G14, each also 200 gsec long, is one half the G,, and G,, total, the background counting rate for gates G,-G,2, each 100 gsec long, is one-quarter the gate G,,, and G,, total, and so forth.

A reasonable set of gates is then selected and the fractional standard deviation a,/R in the 65 1 GB2113387A 15 ratio R of the count rates from such gates is calculated from:

TM TI 11,11 2 NN 1 1 51 (3) 5 where: NN is the numerator net counting rate and D, is the denominator net counting rate. The standard deviations in the numerator counting rate a, and the denominator counting rate aD are 10 given by:

and (4) 15 F4 61 + 20 D A / (5) where NB is numerator background counting rate, D, is the denominator background counting 25 rate, B is the sum of the counting rates from gates G,, and G,,, N, is the sum of N, and NB, and D. is the sum of D, + ID,.

Using Eq. (3), the fractional standard deviation a,/R of the ratio is computed for several different background smoothing times, e.g. 1, 2, 4 and 8 seconds. For instance, for the data of

Table V the term -\a/B in Eqs. (4) and (5) is 0.0336 for a 1 -second averaging time, but is only 30 one half of that, or 0.0 186, for a 4second averaging time. With the UR/R values thus obtained, the fractional standard deviation cr,/,r in 7. is calculated from:

3 5 35 (6) where:

4 0 AT, + C7-,- TI) l- (7) 40 p aTIf -k -I- F2- /-C, - 1 where: AT,, AT,, T1 and T2 are the durations and times of the numerator and denominator gates as taken as single long gates in the manner illustrated in Figs. 1 3A and 1 3B.

Repeated solutions of Eqs. (3) and (6) are made for different gate sets, and their respective K values from Eq. (7), until it is determined that the minimum aJ7 has been found. Some compromise may be required, since a ratio (gate set) which gives the best results with one background smoothing time may not be optimum with another.

By way of illustration, six different gate sets, each affording a different ratio R, have been 50 selected for the case of Table V (,r = 137.5 gsec and F = 1) as listed below in Table VI. The results obtained from the solution of Eqs. (3) and (6) are shown opposite each ratio for both 1 - second and 4-second background smoothing times. The K value obtained through solution of

Eq. (7) for each ratio is also shown.

16 TABLE V1

1-Sec. Bkgnd. Ave.

Ratio K aR/R alr G, + G, 4-Sec. Bkgnd. Ave.

UR/R alr (1).553 7.33% 4.05% 6.58% 3.64% G8 + G9 + G10 + G, 10 G4+G5 (2).722 5.72% 4.13% 5.35% 3.86% GB2113387A 16 G7 + G8 + G9 + G10 G4+ G, (3).527 7.94% 4.19% 6.87% 3.62% G,+ G,+ G,)+ G, +G12 G4 + G5 20 (4).670 6.02% 4.03% 5.47% 3.67% G, + G, + G, + G,, + G, G, + G, + G, (5) OZ19 7.15% 4.28% 6.37% 3.81% 25 G8 + G9 + Glo + G, G, + G5 (6).598 6.92% 4.14% 6.43% 3.84% G8 + G9 + Glo 30 As may be seen, ratios (1) and (4) yield close to the same minimum value alr when background is averaged for 1 second, whereas with 4-second averaging ratios (1) and (3) are best, with ratio (4) close behind. In this case, therefore, ratio (1) would be the preferred ratio for 35 use where r is within the neighbourhood of 137.5 gsec and F = 1. (See also Table V11 below.) The data of Table VI also shows that there is not a great deal of variation between the best and the worst values of or,/T among all of the ratios. This occurs because the corresponding variation in K tends to compensate for the variation in a,/R with different ratios.

Tables like Tables V and VI are also prepared for other r's within each r range and for all of 40 the other r ranges over the full range of interest, e.g. from 50 gsec to 600 gsec. In general, calculations are preferably made for three T'S within each T range, suitable the mean value and one near or at each extreme of the range. For instance, for the r range of 131.3-143.8 jusec, calculations might be made for r's of 131 gsec, 137.5 gsec and 144jusec. The ratio which best minimizes alr over the entire r range is then selected as the one to be used for that particular 45 range.

The same process is repeated for each of the remaining F values of 1 /V"3, N/_3 and 3 to build up a complete library of ratios for all of the scale factors. Tables V and V], it will be recalled, represent only a single F value, i.e., F = 1, and only a single r, i.e., r = 137.5 ttsec.

It will be appreciated, therefore, that the foregoing calculations will lead to a number of ratios, 50 or gate sets, for each F value, with each ratio corresponding to a particular r range, as aforementioned. The number of ratios used for each F will depend upon the number of F values used and on the desired degree of precision in T. With 417's, it has been found preferable to use seven ratios for each F value. This number of ratios allows precise calculation of r over the full r range associated with each F value. The particular T limits for each ratio and for each F value 55 may of course vary from those described herein, which are illustrative.

In accordance with the foregoing, a representative library of ratios for the full T range of from approximately 50 ttsec to approximately 600 ttsec might be as follows (for convenience, the symbol G has been omitted from the gate numbers):

4 17 GB2113387A 17 TABLE V11

T Range F Ratio R Equation for r 1 +2 5+6+7+8+9 2+3 r< 61.3 jus 1 /V.3 r = 21.9 + 40.4 R 61.3- 68.5 2 7.9 + 42.2 R - 6+7+8+9+10 3+4 63.5- 75.8 33.6 + 43.9 R - 15 7 + 8 + 9 + 10 + 11 4+5 75.8- 83.0 7. = 3 5.4 + 71.6 R 8+9+10+11 20 5+6 83.0- 93.5 = 39.0 + 94.8 R - 9+10+11 +12 25 6+7 93.8-103.3 = 30.9 + 7 5.2 R - 9 + 10 + 11 + 12 + 13 7+8 30 r> 108.3 = 36.5 + 95.0 R-' + 11 + 12 + 13 1 +2 r< 106.3 = 38.0 + 69.9 R 35 5+6+7+8+9 2+3 106.3-118.8 48.4+ 73.1 R 6+7+8+9+ 10 40 3+4 118.8-131.3 58.2+ 76.1 R 7 + 8 + 9 + 10 + 11 45 4+5 131.3-143.8 61.3+124.1 R 8+9+10+11 5+6 50 143.8-162.5 67.6 + 164.2 R 9+10+11 + 12 6+7 162.5-187.5 --- 53.6 + 130.3 R 55 9 + 10 + 11 + 12 + 13 7+8 r> 187.5 63.2 + 164.6 R 10 + 11 + 12 + 13 60 1 +2 7< 184.0 gs V-3 5+6+7+8+9 r= 65.8+121.1 R 18 GB2113387A 18 TABLE V11 (cont.) T Range F Ratio R Equation for r 2+3 5 184.0-205.7 83.7 + 126.7 R 6+7+8+9+10 3+4 205.7-227.3 11 r= 100.9 + 131.8 R-' 10 7 + 8 + 9 + 10 + 11 4+5 227.3-249.0 106.2 + 215.0 R - 8+9+10+11 15 5+6 249.0-281.5 - 78.9 + 266.0 R - 8+9+10+11 20 6+7 281.5-324.8 72.7 + 265.5 R - 9+10+11 +12 7+8 25 > 3 24.8 - 109.4 + 285.0 R - + 11 + 12 + 13 1 +2 < 318.8 3 114.0 + 209.7 R 30 5+6+7+8+9 2+3 318.8-356.3 145.0 + 219.4 R 6+7+8+9+10 35 3+4 356.3-393.8 ---- 111.0 + 206.3 R 6+7+8+9+ 10 40 4+5 393.8-431.3 T = 136.2 + 305.1 R 7 + 8 + 9 + 10 + 11 5+6 45 431.3-487.5 T = 136.7 + 46 1.0 R 8+9+10+11 6+7 487.5-562.5 T = 126.1 + 460.0 R 50 9+10+11 +12 r> 562.5 7+8 r = 139.5 + 494.0 R-' 10 + 11 + 12 + 13 55 There is no simple relationship between R and r from which r may be obtained directly once the ratio has been calculated. However, as each ratio R is used over only a limited range of r, a linear relatioship can be established between R and r which closely approximates the true relationship therebetween. For instance, the dashed curve 298 in Fig. 14 illustrates an example of the true relationship between 7. and R - 1 given by the equation:

19 GB2113387A 19 e- T1 - T1 AT, A-12- (8) 5 (i - C- - r) where the terms AT,, AT2, T1 and T2 are defined according to Figs. 1 3A and 1 3B.

Eq. (8) is solved with assumed values of r over the range 50 gsec to 200 Msec, using the gate set (G, + GJ/(Q, + G, + G10 + G,J, where G4 = 25 gsec, G. and G. = 50 itsec each, and G,, 10 G,0 and G,, = 100 jusee each, and curve 298 of Fig. 14 is the result. In this instance, F = 1. From Table VII, the region of the dashed curve 298 over which the highest accuracy in r is required is from 131.3 tisec to 143.8 gsec, this being the r interval of validity for the particular gate set and F value represented by curve 298. Accordingly, the solid straight- line curve 300 in Fig. 14 is made to fit these points as closely as possible by entering the r and R' values in Eq. 15 (1) for each of these points and solving the resulting simultaneous equations for the values of the coefficients a and b. This gives, for the example of Fig. 14, an a value of 61.3 and a b value of 124. 1.

A solution of the equation for curve 300 in Fig. 14, i.e., r = 61.3 + 124. 1 R - 1, for the R values used in plotting Fig. 14 gives calculated r values as shown in Table Vill, from which it 20 may be seen that the accuracy of the calculated r is 1 % or better over approximately a 2-to-1 T range, namely, from 100 1Asec to 200 jusec.

TABLE Vill

True r R (jusec) Calc. r (gsec) 0.0388 66.1 75 0.1520 80.2 30 0.3194 100.9 0.4340 115.2 0.5133 125.0 137.5 0.6139 137.5 150 0.7147 150.0 35 0.9126 174.6 1.1014 198.0 The values of the coefficients a and b for the remaining combinations of F and gates sets of 40 Table V11 are determined in a like manner to develop the complete library of expressions of Eq.

(1) for use in solving for r, and r,, based on respective measured values of R, and R,. These expressions are also listed in Table VII opposite the corresponding ratios and are also stored in the computer 42 in correspondence with the associated F values and ratio gate set. It will be understood that the values of the coefficients a and b will differ from those set out in Table VII if 45 F values other than 1 1, VC3 and 3 are used or if different gates are used in determining the ratios R.

As mentioned, the counting rates from the various gates used in computing the ratios R, and RF are net counting rates over the accumulation period At. To obtain the net counting rates, it is necessary to determine the background counting rate and subtract the appropriate amount from 50 the gross gate counting rates. As background counting rate is unknown and varies, it must be estimated. Since the background counting rates generally change slowly, it is permissible to average it over a relatively long time, i.e. 4-8 seconds as compared to a normal accumulation period At of 1 second for the gross gate counting rate. It has been found that for the first four sets of gates and equations for each F value in Table VII, it is sufficient to assume that gates 15 55 and 16 contain only background signal, and the gross counting rates N15 and N,, from these gates may simply be accumulated and averaged over the background accumulation period and then subtracted from the gross counting rates from the gates to be used in determining the ratios. In the case of the last three gate sets and equations for each F value, however, it has been found necessary to adjust the coefficients a and b to correct for the presence of a small, 60 but significant, amount of decay signal in the gross counting rates of gates 15 and 16. The manner in which this background adjustment is made may be seen by considering, as an example, the case of F = 1 and R = (G, + GJ/(G,o + G,, + G,, + G,J. First, the true mean counting rates N,, N8, N10, etc. in each of the gates G,, G,, G,,, etc. must be determined. This may be done as described above by use of Eq. (2). For the example at hand, and assuming 65 GB2113387A 20 T = 185 gsec, A,, = 100 and F = 1 and using the neutron burst and detection gate times of Fig.

2, Eq. (2) yields the following---true-decay signal count rates (in cps)in each of the gates of interest: N7 = 881.0, NB = 672.3, N10 = 526.9, N, = 306.8, N12 = 178.8, N, 3 = 164.8, N,, = 18.9 and N, = 6.4. The magnitude of the decay signal which would be subtracted from a 200 gsec time gate along with the background, therefore, would be (N,, + N1J/2 = 12.65 cps. 5

This would give apparent---net-count rates (in cps) for the gates of interest of N7(net) = 881.0 - 12.65/4 = 877.8, NB = 672.3 - 12.65/4 = 669.1, N,o = 526.9 - 12.65/2 = 520.6, N11 = 306.8 - 12.65/2 = 300.5, N12 = 178.8 - 12.65/2 = 172.5 and N1, = 164.8 - 12.65 = 152.2. Similarly, for T = 210 jusec (all other parameters remaining the same), Eq. (2) yields true decay signal count rates (cps) 10 of N7 = 1019.2, NB = 803.0, N,, = 702.8, N11 = 436.8, N12 = 271.6, N1, = 273, N, = 40.6, and N1, = 15.7. Summing the count rates from gates G,, and G,6 and dividing by two, the decay signal subtracted along with background from a 200 gsec gate to obtain the "net" count rate would be 28.15 cps. The respective---net-count rates (in cps) therefore, are N, = 1012.2,

NB = 796.0, N1, = 688.7, N11 = 422.7, N12 = 257.5, N13 = 244.9.

Forming the ratio R = (N7 + NJ/(N1, + N11 + N12 + Nj.) for both T = 185 jusec and T = 210 ttsec, the respective values of R are 1.350 and 1. 1205, with the corresponding values of R - 1 being 0.7407 and 0.8925. The two sets of T's and R's may then be used to solve for the adjusted values of the coefficients a and b in Eq. (1). This gives a= 63.0 and b = 164.7, so that it gates G, and G,, are used for background, the resulting equation for the gate set (N7 + NJ/(1\1,0 + N, + N12 + N1,) is T = 63.0 + 1 64.7R 1. This is not quite identical to the equation for this gate set in Table V11, since that equation was made to fit the---true-T vs. R curve at T's or 187 jusec and 212.5 tisec, whereas T's of 185 and 210 have been used for the purpose of this example. However, the differences between the two equations are quite minor. It will be appreciated, therefore, that the presence of decay signal in the - background- gates G,, 25 and G,, may properly be accounted for in the foregoing way for each of the last three gate sets and equations for all F values.

Eq. (7) for K assumes that there is no significant decay signal in gates G, and G,, but only background signal. An alternative method of determining K, and one which can be used whether or not there is non-negligible signal mixed with background in gates G, and G,, is to 30 calculate a AR - 1 to go with a AT, and then solve for K from:

AT AR T R For example, to find K for the case of F = 1 and T = 200 ttsec using the gate set (G, + G8)/(G10 + G, + G12 + G13) and further using gates G,, and G,, for background, values of R - 1 are computed as before by solving Eq. (2) for the respective gate counting rates and taking the inverse of the ratio for two values of T spaced equally on either side of the T in question, i.e. 40 T = 200 gsec. Hence, for exanple, for T = 213 gsec and 187 ttsec, for a AT of 26 ttsec, values of R - 1 of 0.9 105 and 0.7527, respectively, are obtained, for a AR - 1 of 0. 1578. For the mean T of 200 gsec, the mean R - 1 is 0.8316. K is then readily obtained from Eq. (8) by inserting 200 tisee for T, 0.8316 for R- 1, 26 ILsec for AT and 0. 1578 for AR - 1, giving for K a value of 0.685. This value is then used in Eq. (6) to determine the fractional standard deviation in T.

As noted above, the same time gates are used for the far detector 26 as for the near detector 24, i.e., NG, = FG, NG, = FG,... NG, = FG,., and the same F value, selected on the basis of new T,, is also used for both detectors. Likewise, TF is calculated based on the same type of equation as T, i.e., the equations of Table V[[, but using of course the counting rates from the far-detector gates. Background correction of the far-detector counting rates, and of the coefficients a and b if needed, is made in the same manner as described above in connection with the near detector. Because T, tends to be larger then T, the first gate chosen for calculating T, is generally less than 2 XTF from the end of the neutron burst. While this does not seriously affect the value Of T,, having the far-detector gates begin closer than 2 X T, affords the substantial statistical advantage of significantly increasing the counting rates in the far-detector 55 gates. For instance, if T, is 1. 15 X T,, the far-detector counting rates F, F,... F,, are on the order of 1. 3 times higher than would be the case if 7-F equalled TN. The fact of TF being larger than T, does result in relatively more decay signal in gates FGI,, and FG16. This effect, however, does not appear significant, and at the most T. might be decreased as a result thereof by about 1 % when TF = 1.15 7-,. An important benefit Of TF is that it is substantially free of neutrondiffusion effects. It is, therefore, quite useful for applications where diffusion effects must be considered.

Once 7-, and TF have been determined, I, and IF: can readily be computed using the expression:

21 GB2113387A 21 4550 where 1 is in capture units and r,, or r,, is in gsec.

It may also be desirable to obtain a ratio, generally designated the N/F ratio, of the counting rates from certain near and far detector gates. Such a ratio, plotted against IN and/or IP 'S useful in obtaining apparent values of porosity and water salinity in accordance with U. S.

patent No. 3,971,935, granted July 27, 1976 to W. B. Nelligan. The ratio N/F may take various forms, but preferably is formed from the gates used in computing r plus all intermediate gates. For example, for the case of F = 1 and R = (G, + G70G, + G10 + G, + G12 + G13) a suitable form of the ratio would be:

N N, + N, + N, + N, + NjO + N11 + N12 + N13 F F6 + F7 + F8 + F9 + F10 + F, + F12 + F13 (10) where N, N13 and F6,... F13 are net counting rates averaged over the accumulation period 2 0 At.

As noted above, the telemetry circuits 34 and 36 may comprise any suitable bi-directional telemetry system, and the details thereof do not form a part of the present invention.

Attention is directed to out co-pending Patent Applications Nos. 79 35 429 (Publication No.

2 036 303), 8228823 (Publication No.) and 8228889 (Publication No.

Claims (2)

1. A method for providing a background-compensated measurement of the level of induced radiation within an earth formation, comprising:

(a) irradiating an earth formation with a discrete burst of neutrons during each of a succession of irradiation intervals; (b) detecting indications of the level of radiation in the formation during at least a first detection interval occurring at a first time within each irradiation interval; (c) detecting indications of the level of background radiation during a second detection interval occurring at a second time within each irradiation interval; (d) measuring the average level of said first detected indications over a first plurality of said 35 irradiation intervals; (e) measuring the average level of said second detected indications over a second, greater pluralily of said irradiation intervals; and (f) combining said first and second measurements to provide a first background-compensated measurement of the average level of induced radiation in the formation.

CLAIMS (16 Mar 1983) 1. A method for providing a background-compensated measurement of the level of induced radiation within an earth formation, comprising:

(a) irradiating an earth formation with a discrete burst of neutrons during each of a succession 45 of irradiation intervals; (b) detecting indications of the level of radiation in the formation during at least a first detection interval occurring at a first time within each irradiation interval, said detection interval being subsequent to said neutron burst; (c) detecting indications of the level of background radiation during a second detection 50 interval occurring at a second time within each irradiation interval; (d) measuring the average level of said first detected indications over a first plurality of said irradiation intervals; (e) measuring the average level of said second detected indications over a second, greater plurality of said irradiation intervals; and (f) combining said first and second measurements to provide a first background-compensated measurement of the average level of induced radiation in the formation.

2. Apparatus for providing a background-compensated measurement of radiation levels in an earth formation traversed by a borehole, comprising:

(a) means arranged to irradiate an earth formation surrounding the borehole with a discrete 60 burst of neutrons during each of a succession of irradiation intervals; (b) means arranged to detect, during a first detection time period within each irradiation interval, said time period being subsequent to said neutron burst, radiation resulting from a first type of interaction between said neutrons and earth formation elements to be measured and from background sources; 22 GB2113387A 22 (c) means arranged to detect, during a second detection time period within each irradiation interval, radiation resulting from said background sources; (d) means arranged to measure the average level of said first-detected radiation over a first measurement period encompassing a plurality of said irradiation intervals; (e) means arranged to measure the average level of said background radiation over a second 5 measurement period encompassing a greater plurality of said irradiation intervals than said first measurement time period; and (f) means arranged to combine said first-detected radiation measurement and said background radiation measurement to compensate said first-detected radiation measurement for the presence within said first detection period of background-radiation.

Printed for Her Majesty's Stationery Office by Burgess & Son (Abingdon) Ltd-1 983. Published at The Patent Office. 25 Southampton Buildings. London. WC2A 'I AY, from which copies may be obtained 11 'I Ir