GB2110482A

GB2110482A - Inverter

Info

Publication number: GB2110482A
Application number: GB08228357A
Authority: GB
Inventors: Yoshihide Kimbara
Original assignee: Mitsubishi Electric Corp
Current assignee: Mitsubishi Electric Corp
Priority date: 1981-10-07
Filing date: 1982-10-05
Publication date: 1983-06-15
Also published as: DE3237220A1; JPH0121704B2; JPS5863081A; GB2110482B

Abstract

The inverter includes a pair of controlled switches 12, 14, e.g. MOSFETs or transistors with reverse parallel connected diodes, connected to a d.c. source 10 and to an output terminal 100, and a respective current and voltage limiting circuit 44, 48; 46, 50 connected to the positive terminal of each switch as shown. In the embodiment shown each limiting circuit comprises a current-limiting reactance 44, 46 bridge by a voltage absorbing diode-resistor series circuit 48, 50. In an alternative embodiment the reactance is replaced by a ferrite core. The two switches may be arranged with another four of such switches and limiters to form a bridge and each arm of the bridge may include parallel connected switches. The inverter may be used to drive a silent discharge excitation laser. <IMAGE>

Description

SPECIFICATION Inverter This invention relates to inverters, and more particularly, to an inverter of this type is as shown in Figure 1 in the inverter, the positive terminal of a power source 10 is connected to the drain 1 2a of a first field-effect transistor 12 (hereinafter referred to as "a MOSFET" when applicable). The source 1 2b of the MOSFET 12 is connected to the drain 1 4a of a second MOSFET 14, and the source 1 4b of the second MOSFET 14 is connected to the negative terminal of the power source 10, to form a closed loop. The gates 1 2c and 1 4c of the first and second MOSFETS 12 and 14 are connected to gate drive circuits 1 6 and 18, respectively.

When a MOSFET is used as a switching element as described above, the equivalent circuit of the MOSFET is as shown in Figure 2. In Figure 2, a first electrostatic capacitance 20 is established between the drain 1 2a and the gate 12c, a second electrostatic capacitance 22 is established between the date 12c and the source 12b, and a third electrostatic capacitance 24 is established between the gate 1 2c and the source 12b. A resistor 26 is connected in series to a switch 28 which is controlled by a voltage between the source 1 2b and the gate 1 2c when the MOSFET 12 is rendered conductive (ON). A reverse diode 30 is connected between the drain 1 2a and the source 12b.

The operation of the prior art circuit shown in Figure 1 2 will now be described. When the first MOSFET 12 is rendered conductive by the output of the gate drive circuit 1 6, the potential of the output terminal 100 is raised to the potential V+ of the power source 10. When the MOSFET 12 is rendered non-conductive (OFF) and the second MOSFET 14 is rendered conductive (ON) by the output of the gate drive circuit 18, the voltage between the drain 1 4a and the source 1 4b of the MOSFET 14 is changed to 0 volts from V+, and the voltage between the drain 1 2a and the source 1 2b of the MOSFET 12 is changed abruptly by V+. In this manner, the potential of the output terminal 100 is inverted from +V to -V.

Figures 3A-3G show the timed operation of the various components of the circuit shown in Figure 1. More specifically, Figure 3A shows the switching states of the MOSFET 12, Figure 3B shows the switching states of the MOSFET 14, Figure 3C shows the potential of the output terminal 100, Figure 3D shows the drain current of the MOSFET 12, Figure 3E shows the drain current of the MOSFET 14, Figure 3F the voltage between the source 1 2b and the gate 1 2c of the MOSFET 12, and Figure 3G shows the voltage between the source 14b and the gate 14c of the MOSFET 14.

As is apparent from Figure 3E, which the MOSFET 14 is rendered conductive, current flowing through the electrostatic capacitance 20-24 flows in the MOSFET 14, creating an over-current 34. Similarly, when the MOSFET 12 is turned on, an over-current 32 flows as shown in Figure 3D. As a result, voltage drops 36 and 38 (as shown in Figures 3F and 3G) develop across the electrostatic capacitance 22. When each voltage drop respectively reaches the threshold voltges 40 and 41 of the MOSFETS 12 and 14, respectively, the switch 28 in Figure 2 is turned on, rendering the MOSFETS conductive. When the MOSFETS 1 2 and 14 are in their respective conductive states, the power source 10 is thus short-circuited.

In the conventional inverter, as described above, over-current flow during switching such that the MOSFET which has been non-conductive is rendered conductive by being affected by the over-current of the MOSFET which is rendered conductive, short-circuiting the power source. As a result, the MOSFETS and the power source may be destroyed. Accordingly, it has been difficult heretofore to form an inverter with MOSFETS which performs a high speed switching operation under high voltage.

In view of the foregoing, an object of this invention is to provide an inverter in which the switching operation is carried out in a stable manner.

An inverter in accordance with the invention comprises first switching means having first and second inputs and an output; first driving means connected to said first input of said first switching means for driving said first switching means; second switching means having first and second inputs and an output; second driving means connected to said first input of said second switching means for driving said second switching means; first limiting means connected between said positive terminal of said power source and said second inputs of said first switching means for limiting both a voltage and a current at said second input of said first switching means; output means connected to said output of said first switching means for outputting said inverted reference voltage; second limiting means connected between said output means and the second of said inputs of said second switching means for limiting both voltage and a current at said second input of said second switching means; and said output of said second switching means being connected to said negative terminal of said power source.

In the accompanying drawings Figure 1 is a circuit diagram of a conventional inverter; Figure 2 is an equivalent circuit diagram of a standard MOSFET; Figures 3A-3G show the waveforms of the various circuit elements of Figure 1; Figure 4 is a circuit digram of a first exemplary embodiment of the present invention; Figures 5A-5G show the waveforms of the various circuit elements of Figure 4; Figure 6 is a circuit diagram showing a second exemplary embodiment of the invention; Figure 7 is a circuit diagram showing a third exemplary embodiment of the invention; Figure 8 is a circuit diagram showing a fourth exemplary embodiment of the invention; Figure 9 is a circuit diagram showing a fifth exemplary embodiment of the invention;; Figure 10 is a circuit diagram showing a sixth exemplary embodiment of the invention; Figure 11 is a circuit diagram showing a power source employed in the above-described embodiments of the invention; and Figure 1 2 is a circuit diagram showing a circuit in which an example of an inverter according to the invention is employed as a power source of a silent discharge excitation laser oscillator.

A first embodiment of the present invention is as shown in Figure 4 wherein components which have been previously described with reference to Figure 1 are similarly numbered. Reactors 44 and 46 are connected in series to the drains 1 2a and 1 4a of the MOSFETS 12 and 14, respectively.

Over-voltage absorbing circuits 48 and 50 are connected in parallel to the reactors 44 and 46, respectively. The over-voltage absorbing circuits 48 and 50 are made up of diodes 52 and 56 and resistors 54 and 58, respectively.

Figures 5A-5G are time charts indicating the operation of the circuit in Figure 4. Figures 5A 5E show the voltage waveforms of the same devices as shown in Figures 3A-3E, respectively. Figures 5F and 5G show the voltages of the over-voltage absorbing circuits 48 and 50, respectively.

In the circuit in Figure 4, the drain currents of the MOSFETS 12 and 14 are limited by the reactors 44 and 46, respectively, so that the overcurrents 60 and 62 are small as indicated in Figures 5D and 5E. In this case, current limitation can be achieved even when a capacitive load is connected to the output terminal 100. When the MOSFETS 12 and 14 are rendered nonconductive (OFF), the over-voltage absorbing circuits 48 and 50 attenuate the voltages developed across the reactors 44 and 46 as indicated in Figures 5F and 5G, respectively, in order to reduce the over-voltages which may be caused by currents flowing in the reactors 44 and 46. It is preferable that the diodes 52 and 56 as shown in Figure 4 be high-speed switching types and that the resistors 54 and 58 be non-inductive types.

Figure 6 shows a second embodiment of the invention. The arrangement of the second embodiment is such that ferrite cores 64 and 66 are employed instead of the reactors 44 and 46 in Figure 4. The ferrite cores, having a magnetic permeability 4 in order to 1000 to 3000 ,uH operate as reactors of 1000 to 2000 ,uH merely by inserting a wire thereinto. The ferrite cores operate to attenuate high frequency components, and accordingly prevent parastic oscillation which may be caused by the MOSFETS during high frequency operations. In this manner, the ferrite cores carry out stable switching operations.

Figure 7 shows a third embodiment of the present invention. The third embodiment is a single-phase inverter in which the series circuit of the MOSFETS 12 and 14 is connected in parallel to a series circuit of MOSFETS 68 and 70. The drains 68a and 70a of the MOSFETS 68 and 70 are connected to reactors 72 and 74, respectively. The gates 68c and 70c are connected to gate drive circuits 76 and 78, respectively. Reactor 72 is connected to an overvoltage absorbing circuit 88 consisting of a series circuit of a diode 80 and a resistor 82. Similarly, reactor 74 is connected to an over-voltage absorbing circuit 90 comprising a series circuit of a diode 84 and a resistor 86.

In the third embodiment, the inverter output of a load 92 can be made twice as high as that of the first embodiment. In the case where the load 92 is inductive, reverse voltages may be applied to the MOSFETS; however, owing to the reverse diodes 30 included in the MOSFETS and the provision of the reactors 44, 46, 72 and 74 and the over-voltage absorbing circuits 48, 50, 88 and 90, the integrity of the MOSFETS will not be affected.

Figure 8 shows a fourth embodiment of the invention, which is obtained by replacing the MOSFETS 12, 14, 68 and 70 in the third embodiment by a parallel circuit of a transistor 110 and a diode 112, a parallel circuit of a transistor 114 and a diode 11 6, a parallel circuit of a transistor 118 and a diode 120, and a parallel circuit of a transistor 122 and a diode 124.

Diodes 112, 116, 120 and 124 are provided in order to prevent the above-mentioned reverse voltages (that is, they perform the same function as the reverse diodes 30 of the MOSFETS).

Figure 9 illustrates a fifth embodiment of the invention. When the MOSFET circuits are connected in parallel in this manner, equal currents will not flow because the "on" resistors 26 in the equivalent circuits of the MOSFETS (Figure 2) are not equal to each other. In order to overcome this difficulty, current balancing resistors 126 through 132 and 126' through 132' are connected in series to the reactors in the drain circuits. Each current balancing resistor has a resistance which is substantially equal to that of the "on" resistor in the MOSFET, generally 0.1 to 1Q.

Figure 10 is a circuit diagram showing a sixth embodiment of the invention in which, instead of the reactors in Figure 9, ferrite cores 134, 136, 138 and 140, and ferrite cores 134', 136', 138' and 140' are employed.

While single-phase inverters according to the invention have been described, it is within the scope of the present invention that a three-phase inverter can be provided by using three circuits according to the first embodiment, and that a poly-phase inverter can be provided by using a plurality of circuits according to the first embodiment.

Figure 11 shows an example of the power source 10 which is employed in the abovedescribed embodiment. Three phase alternate currents R, S and T are phase-controlled by thyristors 142, 144, 146, 148, 150 and 152 and the resultant output is rectified by a reactor 1 54 and a capacitor 1 56 to obtain a predetermined DC voltage.

Figure 12 shows one example of a circuit in which an inverter 1 58 with MOSFETS according to the invention is employed as a silent discharging power source in a silent discharge excitation laser oscillator 1 60. The output of the inverter 1 58 is converted into a high voltage by a boosting transformer 162, which is applied to electrodes 1 64 and 1 66 the surfaces of which are covered with dielectric material. The silent discharge excitation laser oscillator 1 60 is filled with laser medium gas 168. When silent discharge 1 70 is produced, laser oscillation is effected between a total-reflection mirror 1 72 and a partially transparent mirror 1 74 to produce an output laser beam 1 76. The output frequency of the inverter 1 58 as the silent discharging power source is 50 to 200 KHz. This output frequency is not practical with transistors or thyristors; hence, the MOSFET inverter of the present invention is particularly suited to serve as the silent discharge power source for a laser oscillator.

As is apparent from the above description, in the invention, the parallel circuits of the reactors and the over-voltage absorbing circuits are connected to the drain or source circuits of the MOSFETS, whereby the flow of over-currents in the MOSFETS can be prevented. Accordingly, the switching problems inherent in the MOSFET inverters of the prior art are reduced with the result that the power source and the MOSFETS are protected from damage. In the inverter according to the invention, no parastic oscillation occurs with high frequency, and stable switching can be achieved.

Claims

1. An inverter for inverting a reference voltage supplied by a power source having a positive terminal and a negative terminal, comprising: first switching means having first and second inputs and an output; first driving means connected to said first input of said first switching means for driving said first switching means; second switching means having first and second inputs and an output; second driving means connected to said first input of said second switching means for driving said second switching means; first limiting means connected between said positive terminal of said power source and said second inputs of said first switching means for limiting both a voltage and a current at said second input of said first switching means; output means connected to said output of said first switching means for outputting said inverted reference voltage;; second limiting means connected between said output means and the second of said inputs of said second switching means for limiting both voltage and a current at said second input of said second switching means; and said output of said second switching means being connected to said negative terminal of said power source.

2. The inverter as claimed in claim 1, wherein said inverter further comprises: a third switching means having first and second inputs and an output; a third driving means connected to said first inputs of said third switching means for driving said third switching means; a fourth switching means having first and second inputs and an output; a fourth driving means connected to said first inputs of said fourth switching means for driving said fourth switching means; a third limiting means connected between said positive terminal of said power source and said second input of said third switching means for limiting both a voltage and a current at said second input of said third switching means; said output means being connected at an intersection point to said output of said third switching means;; a fourth limiting means connected between said intersection point and the second input of said fourth switching means for limiting both a voltage and a current at said second input of said fourth switching means; said output of said fourth switching means being connected to the output of said second switching means.

3. The inverter as claimed in claims 1 or 2, wherein said first and second switching means are MOSFET devices.

4. The inverter as claimed in claims 1 or 2, wherein said first and second switching means comprise first and second transistors each of which having an emitter, a base and a collector, each of said transistors having a diode connected across said collector and said emitter for maintaining a preset voltage polarity therein.

5. The inverter as claimed in claims 1 or 2, wherein said first and second limiting means comprise first and second current limiting means and first and second voltage absorbing means connected in parallel to said first and second current limiting means, respectively.

6. The inverter as claimed in claim 5, wherein said first current limiting means comprises a first reactance, and wherein said second current limiting means comprises a second reactance.

7. The inverter as claimed in claim 6, wherein said first and second reactances comprise ferrite cores.

8. The inverter as claimed in claim 5, wherein said first and second voltage absorbing means comprise series circuits of a diode and a resistor.

9. The inverter as claimed in claim 2, wherein said third driving means comprises a first connecting means for interconnecting said third switching means and said first driving means and said fourth driving means comprises a second connecting means for interconnecting said fourth switching means and said second driving means.

10. The inverter as claimed in claim 9, wherein said first and second limiting means each comprise a first series circuit of a reactance and a current balancing resistor and a second series circuit of a diode and a resistor, said second circuit being connected across said first circuit.

11. The inverter as claimed in claim 9, wherein said reactance comprises a ferrite core.

12. An inverter for inverting a reference voltage from a voltage source having a positive terminal and a negative terminal comprising: a first transistor having a gate, a source, and a drain; a second transistor having a gate, a source, and a drain, and said source of said second transistor being connected to said negative terminal of said voltage source; an inverting terminal connected to said source of said first transistor for outputting said inverted reference voltage; first current limiting means connected between said drain of said first transistor and said positive terminal of said voltage source for limiting a current received by said first transistor; first driving means connected to said gate of said first transistor for rendering said first transistor conductive;; second driving means connected to said gate of said second transistor for rendering said second transistor conductive; second current limiting means connected between said inverting terminal and said drain of said second transistor for limiting a current received by said second transistor; first voltage absorbing means connected across said first current limiting means for absorbing overvoltages developed therein; and a second voltage absorbing means connected across said second current limiting means for absorbing over-voltages developed therein.

1 3. In a silent discharge excitation laser oscillator of the type comprising a boosting transformer having a primary and a secondary, a gas chamber with gas therein, a plurality of electrodes within said gas chamber and connected across said secondary of said boosting transformer, a plurality of mirrors within said gas chamber describing a light path between said electrodes, one of said mirrors being partially reflective and partially transmissive to output a laser beam, the improvement comprising:: a power source connected to said primary of said boosting transformer, comprising; first switching means having first and second inputs and an output; first driving means connected to said first input of said first switching means for driving said first switching means; second switching means having first and second inputs and an output; second driving means connected to said first input of said second switching means for driving said second switching means; first limiting means connected between said positive terminal of said power source and said second inputs of said first switching means for limiting both a voltage and a current at said second input of said first switching means; output means connected to said output of said first switching means for outputting said inverted reference voltages; ; second limiting means connected between said output means and the other of said inputs of said second switching means for limiting both voltage and a current at said second input of said second switching means; and said output of said second switching means being connected to said negative terminal of said power source.