GB2107950A - Analogue pulse-density modulator - Google Patents

Abstract

A pulse density modulator, for an analogue to digital converter, is characterised in that the integrators thereof are comprised by switched capacitors whereby to facilitate embodiment using MOS LSI technology. A first integrator circuit (A) has an analogue signal input and outputs to a second integrator circuit (B), which is also input by a proportion and of the analogue signal input. The second integrator circuit (B) outputs to a comparator (21) with a subsequent clocked bistable (22), which has an output (from Q) which comprises a pulse density modulated digital version of the analogue input signal, and a complementary output (P from Q) which is input to both integrator circuits (A, B). Simplified versions of the pulse density modulator circuit are outputs to a second integrator circuit described with reference to Figures 8 and 9 (not shown), in which the analogue input is fed to integrator circuit A only. <IMAGE>

Description

SPECIFICATION Analogue pulse-density modulator This invention relates to an analogue-to-digital converter and in particular to an analogue pulsedensity modulator for use therein.

According to the present invention there is provided an analogue pulse-density modulator including a modulator input terminal first and second integrators, the first integrator being connected from the modulator input terminal and having an output connected to an input of the second integrator, a bistable device to whose input the output of the second integrator is applied, means for clocking the bistable device at a predetermined rate, and a modulator output terminal, wherein, when an analogue signal is applied to the modulator input terminal, one bistable device output provides a digital signal pulse density modulated at the clock rate to the modulator output terminal and another bistable device output provides a signal complementary to the digital signal to both the first and second integrators, and wherein the integrators are comprised by switched capacitors.

Embodiments of the present invention will now be described with reference to the accompanying drawings, in which: Fig. 1 illustrates, schematically, an analogue-to-digital converter employing pulse density modulation: Figs. 2a and 2b illustrate part of an analogue pulse density modulator adapted from Fig. 8 of our British Patent Specification No. 1 450,989 (E.H. Lambourn -- 8) and a rearrangement thereof, respectively; Fig. 3a illustrates an RC integrator circuit and a switched capacitor equivalent thereof; Fig. 3b shows the switching sequence for the switched capacitor arrangement of Fig. 3a; Fig. 4 illustrates an RC T-junction integrator circuit and a switched capacitor equivalent thereof; Fig. 5 shows a pulse density modulator (digital decoder) circuit derived from Figs. 2a and 2b; Fig. 6 shows a pulse density modulator (digital decoder) circuit as disclosed in our co-pending application No. 81/31145 (Serial No. ) (E.H. Lambourn -- 13); Fig. 7 shows a switched capacitor pulse density modulator (analogue-to-digital) according to one embodiment of the present invention and the switching sequence therefor; Fig. 8 shows a simplified version of the embodiment of Fig. 7, and Fig. 9 shows another simplified version of the embodiment of Fig. 7.

Our British Patent Specification No. 1,450,989 (E. H. Lambourn -- 8) relates to an anaiogue-todigital converter with an analogue pulse density modulator which converts analogue samples into a pulse density modulated stream with the same characteristics. In Fig. 1 a continuous analogue signal is input to an analogue pulse density modulator 1 which is clocked with a clock frequency fc and whose output is a sigma-delta type binary stream modulated at the clock rate. This output signal is applied to a conversion filter comprising a digital filter 2, which is also clocked with the clock frequency fct whose output comprises linear p.c.m. M-bit words at an intermediate sampling frequency f,.

Fig. 2a shows part of an analogue pulse density modulator adapted from Fig. 8 of Patent Specification No. 1,450,989 and comprising an operational amplifier A and a bistable device B together with an additional bistable device B' and a dashed path comprising an optional feedback loop. Fig. 2b shows a convenient rearrangement of Fig. 2a, including two adders 5 and 6, a multiplier 7 and a bistable device b", the values of R1, R2, C1 and C2 are not the same as in Fig. 8 of Patent Specification No. 1,450,989.

Now, when working in discrete time intervals a simple RC integrator circuit (left hand side of Fig.

3a) can be replaced by two switched capacitors comprising capacitors C1 and C2 with switches SW1 and SW2 (right hand side of Fig. 3a), with a switching sequence as shown in Fig. 3b.

When the switches SW1 and SW2 are both open the charge on capacitor C1 and q1 and that on capacitor C2 is stil Q1, V still being V,. When switch SW1 is open and switch SW2 is closed the charge on capacitor C, is q3 whilst that on capacitor C2 is Q2, the value of V being V2. Now, q2 = E.C1, when SW1 is closed and SW2 is open and when SW1 is subsequently opened and SW 2 is closed Q2 = (E.C1 + Q,) C2/(C, + C2), and V2 = Q2/C2.

Thus Q2 Q1.C2/(C1 + (:2) + q2.C2 (Cr + C2) Q2 = Q,.C2/(C1 + C2) + E.C2.C,/(C, + C2) Q2=Q1.K + E.C2.(1-K) (1) where K = C2/(C1 + C2), (1-K) = C1/(C1 + C2) and C2=C1.K/(1-K) Also, V2 = Q2/C2 = Q1.K/C2 + E (1-K) V2=V1.K + E(1-K) (2) For the simple RC circuit (left hand side of Fig. 3a), however, V2 = V1.e T/CR + E.(1--e-CR) V2=V1.K + E(i-K) (3) where K = e-T/CR and T is the time period, thus showing that the left and right hand sides of Fig. 3 are equivalent.

Fig. 4 shows an equivalent switched capacitor circuit (right hand side of Fig. 4) for an RC Tjunction integrator circuit (left hand side of Fig. 4). In this case the same formulae are used, but R is equal to R1 and R2 in parallel, K = C2/(C, + C2 + C3) and (1-K) = (C1 + C3)/(C1 + C2 + C3). Therefore, V2 1= V11. K + E&alpha;1. (1-K) + Pa2 (1 -K) (4). If C1 = C3, equivalent to R1 = R2, then 1 and 2 both equal 0.5. This same reasoning can be applied to any number of capacitors.

In order to create a switched capacitor replica of the pulse density modulated type (analogue to digital) as described in Specification No. 1,450,989, and partly shown in Fig. 2a, and alternatively in Fig.

2b, it should be possible to directly replace the relevant RC integrator circuit by the switched capacitor equivalent, but this is not strictly true since the circuit of specification No. 1,450,989 works as a continuous function, whereas those in Figs. 2a and 2b are discrete. Therefore, the correct method is based on the derived analogue formulae quoted hereinafter that refer to the block diagram shown in Fig.

5, which shows a direct digital version of Fig. 2b. These derived analogue formulae and the direct digital block diagram are also described in our co-pending application No. (Serial No. 81/31145) (E. H.

Lambourn - 13) which discloses a digital pulse density modulator (digital decoder). The direct digital version of Fig. 2b shown in Fig. 5 comprises adders 8, 9 and 10, an X-bit storage resistor 11, a Y-bit storage resistor 12, a digital comparator and ROM (read only memory) 13 and six multipliers 21 to 26 with constants K1 to K6 respectively whose values are obtained from the analogue simulation formulae quoted hereinafter. The registers 11 and 12 and the comparator 13 present a delay of Z~' as one clock period equal to T = 1/f, and comparator 13 presents a number +P according to whether V3 is negative or positive at the outset of a clock pulse at time T, 2T, 3T etc.

The terms V0 1 and VD3 represent the delayed stored numbers in registerss 11 and 12, respectively, and V1 1 and V13 the resultant number at the onset of an imminent clock pulse. The comparator 13 at this point in time assume the value logical 1 or logical 0 according to the polarity of V13, being 0 if V13 is positive. The output is therefore a binary stream representing the input digital signal as a pulse-density modulated 1 bit signal, which can be demodulated to an analogue signal by a simple R.C. filter (not shown).

The derived analogue simulation formulae employed for Fig. 5 are as follows: V13 = Vo3.K2 + Vo1.(K1- K2) /(1-R2C2/R1C1)+ +'u.(1-K2) - .#(K1 - K2)/(1 -R2C2/R,C1)+ + P0(1-K2) and V11 =Vo1.K1 + S (1K1) where K1 = eC1R1, K2 = e-C2R2. + P + E If K=1I(1--R,CdR, K 1/(1-R2C2/R1C1) V13 = Vo3.K2 + V,1.K(K1--K2) iu + ,u (1-K2) - u.K.S (K1-K2) + P0(1-K2).

If (K1-K2) = K4, V13 = Vo3.K2 + V01 .K.K4 + . (1--K2--K2.K4) + Po(1--2) + P0 (1-K2) If .K.K4 = K6, (1--K2- K2.K4)= K5,(1 -K1)= K4 and (1-K2)=K3.

Then V13 = V,3.K2 + V,1 .K6 + 8.K5 + Po.K3 and V11 =Vo1.K1 +SK4.

One particularly advantageous arrangement of the Fig. 5 circuit is shown in Fig. 6, which is substantially equivalent to Fig. 7 of our co-pending Application No. 81/31145 referred to above. In our co-pending Application this circuit is employed as a digital decoder, A and B comprising non-recursive filters in this instance and when the output thereof is applied to, for example, a simple RC filter for demodulation purposes, the overall arrangement converts digital signals to analogue signals. The basic circuit is however a pulse density modulator which can be employed in an analogue to digital converter, when A and B comprise integrators, as well as a digital to analogue converter.

Fig. 7 is a switched capacitor equivalent of Fig. 6. Blocks A and B of Fig. 7 are equivalent to blocks A and B of Fig. 6 respectively. The circuit of Fig. 7 is thus designed to be a switched capacitor pulse density modulator for use in an analogue to digital converter, that is an analogue pulse density modulator. An analogue input signal is applied to a buffer amplifier 20 which compares it with a d.c.

reference signal. The resultant output signal is applied to the various components of integrators A and B in accordance with the switch sequence shown. Basically, an analogue signal is input to a first integrator circuit A which outputs to a second integrator circuit B, which is also input by a proportion of the first mentioned analogue input signal. Circuit B outputs to a comparator 21 which compares its input from circuit B with a d.c. reference levei and outputs to a clocked bistable 22, which also provides a complementary output (Q) to the integrator circuits A and B respectively. The Q output of bistable 22 is a binary sigma-delta type signal which is modulated at the clock rate and can be applied to a digital filter (not shown) as described with respect to Fig. 1 when the pulse density modulator of Fig. 7 is employed in an analogue to digital converter. The circuit of Fig. 7 includes capacitors C1 1 to C17, switches S11 to S20 an input buffer 23 by means of which the analogue input signal is compared with the d.c. reference level, and buffers 24 and 25. The bistable is clocked by the clock signal fcw The switching sequence is shown in the table in Fig. 7. The alternate switching of capacitors causes charge redistribution as described above.At the end of each switching sequence the bistable is clocked as indicated in the table by the transition from logical 0 to logical 1, and the comparator output is stored for use during the following cycle.

There are various other circuits which will model the formulae quoted above, some of which require more or less capacitors. The use of switched capacitor equivalents of RC integrator circuits facilitates the fabrication of integrated circuits, since discrete analogue components are dispensed with in favour of integrated capacitors which are particularly suitable for embodiment by MOS LSI technology.

Figs. 8 and 9 show two simplified versions of Fig. 7 and the associated switching sequences. In the Fig. 8 arrangement the analogue signal input is applied solely to integrator A, thus eliminating capacitor C14 and switches S15 and S19. In the Fig. 9 arrangement, the analogue signal input is also applied solely to integrator A, from which capacitor C12 has been removed and instead arranged between the input and output of the buffer 24. Switches S1 5 and S 9 together with capacitor C14 have been eliminated, whilst capacitor C17 has been arranged between the input and the output of comparator 21. An inverter 26 has been arranged between the output of buffer 25 and switch S18.

Thus this arrangement employs Miller integrators.

Claims (11)

1. An analogue pulse density modulator including a modulator input terminal, first and second integrators, the first integrator being connected from the modulator input terminal and having an output connected to an input of the second integrator, a bistable device to whose input the output of the second integrator is applied, means for clocking the bistable device at a predetermined rate, and a modulator output terminal, wherein, when an analogue signal is applied to the modulator input terminal, one output of the bistable device provides a digital signal pulse density modulated at the clock rate to the modulator output terminal and another output of the bistable device provides a signal complementary to the digital signal to both the first and second integrators, and wherein the integrators are comprised by switched capacitors.

2. A pulse density modulator as claimed in claim 1, wherein the first integrator comprises first, second, third and fourth switches connected in series between the modulator input terminal and the other bistable output, and first, second and third capacitors, wherein one electrode of each capacitor is connected from between a respective pair of switches, wherein the other electrodes of the capacitors are connected together, and connected to earth in use of the modulator, wherein the one electrode of the second capacitor is connected to the outer of the first integrator, and wherein in use of the modulator the switches are operated in accordance with a predetermined switching sequence.

3. A pulse density modulator as claimed in claim 1, wherein a buffer amplifier is arranged between the output df the first integrator and the input of the second integrator, wherein the first integrator comprises, first, second, third and fourth switches connected in series between the modulator input terminal and the other bistable output, and first and third capacitors, one electrode of the first capacitor being connected from between the first and second switches, one electrode of the third capacitor being connected from between the third and fourth switches, wherein the other electrodes of the first and third capacitors are connected together, and connected to earth in use of the modulator, wherein the output of the first integrator is connected from between the second and third switches to the buffer amplifier, and including a second capacitor connected between the input and output of the buffer amplifier.

4. A pulse density modulator as claimed in claim 2, wherein the modulator input terminal is also connected directly to the second integrator, wherein the second integrator comprises fifth, sixth, seventh and eighth switches connected in series between the modulator input terminal and the other bistable output, fourth, fifth, sixth and seventh capacitors and ninth and tenth switches, wherein one electrode of the fourth capacitor is connected from between the fifth and sixth switches, wherein one electrode of the fifth capacitor is connected via the ninth switch to the input of the second integrator and via the tenth switch from between the sixth and seventh switches, wherein on electrode of the sixth capacitor is connected from between the seventh and eighth switches, wherein one electrode of the seventh capacitor is connected from between the sixth and seventh switches, wherein the other electrodes of the fourth, fifth, sixth and seventh capacitors are connected together, and connected to earth in use of the modulator, and wherein the output of the second integrator is connected from between the sixth and seventh switches.

5. A pulse density modulator as claimed in claim 2, wherein the second integrator comprises tenth, eleventh, twelfth and thirteenth switches connected in series between the input of the second integrator and the other bistable output, and eighth, ninth and tenth capacitors, wherein one electrode of each of the eighth, ninth and tenth capacitors is connected from between a respective pair of the tenth, eleventh, twelfth and thirteenth switches wherein the other electrode of the eighth, ninth and tenth capacitors are connected together, and connected to earth in use of the modulator.

6. A pulse density modulator as claimed in claim 4 or claim 5, wherein the output of the first integrator is connected to the input of the second integrator via buffer amplifier.

7. A pulse density modulator as claimed in any one of the preceding claims, wherein the output of the second integrator is applied to the input of the bistable via a comparator serving to compare it with a d.c. reference signal.

8. A pulse density modulator as claimed in any one of the preceding claims wherein the other bistable output signal is applied to the first and second integrators via a second buffer amplifier.

9. A pulse density modulator as claimed in any one of the preceding claims, including a third buffer amplifier connected to the modulator input terminal whereby the analogue signal is compared with a d.c. reference signal prior to application to the first integrator.

10. An analogue pulse density modulator substantially as herein described with reference to and as illustrated in any one of Figs. 7 to 9 of the accompanying drawings.

11. An analogue-to-digital converter comprising an analogue pulse density modulator as claimed in any one of the preceding claims in combination with a digital filter.