GB2104332A - Digital finite impulse response filter - Google Patents

Abstract

The filter comprises weighting function circuits (20,22,24,26) which provide weighted signals to pairs of different delay points (32, 36; 42, 46; 52, (56); (62) 30, 66) of the shift register, ie an arrangement for providing symmetrical weightings about a centre point, resulting in a linear phase characteristic. The filter comprises a number of modules (60), each including a weighting function circuit (22) and a pair of adders (32,36) and delay elements (30,34) which are interconnected to give the filter a "folded" structural characteristic. <IMAGE>

Description

SPECIFICATION Digital FIR filter This invention relates to digital finite inpulse response (FIR) filters.

In a digital FIR filter, an input signal is weighted and delayed by varying amounts of time relative to the impulse point of the filter.

The weighted and delayed signal components are combined at an output which exhibits a desired response characteristic.

Digital FIR filters may be constructed using either output tapped shift registers or input tapped shift registers. An output tapped FIR filter may be constructed as shown in Chapter 9 of the text "Theory and Application of Digital Signal Processing", by Rabiner and Gold (Prentice-Hall, 1 975), wherein output tapped signals from the shift register are weighted and then combined in parallel by an adder tree arrangement to produce a filtered output signal. An input tapped FIR filter may be constructed as shown in that text and illustrated in Fig. 1. The shift register comprises a plurality of one-clock delay elements each represented by the Z-transform z' with adders 10, 12, 14, 1 6 following each z-1 delay element.An input signal x(n) is applied in parallel to the first delay element and to second inputs of the adders 10-16 by way of weighting function circuits aO, a, ... aN.3, aN2, aN, which weight the applied x(n) signal.

Weighted signal samples are thus accumulated as they are added and shifted through the register to produce a final output signal y(n) at the output of the last adder 16.

The FIR filter of Fig. 1 may be given a linear phase response characteristic by distributing the delay elements and the weighting function circuits symmetrically about the impuse response point at the center (in time) of the filter, and using symmetrically distributed weights in the weighting function circuits. For example, a five-tap FIR filter would include weighting function circuits aO, a1, a2, a3 and a4 connected to input taps of the filter. To provide a linear phase characteristic, tap weights aO, a1, a3 and a4 would be distributed symmetrically before and after the center tap a2, which corresponds to the impulse response point of the filter.The first and last weighting functions a0 and a4 are then given the same values, as are the second and fourth weighting functions a, and a3. It is desirable to implement a linear phase FIR filter using a minimal amount of circuitry, and to make the weighting function values programmable so that the characteristic of the filter may be dynamically altered.

In accordance with an aspect of the present invention, a digital FIR filter is provided in which weighting function circuits are shared, and provide weighted signals to a plurality of different delay points of the shift register. In a preferred embodiment of the invention, the FIR filter is comprised of a number of modules, each including a weighting function circuit and a plurality of adders and delay elements which are interconnected to give the filter a "folded" structural characteristic.

In accordance with a further aspect of the present invention, the weighting function circuits are made programmable, so that the filter response characteristic may be dynamically changed. The weighting function circuits in a preferred embodiment of the FIR filter each include a register for holding weighting coefficient information, two programmable shifters, and an adder for summing weighted signals provided by the shifters. By changing the coefficient information stored in the register, the response characteristic and/or the order (indicative of the number of samples accumulated in the filter) of the FIR filter may be altered.

In the drawings: Figure 1 shows an input tap-weighted FIR filter of the prior art in block diagram form; Figure 2 shows in block diagram form a modular programmable FIR filter constructed in accordance with the principles of the present invention; Figure 3 shows in block diagram form a programmable weighting function circuit for the FIR filter of Fig. 2; Figures 4 and 5 illustrate in block diagram form a more detailed representation of the shifter matrix and shift register of the programmable weighting function circuit of Fig.

3; Figure 6 is a schematic diagram of a semidynamic latch circuit suitable for use in the shift register in Fig. 5; and Figure 7 is a schematic representation of the shifter matrix of Fig. 4.

Referring to Fig. 2, an FIR filter constructed in accordance with the principles of the present invention is shown. A digital input signal x(n) is applied to weighting function circuits 20, 22, 24, and 26. The output of weighting function circuit 20 is coupled to inputs of a latch circuit 30 and an adder 66. The output of weighting function circuit 22 is coupled to inputs of adders 32 and 36. The output of latch circuit 30 is coupled to a second input of adder 32, and the output of adder 36 is coupled to the input of a latch circuit 34. The output of latch circuit 34 is coupled to a second input of adder 66. The output of adder 32 is coupled to the input of a latch circuit 40, and a second input of adder 36 is coupled to the output of a latch circuit 44.

Weighting function circuit 22, latches 30 and 34, and adders 32 and 36 are grouped in a module configuration 60. The dashed lines below module 60 indicate the possible location of additional modules, which may be included if a higher order filter is desired.

The input of latch circuit 44 and the output of latch circuit 40 are coupled to the output of an adder 46 and an input of an adder 42, respectively. The output of weighting function circuit 24 is coupled to inputs of adders 42 and 46. The output of adder 42 is coupled to the input of a latch circuit 50, and a latch circuit 54 has its output coupled to a second input of adder 46. The output of latch circuit 50 is coupled to an input of an adder 52, which has a second input coupled to the output of a weighting function circuit 26. The output of adder 52 is coupled to the input of latch circuit 54. The coefficient generators 20, 22, 24 and 26 are serially connected by portions of a coefficient control bus 77.

The shift register of the filter is comprised of the serially connected latches 30, 40, 50, 54, 44, 34, and a latch 64 which is coupled to the output of adder 66. The latches of the shift register are clocked by a shift register clock signal to transfer data through the filter.

The input signal x(n) is weighted by the weighting function circuits and applied to the adders which connect the latches of the register, as well as to the input of the first latch circuit 30. Weighting function circuits 20, 22 and 24 each develop weighted signals for two stages of the filter. Weighting function circuit 20, for instance, produces weighted signals for the first stage latch 30 and the last adder stage 66, which corresponds to weighting function values a0 and aN, of an N tap filter.

Similarly, weighting function circuit 22 develops signals weighted by functions a1 and aN2 for the first and penultimate adders 32 and 36, respectively. Weighted signals are thus accumulated through the latch and adder network, and a filtered version y(n) of the input signal x(n) is produced at the output of the last latch 64.

The FIR filter of Fig. 2 is comprised of a number of modules, one of which is indicated by dashed box 60. Each module includes a weighting function circuit (22), two adders (32, 36), and two latches or shift register stages (30, 34). The number of modules used in the filter will determine the order of the filter. The modules at the ends and the center of the filter are modified as illustrated in the embodiment of Fig. 2. Node 62, for example, can comprise an adder of a module in the illustrated embodiment which also includes weighting function circuit 20, latches 68 and 64, and adder 66 corresponding to adder 32, weighting function circuit 22, latches 30 and 34, and adder 36 in module 60 respectively.

In order for an adder at that location to function as a node, the adder must add a zero value signal (from latch 68) to the weighted signal supplied by circuit 20, thereby effectively applying the weighted signal of circuit 20 to the input of latch 30. Similarly, at the impulse response center of the filter, a module includes weighting function circuit 26, latches 50 and 54, an adder 52, and a node 56 corresponding to weighting function circuit 22, latches 30 and 34, and adders 32 and 36 in module 60 respectively. The node 56 may also comprise an adder of that module.

In that case, the center tap weighting function value a"N ,),2) is divided in half, and the input signal weighted by this value is added to the output signal of latch 50 in both adder 52 and adder 56. For instance, if the value of the center tap weighting function is +, the weight ing function a < (N 1),2 is set equal to i. The input signal weighted by i is then added to the output signal of latch 50 in adder 52, and again in adder 56, thereby providing the desired addition of weighted signals.

The FIR filter shown in Fig. 2 is a seventh order filter which includes seven input tapweighted signals and seven latch stages. The filter may be converted to an eighth order filter by inserting an additional latch stage between adders 52 and 56. In this modified configuration, four input taps precede and follow this additional latch stage which is at the center of the filter.

The modular configuration of the FIR filter of Fig. 2, in which the same weighting function circuit provides weighted input signals at two points in the filter distributed equally in time about the impulse response center of the filter, gives the filter a linear phase response characteristic. A significant savings in hardware results from this dual use of the weighting function circuits, which also gives the filter a "folded" structural characteristic about the impulse response or center module.

In accordance with a further aspect of the present invention, the response characteristic and/or the order of the FIR filter of Fig. 2 may be dynamically altered by changing the weighting function values. This is accomplished by a coefficient control bus 77, which interconnects the weighting function circuits.

The response characteristic of the filter is changed by serially shifting new coefficients into the weighting function circuits, as described below.

Referring to Fig. 3, a block diagram of one of the weighting function circuits of Fig. 2 is shown. Two dynamic shift registers 72 and 74 are serially coupled by portions of the coefficient control bus 77. An output of dynamic shift register 72 is coupled to a control input of a shifter matrix 76, and an output of dyanamic shift register 74 is coupled to a control input of a shifter matrix 78. The x(n) input signal is applied to signal inputs of the shifter matrices 76 and 78, outputs of which are coupled to two inputs of an adder 70. A weighted x(n) signal is produced at an output of adder 70.

The weighting function circuit of Fig. 3 weights the applied x(n) signal by a function which is a sum or difference of multiples on inverse powers of two, using a shift-and-addor-subtract technique. For example, assume that the weighting function circuit is to produce a signal equal to (3/16)x(n). Coefficient values representative of 1 /8 and 1/16 are first shifted into the dynamic shift registers 72 and 74, respectively. The 1/8 coefficient is applied to the shifter matrix 76 which shifts the x(n) input signal to the right by three bit positions, producing a signal equal to (1 /8)x(n).The 1/16 coefficient is applied to the shifter matrix 78, which shifts the x(n) input signal to the right by four bit positions, thereby producing a signal equal to (1/16)x(n). The adder 70 then adds the value of(1 /8)x(n) to (1/16)x(n), producing the desired weighted signal of (3/16)x(n).

The shifter matrices and dynamic shift registers of Fig. 3 are shown in further detail in Figs. 4 and 5 respectively. Referring to shifter matrix illustrated in Fig. 4, the applied x(n) input signal of, for instance, eight bits is applied to an invert section 80 of the shifter matrix. The invert section 80 will invert the x(n) signal or pass it uninverted in accordance with the values of complementary control signals INVERT and INVERT. The signal produced by the invert section is then applied to a one-half weighting section 82, where it may be weighted by one-half or passed through unweighted, in accordance with the values of complementary control signals C1 and C,. A nine-bit signal is produced by the one-half weighting section and applied to a one-quarter weighting section 84.In this section, the signal may be further weighted by one-quarter or passed through unweighted with the value of complementary control signals C2 and C2.

An eleven-bit signal produced by weighting section 84 is applied to a one-sixteenth weighting section 86, which may weight the signal by a further factor of one-sixteenth or pass it through unweighted in accordance with the setting of complementary control signals C4 and C4. The weighted signal is then applied to a zeroer and buffer section 88, which receives a control signal from an AND gate 87. When the C1, C2 and C4 control signals applied to AND gate 87 are all true (i.e., all logical one) section 88 will produce a zero value output signal. Otherwise, the weighted x(n) signal is only buffered by section 88 and applied to adder 70 of Fig. 3.

When the weighting function values are programmable as shown in Figs. 3 and 4, the order of the FIR filter may be altered by zeroing the signals of the weighting function circuits starting with those coupled to the first and last shift register stages of the filter. For instance, the embodiment of Fig. 2 shows a seventh order FIR filter, with tap weights aO, a1, a((N.1)/2)1 a((N1)2), a,,,,,,,,,,' aN2 and aN1, where N = 7. The weighting function values of weighting function circuit 20 of Fig. 2 may be set to zero (e.g., a0 = 0 and a,, = O) by using the structure of Figs. 3 and 4, in which the C1, C2, and C4 coefficients are set equal to .one. The weighting function circuit 20 will then apply zero value signals to latch 30 and adder 66.This will change the FIR filter to a fifth order filter with tap weights of a1, a((N 1)/2).

1 a((N1)/2) a((N-1)/2)+1' anda((N1)/2)+1 and aN2. This fifth order filter is followed by the two clock cycle delays of latches 34 and 64, which receive the filtered output signal produced at the output of the effective final adder 36 of the fifth order filter.

The shifter matrix of Fig. 4 may be con trolled to weight the x(n) signal by factors of one, 1/2, 1/4, 1/8, 1/16, 1/32or1/64, in accordance with the values of the control signals. The weighted signal may, as dis cussed above, be inverted (one's comple mented) or passed uninverted in accordance with the values of the INVERT and INVERT control signals. For example, if two weighted signals are to be subtracted, then the signal to be subtracted from the other must first be two's complemented. The two's-complement ing operation produces a signal which has a value which is the negative of the value of the input signal. To two's complement a binary signal, the input signal bits are first inverted, then a binary '1' added to the result.If the weighted signals are to be two's comple mented, the INVERT control signal may also be applied to the least significant (carry-in) bit position of the adder 70 to complete the two's complementing process by adding 1 to the sum of the augend and addend.

A shift register suitable for use as the dynamic shift register 72 or 74 of Fig. 3 is shown in Fig. 5. D-type flip-flips 90, 92, 94 and 96 are coupled in series with the coeffici ent control bus 77 and are clocked by a clock signal. When it is desired to change the value of the weighting function of the shifter matrix of Fig. 4, the clock signal is activated to shift new control signals into the register from bus 77. The control signal data stream, consisting of serial coefficient data bits, is clocked through the register until the bits representing the desired coefficients are stored in the pro per stages of the register. Coefficient values for succeeding registers may also pass through the register and into following, simi larly constructed registers.When the register is properly loaded, the INVERT, C1, C2 and C4 control signals are produced at the Q outputs of the flip-flops, and complementary values are produced at the Q outputs. The shift matrix of Fig. 4 will then weight and/or invert the x(n) input signal in accordance with these coefficient values.

Referring to Fig. 6, a semidynamic latch stage suitable for use in the shift register of Figs. 3 and 5 is shown in schematic diagram form. Four of the latch stages of Fig. 6 may be cascaded to produce a four-stage shift register similar in function to that of Fig. 5.

In Fig. 6, the coefficient control signal is applied to a transmission gate 200, including two source-to-drain coupled complementary p and n type MOS transistors 202 and 204.

The output of the transmission gate 200 is coupled to the input of an inverter 208, the output of which is coupled to a second transmission gate 210, including source-to drain coupled complementary MOS transistors 21 2 and 21 4. The output of transmission gate 210 is coupled to the input of an inverter 218, the output of which is coupled to the input of a third transmission gate 220, includ ing source-to-drain coupled complementary MOS transistors 222 and 224. The output of transmission gate 220 is coupled to the input of inverter 208. Complementary output sig nals OUT AND OUT, (corresponding to the G and Q outputs of flip-flops 90-96 in Fig. 5) are produced at the outputs of inverters 218 and 208, respectively.

The semidynamic latch stage of Fig. 6 is clocked by complementary clock signals ss and +, while gate 220 is open because the WRITE signal is high and the WRITE signal is low.

When the + clock signal is low and the 9 clock signal is high, the coefficient control signal is conducted through transmission gate 200 and stored across the input capacitance 206 of inverter 208. The ss and ss clock signal then changes state, which opens transmission gate 200, and renders transmission gate 2 0 conductive. The signal level at the input ofinverter 208 is inverted, transmitted through gate 210, and held at the input capacitance 216 of inverter 218. Once the latch has been loaded with the desired values, the WRITE signal goes low and the WRITE signal goes high, which renders transmission gate 220 conductive.The signal level at the input of inverter 21 8 is inverted by that inverter and transmitted through gate 220, thereby reinforcing the signal level stored at the input of inverter 208. The output signal of inverter 208 continues to be conducted by gate 210 to reinforce the signal level held at the input of inverter 216. Thus, the stored signal levels are maintained at the inputs of the two inverters through positive feedback, ana' compie- mentary output signals OUT and OUT are presented to the shifter matrix by the latch.

A more detailed embodiment of the shifter matrices of Figs. 3 and 4, suitable for fabrication in MOS integrated circuit form, is shown in Fig. 7 In the Figure, metallized paths are represented by heavy solid lines, diffusion layer paths are represented by thin solid lines, and polysilicon paths are represented by thin broken lines. Intersections of paths of the same type connote connections at those points. Signals are routed through the matrix by transmission gates formed by the intersections of the diffusion layer paths and the polysilicon paths under control of the signal levels on the polysilicon paths. When the signal on the polysilicon path is high, signals may pass through that point in the diffusion layer path; when the signal on the polysilicon path is low, signals are inhibited from passing through that point in the diffusion layer path.

Bits B7-Bo of an eight-bit x(n) input signal are applied to a first column 100 of eight inverters in the invert section of the shifter matrix. Each of these inverters is bypassed by a controlled signal path which is part metallized conductor and part diffusion layer path. The outputs of the first eight inverters are coupled to inputs of a second column 102 of eight inverters. Output signals are produced by the second column of inverters on seven diffusion layer signal paths 110-116, and on path 117, which is part metallized conductor and part diffusion path.

The eight signal paths 110-117 first pass through the one-half weighting section 82, including a polysilicon path 1 30 which carries control signal C1 on a polysilicon and metallized signal path 1 32 which carries control signal C,. The eight signal paths 11 0-11 7 and lower order bit signal path 1 20 next pass through the one-quarter weighting section 84, including a polysilicon path 140 which carries control signal C2 and a polysilicon and metallized path 142 which carries control signal C2.The eight signal paths 110-117 and lower order bit signal paths 1 20-122 then pass through the one-sixteenth weighting section 86, including a polysilicon path 1 50 which carries control signal C4 and a polysilicon and metallized path 1 52 which carries control signal C4. Finally, the eight signal paths 110-117 and lower order bit signal paths 120-122 pass through a zeroer and buffer circuit 88. A zeroing circuit 160, includes polysilicon path 166, a diffusion layer and metallized signal path 1 62 and a metallized ground bus 1 64. The eleven signal paths then are coupled to buffer circuit inverters of columns 1 70 and 172, which produce eleven output bits WB7-WB3.

The zeroing circuit 1 60 is controlled by signals from an AND gate 87, which receives input signals from the C1, C2, and C4 paths 132, 142, and 1 52. The output of AND gate 87 is coupled to metallized and polysilicon path 162, and to the input of an inverter 1 65. The output of inverter 1 65 is coupled to polysilicon path 166.

If the x(n) input signal is not to be inverted, the INVERT signal is low and the INVERT signal is high. The low INVERT signal opens the transmission gates (as described above) in the signals paths which bypass the first inverters 100, and the high INVERT signal closes the transmission gates at the inputs of the first inverters 1 00. The eight bits of the input signal are then doubly inverted by two inverters in each bit path, and the signals on lines 110-11 7 are not inverted with respect to the input signals.

The INVERT signal is also applied to the inputs of three inverters 104, 106 and 108, the outputs of which are coupled to the inputs of lower order bit signal paths 120, 121 and 122, respectively. When the input signal is not to be inverted, the high INVERT signal causes inverters 104, 106 and 108 to apply zero value signal levels at the inputs of the lower order bit signal paths 120, 121 and 122.

When the invert section 80 is to invert the input signal, the INVERT signal is low and the INVERT signal is high. The INVERT signal will then open the transmission gates at the inputs to the first column 100 of inverters, and the IN.VERT signal will close the paths which bypass the first inverters. The bits of the input signal will then be inverted only once by inverters 102. ~~~~~~~ At the same time, the low INVERT signal at the inputs of inverters 104, 106, and 108 produces logical one level signals at the inputs of fractional bit paths 120, 121, and 1 22. This provides a fully complemented eleven bit signal at the output of the shift matrix.

When the input signal is to be weighted by one-half by weighting section 82, the C1 signal is high and the C1 signal is low. The high C, signal on control path 1 32 then closes the diagonal paths connecting adjacent signal paths. The low C, signal on control path 1 30 also opens the signal paths 110-11 6 and 1 20 at points following the take-off points for the diagonal paths and prior to the points at which the signals are applied to respectively lower paths.Thus, signals on conductor 11 7 will be conducted to path 116, signals on path 11 6 will be conducted to path 115, and so forth. (Signals on path 11 7 will be passed through unaffected since path 11 7 is a metallized path.) If the weighting section 82 is to pass the input signal without shifting, the C1 signal is low, which opens the diagonal paths, and the high C1 signal closes paths 110-116 and 1 20 through the section.

Sections 84 and 86 function in a similar manner as section 82, except that the input signal is shifted by two and four bit positions, respectively, by these sections. Control paths 140 and 1 50 control transmission gates in the direct paths 110-116 and 1 20-122, and control paths 1 42 and 1 52 control transmission gates in the diagonal signal paths for shifting. All of the weighting sections 82, 84 and 86 also replicate the most significant bit B7 as the signal is shifted down, for subsequent two's complement adding. For instance, when the input signal is weighted by onesixteenth by section 86, the B7 signal on path 117 is also applied to paths 116, 115, and 114, as well as path 113 by way of diffusion path 1 54.

When control signals C1, C2 and C4 are all high, the shifter signal will be zeroed. The Aiding of these three signals by AND gate 87 places a high signal on conductor 162.

this high signal then connects signal paths 110-1 22 to the grounded bus 1 64. At the same time, inverter 165 and polysilicon path 1 66 open all of the signal paths (including 11 7 which is a diffusion path) prior to the points at which they are grounded. A signal of all zeroes is then produced at the output of the buffer inverters 1 70 and 1 72.

By way of example, assume that the x(n) input signal is to be weighted by a factor of 1/64. This is accomplished by causing weighting sections 84 and 86 to provide a shift of six bit positions. Bit B5 will be placed on signal path 11 5 by inverters in columns 100 and 102, and will pass directly through the one-half weighting section 82, staying on signal path 11 5. Bit B5 will then be conducted to signal path 11 3 by weighting section 84, then to signal path 1 20 by weighting section 86. The original B5 bit of the input signal will then pass through to output We~,. a shift of six places from its original position. All of the bits of the input signal will be shifted in this manner, thereby weighting the x(n) input signal by a factor of 1/64.

The shifter matrices and weighting function circuits of the FIR filter of the present invention are described more fully in United States patent application number 363,827, entitled "Digital Filter Circuits", by Lauren A. Christopher, corresponding to copending British Patent Application 8222991 (RCA 77399A), entitled Controllable Shift Matrix Weighting Function Circuit And Digital Circuits, Expecially Filters Using Such a Matrix.

Claims (13)

1. A digital input tap weighted finite impulse response filter, including a plurality of serially coupled delay elements and adders in alternating sequence, said plurality having a central point; a plurality of input taps coupled to a first one of said delay elements and to inputs of said adders; and a plurality of weighting function circuits having inputs coupled to receive a digital input signal and respective outputs wherein said respective outputs are coupled to input taps located a like number of taps before and after said centrally located point.

2. The digital filter of Claim 1 wherein: said pluralities of delay elements, adders, and weighting function circuits are arranged in a plurality of modules, each module comprising: an input signal weighting function circuit having an input for receiving said digital input signal and an output at which weighted signals are produced; first and second delay elements, each having a signal input, and a signal output; a first adder having a first input coupled to said output of said weighting function circuit, a second input coupled to said signal output of said first delay element, and an output; and a second adder having a first input coupled to said output of said weighting function circuit, a second input, and an output coupled to said signal input of said second delay element.

3. The digital filter of Claim 2 wherein: said plurality of modules includes an end module having an output at which a filtered signal is produced; said filter further comprising means for coupling each input of said first delay element and each output of said second delay element of said modules to the output of a first adder and the first input of a second adder of an adjoining module, respectively.

4. The arrangement of Claim 3, wherein said end module comprises: a weighting function circuit having an input for receiving a digital signal and an output at which a weighted digital signal is produced; an adder having a first input coupled to the output of said weighting function circuit, a second input coupled to the output of a second delay element of an adjoining module, and an output; and a delay element having an input coupled to said output of said adder of said end module and an output at which said filtered signal is produced.

5. The digital filter of Claim 1 wherein: said plurality of delay elements comprises N delay elements having inputs and outputs, and respectively numbered N-i, where i is an integer number over the range of N-l to zero, with the output of delay element number N being coupled to said output of said filter; said plurality of adders comprises N-l adders respectively numbered N-j, where j is an integer number over the range of Ni-2 to zero, each of said adders having a first input, a second input coupled to the output of delay element number N-j-l, and an output coupled to the input of delay element number N-j;; said plurality of input taps comprises N input taps respectively numbered N-i, where input tap number 1 is coupled to the input of delay element number 1, and respective input taps numbered 2 through N are coupled to respective first inputs of adders numbered 2 through N; and said plurality of weighting function circuits comprises (N/2) weighting function circuits respectively numbered (N/2)-k, where k is an integer number over the range of (N/2)-1 to zero, with inputs of said weighting function circuits being coupled to said input of said filter, and respective outputs of said weighting function circuits being coupled to respective taps of the same number, and to respective taps numbered N-(N/2) + k + 1, wherein the fractional portion of the N/2 terms, if any, is disregarded.

6. The digital filter of Claim 5, wherein said number N is an odd number, said plurality of taps includes a center tap number (N + 1)/2, and further including an additional weighting function circuit having an input coupled to said input of said filter and an output coupled to said center tap.

7. The digital filter of Claim 1 wherein said plurality of delay elements each has an input and an output; said plurality of adders comprises one fewer in number than said delay elements, one input of each of said adders being coupled to an output of a preceding delay element and the output of each adder being coupled to the input of a succeeding delay element; said central point is located a given number of delay elements following the input of the first delay element of said sequence and preceding the output of the last delay element of said sequence; said plurality of input taps are coupled to second inputs of said adders and to said input of said first delay element; and said plurality of weighting function circuits each having an input coupled to receive a digital signal which is to be filtered, for producing weighted digital signals at respective outputs, each of said outputs of said weighting function circuits being coupled to two of said input taps which are located a like number of taps away from said central point of said sequence.

8. The digital filter of Claim 7, wherein said central point is located a given number of input taps following the input tap coupled to said input of said first delay element and preceding the input tap coupled to said final adder of said sequence, wherein one of said plurality of adders is located at said central point; and further comprising an additional weighting function circuit having an input coupled to receive said digital signal which is to be filtered and an output coupled to the second input of said adder which is located at said central point.

9. The digital filter of Claim 1 further comprising an input for receiving said digital input signal to be processed; and an output at which a processed signal is produced; wherein said plurality of adders is equal in number to said plurality of delay elements; each of said plurality of adders having first and second inputs and an output; the outputs of said delay elements coupled to the first inputs of the respective succeeding adders and the outputs of said adders coupled to the inputs of the respective succeeding delay elements, the output of the last adder in said alternating sequence being coupled to said output of said filter; said central point comprises an adder; the number of delay elements between the input of the first delay and the first input of said central adder being equal to the number of delay elements between the output of said central adder and the output of said last adder; said plurality of taps is equal in number to at least one more then said number of said delay elements, one of said taps being coupled to the input of the first delay element, the remaining ones of said taps being coupled to respective ones of the second inputs of said adders; and said plurality of weighting function circuits is equal in number to one more than one half the number of said delay elements, each of said weighting function circuits having an input and an output, the inputs of all of said weighting elements being coupled to said input of said filter, the output of a first one of said weighting elements being coupled to the second input of said central adder, the outputs of each of the other weighting elements being coupled to at least two taps, each of said two taps being the same number of delay elements away from said central adder.

10. The digital filter of Claim 1 wherein each of said plurality of weighting function circuits includes first and second shifter matrices, each having an input coupled to receive said digital signal and respective outputs at which first and second weighted digital signals are produced, and an adder having a first input coupled to the output of said first shifter matrix, a second input coupled to the output of said second shifter matrix, and an output at which a weighted digital signal is produced.

11. The digital filter of Claim 1 wherein each of said plurality of weighting function circuits comprises: a first shifter matrix having an input coupled to receive said digital signal, an output at which a first controllably shifted digital signal is produced, and a shift control input; a second shifter matrix having an input coupled to the input of said first shifter matrix, an output at which a second controllably shifted digital signal is produced, and a shift control input; and an adder having inputs coupled to the outputs of said shifter matrices and an output at which a weighted digital signal is produced; and a register having an input coupled to receive a shifter control signal and an plurality of outputs coupled to said control inputs of said shifter matrices.

12. The filter of Claim 11, wherein said shifter matrices include a first shifter section for controllably shifting said digital signal by one bit position; a second shifter section coupled in series with said first section for controllably shifting said digital signal by two bit positions; and a third shifter section coupled in series with said second section for controllably shifting said digital signal by four bit positions.

13. The filter of Claim 12, further including an inverting section, coupled in series with said first section for controllably complementing said digital signal.

1 4. A digital filter substantially as hereinbefore described with reference to Figs. 2-7 of the drawings.