GB2102644A - Circuit arrangement for producing analogue television signals with amplitude adjustment - Google Patents

Abstract

Circuit arrangement for producing analogue television signals from digital colour television signals, in which the control quantities for saturation, contrast or such like are applied to digital-to-analogue converters which operate to a certain extent as multipliers, in that the analogue output signals depend on an adjustable reference value.

Description

SPECIFICATION Circuit arrangement for producing analogue television signals with amplitude adjustment The invention relates to a circuit arrangement for producing analogue television signals, particularly for driving a colour picture display tube, from digital colour television signals incorporating at least one-digital-to-analogue converter and with amplitude adjustment, for example to change the colour saturation and/ or the contrast.

With such a circuit arrangement it is possible to effect the amplitude adjustment by using at least one controllable amplifier, after the analogue signal has been recovered. However, this means additional cost and design effort and due to deviations in the characteristics when several analogue amplifiers are used, it is often not possible to accomplish the accurately uniform control which is required to prevent an incorrect picture representation.

It is an object of the invention to provide a simpler and more precise amplitude adjustment of the received analogue signal.

According to the invention this object is accomplished in that the digital signals are applied to a digital-to-analogue converter whose analogue output signal also depends on a reference value and that this reference value is adjustable.

The output signal must depend on the reference value in accordance with a defined, preferably linear function. When a digital-toanalog converter which is known per se is used in which, depending on the positions of the digital signal, different currents and voltages, respectively are added together, it may happen that the tolerances of this signal add up in a disadvantageous manner. If then, for example, a signal is processed which increases like a ramp in much the same way as a sawtooth, it is possible that between a value formed from a sum of small values, and the next value, which is represented by a greater value, a negative difference occurs, because the positive tolerance deviations of the smaller values were larger that the tolerance deviation of the next higher value: A flyback then occurs in the sawtooth, a uniform variation is not ensured.

Preferably, a digital-to-analog converter is therefore used in which the set of values of the analogue signal is in the form of taps of a single resistive voltage divider which is connected to a reference voltage and in which each tap has an associated switch which at the occurrence of a predetermined digital signal value is operated and through which the associated analogue value tap of the voltage divider is connected to the output.

With such a converter each analogue value is unambiguously defined, it is not composed of other values, so that consecutive values can only be distinguished from the resistance between the relevant taps and its tolerance.

Even so it might happen that in the circuit, when switching from one tap to the next tap the relevant resistor is accidentally by-passed, only a voltage means value is produced which in essence conforms with the sequence of adjacent analogue values.

Preferably, the switching criterion which depends on a predetermined digital value is applied via a clock pulse stage to the associated switch at the analog value voltage divider. When switching from one to the next digital value it is often possible that in the transition region greatly deviating, peakshaped values occur which would be a misrepresentation of the required results. The above-mentioned clock pulse stage does not convey the relevant digital signal until the transistion region has been passed through and the signal has assumed its required value.

In accordance with a further embodiment the value taken from the voltage divider can be applied to an output signal store, preferably via a clock pulse stage. Then the relevant analogue value is stored during one whole clock pulse interval, the next disturbance-free analogue value then being conveyed to the output.

The control of a digital-to-analog converter in which the analogue signals are in the form of taps of a resistor-voltage divided is efficiently effected in that the n-bit-digital and the inverted digital signals are applied to a number of 2n NOR-gates which are controlled such that for each digital value only one NOR-gate produces an output value which operates a switch which connects the associated tap of a resistor voltage divider to the output.

The invention will now be further described by way of example with reference to the accompanying drawing, in which Figures 1 and 2 show two embodiments of the invention, while Figure 3 shows a digital-to-analog converter which is suitable for use in a circuit arrangement in accordance with the invention.

In Fig. 1, the colour difference signals (B-Y) and (R-Y), which are applied as digital signals u and v, respectively, and the likewise digitized luminance signal y are taken as the starting point. These signals are applied to the digital-to-analog converter 1, 2 and 3, respectively. The output signals of these converters depend on the supply voltage or reference voltage applied to the terminals 11, 12, 21, 22 and 31, 32 respectively, so they operate to a certain extent as multipliers. In a control portion 8, whose outputs are connected to the terminals 11, 12, 21, 22 and 31, 32 of the converters 1, 2 and 3, the required voltages are produced which are controlled on the one hand by a saturation-adjusting signal S and on the other hand by a contrast-adjusting signal K.This may be done in a manner such that, to adjust the saturation the voltages at the terminals 11, 12 and 21, 22 are changed to the required extent, while the voltages at the terminals 31, 32 remain constant, so that the luminance signal is not altered. In contrast therewith, to adjust the contrast, all the signals which are applied to the multiplier inputs 11, 12, 21,22, 31 and 32 are changed to the required extent.

The colour difference signals received from the converters 1 and 2 are applied in a manner which is known per se via an inverter stage 61, which multiplies simultaneously by a factor of 0.1 9, and via an inverter stage 62 which simultaneously multiplies by a factor of 0.287, to an adder stage 63 as a result of which the colour difference signal (G-Y) is obtained.

The luminance signal obtained from the output of the converter 3 is conveyed through an adder stage 64, in which a value used to change the brightness setting can be added.

The luminance signal thus corrected is combined in the adder stages 65, 66 and 67 with the colour difference signals. so that at the output the analogue colour signals B, G, and R received as the blue signal, green signal and red signal for the drive of a picture display device.

Fig. 2 shows a circuit arrangement which to a very large extent corresponds to Fig. 1 but in which the green colour difference signal (G-Y) is also obtained by means of multiplying digital-to-analog converters. To that end the input signal u is applied to a converter 4 and the digital colour signal vto a converter 5. The inverting outputs of these converters 4 and 5 are combined in an adder stage 71; further processing is effected as described for Fig. 1.

The converters 4 and 5 have controlling inputs 41, 42 and 51, 52 respectively which are connected to the control stage 72; this control stage replaces the control stage 8 in Fig. 1. In an integrated circuit it may be simpler to use the stages 4 and 5 as shown in Fig. 2 instead of the multiplying inverter stages 61 and 62 of Fig. 1. More specifically, an additional influencing of the recovery of the green-colour difference signal from the two other colour difference signals is now possible via the inputs 41, 42 and 51, 52 so that, possibly by influencing the further voltages at the terminals 11, 12, 21 and 22 by a signal F, also an adjustment of the colour hue is possible.

Fig. 3 shows an 8-bit digital-to-analogue converter such as it is preferably used in a circuit arrangement in accordance with the invention, for example instead of converter 1 in Fig. 1. The digital colour difference signal u is applied via eight parallel bit-lines B0, B1, B2, 83, B4, B5, B6, and B7 as well as eight bit-lines BO, B1, B2, B3, B4, B5, B6, B7.

These lines are connected to 256 NOR-gates G,, Gr, G2 G254 and G255 in such a way that for each digital value only one of these gates produces an output value "1". Via field effect transistor paths Ho to H255 which operate as clock-controlled switches, the outputs of these gates are connected to the control electrodes of each one of switching-field effect transistors Mo to M255, whose output electrodes are all connected to the output electrode 81. The supply voltages of the gates and transistors may be 5 V: the field effect transistors are preferably manufactured in N MOS or P-MOS technology, the transistors, the resistors W, to W255 preferably consist of polysilicon.

The number of analogue values are produced by a voltage divider which is formed by the series arrangement of the resistors W, to W255. Each section of this voltage divider is connected to an input electrode of the associated switching transistors Mo to M255. Depending on the applied digital signal only one of these switches becomes conducting, and the corresponding analogue value occurs at the output.

The reference signal terminals 11 and 1 2 are connected to voltages which may be chosen between - 0.5 and + 3.5 V, whereby the individual amplitude stages of the analogue output signal are fixed. One of the terminals 11 and 1 2 may be connected to ground, so that only amplitude values in one sign direction occur. However, also voltages with the opposite sign may occur at the terminals 11 and 12, so that the analogue values obtained may be located in two planes.

If one converter of this type is provided for two coordinate directions, a multiplication in four quadrants ia alternatively possible.

In order to keep any interference occurring during the switching-over from one digital value to the other far removed from the output signal the switching paths Ho to H255 are provided which are operated by a clock signal from the terminal 82 in the interference-free interval between the change-over action.

In known digital-to-analog converter incorporating resistance networks a number of switches corresponding to the number of the parallel bit lines are present, several of which are preferably operated simultaneously. Each analogue value obtained is consequently a sum of one or more individual values. The individual values have different tolerances, so that it is not ensured that, for example on the display of an uniformity increasing ramp voltage, the individual steps have accurately equal step heights. In contrast therewith, with the converter shown in Fig. 3 each analogue value is taken from a defined voltage-divider tap, so that tolerance fluctuations can only cause minimal deviations from the predetermined value, for example on the display of a ramp voltage.

Different values may be chosen for the resistors W, to W255, so that there is a nonlinear relationship between the digital input signals and the output signals at the terminal 81. Thus, particularly a television signal gamma correction corresponding to an exponent 0.5 can be obtained in a simple and reliable manner.

Claims (8)

1. A circuit arrangement for producing analogue television signals from digital colour television signals, the arrangement incorporating at least one digital-to-analogue converter and with amplitude adjustment, characterized in that the digital signals are applied to a digital-to-analogue converter whose analogue output signals also depend on a reference value and that this reference value is adjustable.

2. A circuit arrangement as claimed in Claim 1, characterized in that the output signal depends on the erference value in accordance with a defined, preferably linear, function.

3. A digital-to-analogue converter, particu lariy for a circuit arrangement as claimed in Claim 1 or 2, characterized in that the set of values of the analogue signal are in the form of taps of a single resistive voltage-divider which is connected to a reference voltage and that associated with each tap there is a switch which is operated and connected to the output via the associated analogue value tap of the voltage divider at the occurrence of a predetermined digital signal value.

4. A converter as claimed in Claim 3, characterized in that the switching criterion which depends on a predetermined digital value is applied via a clock pulse state to the associated switch at the analogue value voltage divider.

5. A converter as claimed in Claim 4, characterized in that the tapped-off value is applied to an output signal store, preferably via a clock pulse stage.

6. A converter as claimed in any of the Claims 3, 4 or 5, characterized in that the nbit digital and the inverted u-bit digital signals are applied to a number of 2" NOR-gates which are controlled such that for each digital value only one NOR-gate supplies an output value which operates a switch which connects the associated tap of a resist or voltage divider to the output.

7. A circuit arrangement substantially as hereinbefore described with reference to Fig.

1 or Fig. 2 of the accompanying drawings.

8. A digital-to-analogue converter for a circuit arrangement as claimed in Claim 7, substantially as hereinbefore described with reference to Fig. 3 of the accompanying drawings.