GB2100538A - AM or FM demodulator - Google Patents

Abstract

A sampling demodulator is adaptable as both a frequency demodulator (where the bandwidth of modulating frequencies is small compared to the fundamental carrier frequency) and as an amplitude demodulator. In the amplitude demodulation mode the demodulator is able to produce an output with no residual undulating ripple even when the modulation and carrier frequencies are relatively closely spaced. The amplitude demodulation is achieved by sample-and-hold devices (19,20) which track and hold the maximum value of alternate odd and even- numbered positive and negative-going half cycles of the carrier. The hold values are output to a combining device (25, 26, 28) which produces a step function output, each step being one carrier cycle long. The sample-and-hold devices are controlled by timing pulses (17, 18) which are produced by timing circuits (7, 8, 10, 11, 12, 15, 16) from the zero-crossing points of the carrier. In the frequency demodulation mode the sample-and-hold devices (19,20) are arranged to track and hold the value of the carrier every n/fo seconds after a zero-crossing of the incoming signal (n = an integer and fo is the fundamental carrier frequency). <IMAGE>

Description

SPECIFICATION Signal processing The invention concerns inprovements in or relating to signal processing and particularly, but not exclusively, to electrical circuits for isolating an amplitude modulating signal from a carrier signal where the modulation and carrier frequencies are relatively closely spaced.

A conventional prior art method for separating an amplitude modulating signal from a carrier signal involves passing the rectified composite signal through a low pass filter to block the carrier.

However, for a value of modulation frequency close to that of the carrier frequency, this places exacting requirements on the filter design in order to avoid inclusion of a residual carrier ripple on the extracted modulation signal without distortion of the high frequency components. Additionally, there may be a departure from amplitude linearity at low signal levels where diode rectifiers are used.

A second prior art method for extracting an amplitude modulating signal involves applying the composite signal to an analogue-to-digital (a/d) converter of which the sampling is arranged to occur at a rate and phase so as to coincide with the positive-going peaks of the carrier. This method has the advantage of the linearity of a/d conversion even at low amplitudes. Difficulties associated with the use of diodes and residual carrier ripple as in the first prior art method are therefore avoided. However, the phase of the carrier on arrival at the signal processor may not always be known. Relatively complex circuitry to allow locking onto the arrival phase is therefore necessary.

Purposes of the invention include provision of a relatively simple demodulation circuit which extracts an amplitude modulating signal from a carrier even when the two frequencies are relatively close and in which residual undulating ripple is eliminated and an improved linearity of response is obtained and which may also be adapted for use as a frequency demodulator when the spread of modulation frequencies is relatively small.

According to the present invention there is provided a demodulator for extracting a modulation signal from a modulted carrier signal including latching means for tracking and holding the value of predetermined portions of the carrier and inputting the hold values to a combining means which combines the hold values to produce a step function output representing the modulation signal.

The demodulator may be for demodulation of an amplitude modulated carrier and may include first latching means for operating in an amplitude demodulation mode in which it tracks the value of and holds the extreme value attained by each 2mth half cycle of the carrier (where m is a predetermined integer) and first combining means for accepting the hold values and outputting a step function signal constituted by successive hold values.

The demodulator may alternatively be for demodulation of a frequency modulated carrier and may include primary latching means for operating in a frequency demodulation mode in which it tracks and holds the value achieved by the signal every n/fO seconds after a zero-crossing point of the signal (where n is a predetermined integer and f, is the frequency of the carrier) and primary combining means for accepting the hold values and outputting a step function signal constituted by successive hold values. The frequency demodulator may be additionally operable in an amplitude demodulation mode so as to additionally provide an amplitude demodulation capability.

The amplitude demodulator may be such that the first latching means begins tracking of the carrier signal at a zero-crossing point and holds the value of the signal achieved 41 carrier cycle later.

The latching means may be provided by at least one sample-and-hold device and is preferably provided by two sample and hold devices which operate to input hold values to the combining means alternately.

Preferably the sample-and-hold devices are controlled by timing pulses derived from the zerocrossing points of the carrier signal.

The amplitude demodulator may include second latching and combining means for operating 2m' + 1 half cycles out of phase with the first latching and combining means (where m' is an integer) in order to produce an additional step function output.

The frequency demodulator may also include secondary latching and combining means for operating n/2fO seconds out of phase with the primary latching and combining means in order to produce an additional step function output representing the modulation signal.

The invention will now be described by way of example only with reference to the accompanying diagrams of which: Figure 1 is a schematic circuit diagram of a demodulator according to the invention, Figure 2 is a timing diagram illustrating relative times of signals at a number of points in the circuit of Figure 1, Figure 3 is a timing diagram illustrating the operation of a first modified form of the demoulator of Figure 1, Figure 4 illustrates graphically an alternative mode of operation of a second modified form of the demodulator of Figure 1.

The demodulator of Figure 1 is used for analysing an audio signal included as a subcarrier of constant amplitude and frequency (2 kHz) on a radio frequency carrier (not shown in the diagram). Between transmission from a transmitter (not shown) and reception at a receiver (also not shown), the composite signal suffers periodic low frequency fading so that, on reception, the subcarrier is amplitude modulated.

In Figure 1 an input signal (see Figures 2(a)) consisting of the modulated subcarrier is input at port 1. After input, the signal divides between lines 2 and 3. The signals passing into line 3 are used to generate timing pulses derived from the zerocrossings of thesubcarrier signal, and the signals passing into line 2 are used, in conjunction with the timing pulses, to generate a signal representing the modulation envelope.

The signals on line 3 pass through an amplifier, 4, to a line, 5. The amplifier, 4, strips off most of the modulation envelope and leaves signals on line 5 with large amplitudes and thus a high rate of change which produces well-defined zero crossings. The signals on line 5 then pass to a comparator,6, the reference value, A, of which is set nominally to zero.

(In practice A is offset by a small voltage to preclude switching on noise.) The comparator, 6, therefore detects positive-going zero crossings of the subcarrier signal and produces an output on line 7. The output on line 7 then passes to a conditioning circuit, 8, which conditions the signals on line 7 to produce clocking waveforms, 9, which are compatible with the remainder of the circuit.

A line then takes clocking signals, 9, (see Figure 2(b)) from circuit 8 to a flip4lop, 10. The flip-flop then produces Q and#Ooutputs, 23 and 24, with com- plementary positive-going edges as in Figures 2(c) and 2(d). The Q and#Qoutputs, 23 and 24, are then introduced to AND gates 11 and 12 respectively, both of which additionally receive signals 9. The AND gates, 11 and 12, produce outputs 13 and 14 respectively which are used to trigger monostables 15 and 16 respectively. The monostables produce outputs 17 and 18 respectively (see Figures 2(f) and 2(e)). These consist of positive pulses at the commencement of alternate half cycles of the modulation signal. The odd-numbered half cycles are indicated by one monostable and the even-mumbered half cycles by the other monostable.The pulse widths applied by the monostables are determined by RC circuis (not shown in Figure 1) associated with the monostables and are set at a quarter of the time period of the subcarrier signal. A pulse is therefore arranged to begin at a zero-crossing of the subcarrier signal and ends at the following subcarrier peak.

The modulated subcarrier signals on line 2 then pass to two sample-and-hold devices 19 and 20.

Device 19 is gated by pulses, 17, whilst device 20 is gated by pulses 18 which determine the sample-andhold times. Devices 19 and 20 thus produce outputs 21 and 22 as illustrated in Figures 2(9) and 2(h).

Signals 21 and 22 therefore rise to and hold the peak positive voltages of alternate cycles of the subcarrier signal. The steady peak levels then pass through bilateral analogue gates 25 and 26 which are pulsed by signals 23 and 24 respectively from flip-flop 10 and are thus multiplexed to anoutput line, 27, after passing through a buffer amplifier, 28.

Resistors R1 and R2 and diodes D1 and D2 provide negative voltage suppression to protect the bilateral analogue gates in case of error in setting the monostable pulse widths which cause negative sampling voltages.

The output on line 27 (see Figure 2(i)) therefore consists of a staircase waveform which follows the modulation envelope and with absence of undulating ripple from the subcarrier signal. This may be advantageous for further processing of the modulation signal. The signal may require analysis, for example, to detect any maxima and minima present.

If the signal contains undulating ripple from the subcarrier signal, the maxima and minima will therefore be wrongly positioned. By production of a staircase modulation signal, such a problem may be avoided.

Using the above technique, a modulation signal can therefore be separated from a carrier signal where the two signals have similar frequencies. The technique offers the possibility of use where the modulation frequency approaches the theoretical limit of half the carrier frequency.

As will be appreciated, an advantage of the above circuit is that it is tolerant of frequency modulation.

Additionally, the sampling technique gives the circuit a linear response.

As a modification of the arrangement of Figure 1, the circuit may be arranged to make the monopulse widths controlling the sample-and-hold devices automatically controllable so that a varying subcarrierfrequency may be accommodated.

This may be achieved by generating timing pulses as shown in Figure 3.

In Figure 3(b) timing pulses are produced from an incoming signal (see Figure 3(a)) using the same method as used to produce the timing pulses of Figure 2(b). The pulses are then shifted by A/4 of the instantaneous wavelength to produce pulses as in Figure 3(c). Additionally Q and#flip-flop outputs as in Figures 3(d) and 3(e) are produced in the same manner as those produced in Figures 2(c) and 2(d).

The pulses in Figures 3(b) and 3(c) and the Qflip-flop output in Figure 3(d) are then passed through an AND gate to produce pulses as in Figure 3(f) and the pulses in Figures 3(b) and 3(c) and the Q flip-flop output in Figure 3(e) are then passed through an AND gate to produce pulses as in Figure 3(9). The pulses of Figures 3(f) and 3(9) may therefore be used for sample-and-hold devices in a similar mannerto the pulses produced by monostables 15 and 16 of Figure 1 thus obviating the need for monostables in the circuit.

Alternatively the A/4 shifted pulses of Figure 3(c) may be produced by passing the original signal of Figure 3(a) through a 900 phase-shifter and the pulses of Figure 3(c) produced therefrom using a method similar to that used to produce the pulses of Figure 3(b) from the signal of Figure 3(a).

With only minor alterations, the circuit of Figure 1 may be adapted to demodulate a frequency modulated wave provided that the range of modulating frequencies is small compared with the frequency, f, say, of the unmodulated carrier.

In the frequency demodulation mode the monostables 15 and 16 are set to output pulses to the sample-and-hold devices at a set frequency, the set frequency being falri (where n is a positive integer) for each monostable. The pulse widths are also set to be constant and are such that, for an unmodulated carrier frequency of fO, the end of a pulse coincides with a separate zero-crossing of the carrier.

A sampling operation on an unmodulated signal at frequency f, is illustrated graphically in Figure 4(a).

In Figure 4(a) the sampling interval of length At t = 1/2fro ends at a zero-crossing at time to when the sampled frequency is fO. The sample-and-hold output is therefore zero at frequency fO.

Figure 4(b) illustrates a sampling operation on a frequency modulated wave, the sampled wave having an instantaneous frequency of fur where fO-fa is small relative to fO. The end of the sampling interval, to, does not therefore coincide with a zero-crossing of the carrier. Instead, to corresponds to a finite signal, yea, the nearest zero-crossing of the carrier being at time tq, where that, is small relative to to.

By virtue of the general aproximation sin oc for small it can also be seen that the sample-and-hold output, yon, will be approximately equal to the phase difference 2::f1 (t1 -t0). The frequency, fi, can therefore be calculated.

A problem encountered in this circuit is that the output will be sensitive to edge jitter since dyldt is a maximum near the sampling interval.

The invention is not confined to the details disclosed above. In Figure 1 outputs from the flip-flop, 10, may, for example, be taken directly to the monostsabls, 15 and 16, rather than being first fed through AND gates 11 and 12. However, the arrangement without the AND gates places the onus for timing precision upon the flip-flop whereas the circuit of Figure 1 gives a more reliable timing based directly upon the original zero-crossing points. The circuit is therefore tolerant to edge jitter on the flip-flop outputs.

In Figure 1, two sample-and-hold devices are shown. However, more than two may be used.

Equally, whilst the method iilustrated in Figure 4 illustrates two sampl devices taking samples alternately, these may be substituted by one device taking all the samples.

In the frequency demodulation application illustrated in Figure 4, a larger value of y, may be obtained by taking a largervalue of A t. In general a sampling interval of m/2fO (where m is an integer greaterthan one) may be taken to improve the signal-to-noise ratio.

In the example shown in Figure 1 the sample-andhold devices together sample and hold all maxima of the positive-going half cycles of the carrier. In a modification of the Figure 1 embodiment every nth positive-going half cycle (n being an integer) may instead be sampled. As n increases, however, the resolution of the demodulator will decrease.

Additionally in the Figure 1 embodiment only the positive-going half cycles of the carrier were used in demodulation. In an alternative system the negativegoing half cycles may be used either instead of or in addition to the positive-going half cycles. Where both negative- and positive-going half cycles are used the demodulator will output two step function outputs representing the modultion signal.

Claims (12)

1. A demodulator for extracting a modulation signal from a modulated carrier signal including latching means for tracking and holding the value of predetermined portions of the carrier and inputting the hold values to a combining means which combines the hold values to produce a step function output representing the modulation signal.

2. A demodulator according to claim 1 for use in amplitude demodulation of an amplitude modulated carrier signal including first latching means for operating in an amplitude demodulation mode in which it tracks the value of and holds the extreme value attained by each 2mth half cycle of the carrier (where m is a predetermined integer) and first combining means for accepting the hold values and outputting a step function signal constituted by successive hold values.

3. A demodulator according to claim 1 for use in frequency demodulation of a frequency modulated carrier signal of frequency f, including primary latching means for operating in a frequency demodulation mode in which it tracks and holds the value achieved by the signal every n/fO seconds after a zero-crossing point of the signal (where n is a predetermined integer) and primary combining means for accepting the hold values and outputting a step function signal constituted by successive hold values.

4. A demodulator according to claim 3 in which the primary latching means is additionally operable in an amplitude demodulation mode according to claim 2 so as to additionally provide an amplitude demodulation capability.

5. A demodulator according to claim 2 wherein the first latching means begins tracking of the carrier signal at a zero-crossing point and holds the value of the signal achieved 1/4 carrier cycle later.

6. A demodulator according to any previous claim in which the latching means includes at least one sample and hold device.

7. A demodulator according to claim 2 in which the first latching means consists of two sample-andhold devices, each device being arranged for tracking the value and holding the extreme value of each 4mth half cycle, the two devices also being arranged for working 2m half cycles out of phase and wherein the first combining means forms the step function output by accepting extreme values from each sample and hold device alternately for a duration of 2m half cycles each to form a continuous output.

8. A demodulator according to any previous claim in which each sample-and-hold device is controlled by timing pulses derived by monitoring zero-crossing points of the carrier.

9. A demodulator according to claim 3 wherein the primary latching means begins tracking of the carrier signal at a zero-crossing point.

10. A demodulator according to claim 2 in which second latching and combining means are provided for operating 2m' + 1 half cycles out of phase with the first latching and combining means (where m' is an integer) in order to produce an additional step function output representing the modulation signal.

11. A demodulator according to claim 3 in which secondary latching and combining means are provided for operating n/2fO seconds out of phase with the primary latching and combining means in order to produce an additional step function output representing the modulation signal.

12. A demodulator substantially as herein described with reference to the accompanying drawings.