GB2099648A - A signal processing system - Google Patents

Abstract

The invention relates to the provision of an analogue signal processing arrangement for use with a micro-computer. The host microcomputer is provided with a signal processing hardware board SPHB which is connected to the address and data buses of the host microcomputer. The hardware board consists of a signal processing program store SPPS, a board control logic CL and a number of analogue signal handling channels CH 1-4. Each channel (see Fig. 3) includes a programmable timer, a counter, a random access memory, an input path including an analogue-to-digital converter and an output path including a digital-to-analogue converter. The hardware board SPHB is controlled by the host microcomputer so that the memory in a channel is used to store waveform samples generated by the host microcomputer or the input path for presentation to the host microcomputer or the output path as required. In addition the program store SPPS is adapted to hold machine- code signal processing programs executed by a call from the host micro-computer. <IMAGE>

Description

SPECIFICATION A signal processing system The invention relates to an analogue signal processing system for use with a micro-computer.

With the advent of micro-computers a large number of personal computer systems are being marketed under, for example, the trade names of (i) Commodore Pet, (ii) Apple and (iii) Tandy TRS 80.

Such personal micro-computers are normally organised to operate used the programming language "Basic" and are provided with limited input/output handling capacity. One of the aims of the present invention is to provide an analogue signal processing system suited for connection to the address and data buses through, for example, one of the input/output ports of a personal computer, thereby allowing analogue signal handling software to be written for the personal micro-computer.

According to the invention there is provided an analogue signal processing system for use with a host micro-computer including a signal processing arrangement comprising a plurality of analogue signal handling input/output channels each including (a) a programmable timer, (b) a counter, (c) a random access memory, (d) an input path including an analogue-to-digital converter and (e) an output path including a digital-to-analogue converter, the memory being addressable by the counter which is driven from the programmable timer to store waveform samples generated by the analogue-to-digital converter or the host micro-computer, the programmable timer being conditioned in accordance with the sample sequence required.

According to a feature of the invention the signal processing arrangement includes a programmable read only memory adapted to store signal processing machine code subroutines and the arrangement further includes a signal processing arrangement control logic adapted to be addressed from the host micro-computer to select the subroutines and the channels to be used by the microcomputer for the control of the signal processing arrangement in performance of the required signal processing operations.

Typically the system is arranged such that the performance of a signal processing program is executed by a sequence of host computer program instructions together with calls to the required ones of the signal processing machine code subroutines to manipulate and use the information held in the random access memory of a selected input/output channel.

Each input/output channel may consist of 4096 bytes of static RAM, a 16 programmable timer, an eight bit analogue-to-digital converter, and eight bit output digital-to-analogue converter, an associated counter, multiplexer, address decoding and interface chips, and a buffered eight bit digital output.

The control logic may consist of address decoders providing for the selection of one of four EPROM sockets at system address $A000XAFF in hexidecimal, and one of eight input/output channels or EPROM sockets at system address 5! 9000 59FFF hexidecimal.

Each input/output channel may also consist of control data ports at system address gE9FO~ gE9FF, with associated address decoders.

Each input/output channel can sample an input signal at a rate determined by its programmable timer, programmed by the micro-computer, for example a Commodore Pet Computer, and store 4096 successive samples. These samples may then be displayed through an output digital-to-analogue converter or transferred to the RAM of the micro-computer. The hardware sampling board may also accept 4096 eight bit numbers from the micro-computer, which may then be repeatedly cycled through to form a periodic output signal.

Input/output channel may operate synchronously but at the same or different sampling rates, as determined by the host micro-computer, and while one input/output channel samples an input signal, another may provide a repeatedly cycled output, in any desired combination.

The 6502 micro-code computer programmes may be written to provide efficient and rapid computation of the Fast Fourier transform (FFT) or auto or cross correlation of one or more input signals, or of 4096 eight bit numbers generated by the micro-computer. The FFT program may be based on 16 bit by 8 bit multiplication of signal amplitudes and trigonometric constants, so that for example the FFT of 1024 successive signal amplitudes may be calculated in less than 13 seconds. The auto or cross correlation may be the sum of 8 bit by 8 bit products, stored as 32 bit sums, representing up to 2048 sample delays. The computation time for a 256 point auto or cross correlation, involving 256x256 products, is approximately 22 seconds.

In addition, a separate program may provide for the computation of the amplitude statistics of an input or computer generated signal, and the average (dc) and root means square (rms) amplitudes, of an input or computer generated signal.

Still other programs may provide for the display in 50x80 point resolution of computed FFTS, correlation or amplitude statistics in histogram form with a movable cursor.

The signal processing system is advantageously used with the Commodore Pet Computer.

However, the signal processing system may be easily adapted to suit other microcomputers, especially those that use the 6502 micro-processor. The signal processing system may also be adapted for use with a Z80 based micro-computer, or for use with a micro-computer based on a 1 6 bit microprocessor.

If desired additional input/output channels may be added to the signal processing system to provide for cross correlation, cross spectral density analysis, and simultaneous signal input and output for system response measurement.

An embodiment of the invention will now be described solely by way of example and with reference to the accompanying drawings.

Fig. 1 shows the equipment for one embodiment of the invention, Fig. 2 shows the functional block diagram of the hardware system of the invention, Fig. 3 shows the functional diagram of a hardware input/output channel, Fig. 4 shows the circuit diagram of the programmable timer and the read/write and select circuit, Fig. 5 shows the circuit diagram of the counter, input/output channel memory, the programmable timer and the reset logic of a channel, Fig. 6 shows the circuit diagram of a channel input/output path from an analogue point of view, programmable timer, Fig. 7 shows the circuit diagram of a channel input/output path from a digital point of view, while Fig. 8 shows the flow diagram of a typical Basic Program SPECT for use with the equipment of the invention.

Referring firstly to Fig. 1 and Fig. 2 it can be seen that the embodiment of the invention involves the provision of an additional signal processing hardware board SPHB connected to a host personal micro-computer PET. Typically the micro-computer is the 32K version CBM 3032 Pet micro-computer and the additional signal processing hardware board SPHB is connected to the address PAB and data PDB buses of the micro-computer by way of one of its input/output channels. The hardware board SPHB consists of (i) a signal processing program store which is made up of a number of electrically programmable read only memory units (such as EPROM's 2532), (ii) a control logic CL and (iii) a number of analogue signal handling channels CH 1-4. The numbers of channel provided is dependant upon the signal processing to be performed.One of the channels may be connected to an oscilloscope with triggering facilities.

The signal processing program store SPPS is arranged to hold micro-code computer programs which have been written for the microprocessor of the host micro-computer. In the case of the CBM 3032 the micro-processor chip used is a 6502 and therefore the programs stored in the onboard program store SPPS are in 6502 micro-code.

The signal processing hardware board together with the host micro-computer and an oscilloscope connected to one of the channels, allows computed waveforms to be displayed on the oscilloscope or on the screen of the micro-computer and allows results relating to signals applied to one of the channels to be printed out on a printer attached to the micro-computer.

Fig. 8 shows the flow diagram of a typical program which may be executed by the host microcomputer and which makes "calls" to the 6502 micro-code programs stored in the program store SPPS of the hardware board SPHB. (The basic language statements required to execute the flow diagram of Fig. 8 will be considered later). Basically the host micro-computer program depicted in Fig.

8 allows the equipment of the invention to operate as a frequency spectrum analyser for example.

Referring now to Fig. 3 consideration will be given to the equipment provided in each channel CH1-CH4 (Fig. 2) of the hardware board. Each channel consists of (i) a programmable timer PT, (ii) a twelve bit counter COUNT, (iii) an address decoder ADEC, (iv) an address multiplexer, (v) a random access store RAM, (vi) an input path IP including an eight bit analogue-to-digital converter A/D CON and (vii) an output path OP including an eight bit digital-to-analogue converter D/A CON.

Preferably, a TRW TDC 1 00J monolithic AID converter is used for the analogue-to-digital converter AID CON and the maximum sampling rate obtainable is 1 MHZ using a 10 MHZ successive approximation clock. The input voltage range is plus or minus 5 volts. The converter uses a successive approximation technique and a comparator is used to provide decision logic for bit setting.

Referring now to the programmable timer PT, in the rate generator mode, the input clock frequency of 2 MHZ can be divided down by one or two integer numbers N, where N ranges from 2 to 65535 as defined by the value on the data bus PDB. Hence the sample increment timer is from 1 ,uS to as long as 35.8 minutes. The programmable timer controls the stepping of the counter COUNT.

The complete cycle of a periodic input waveform can be sampled, under the control of the counter COUNT, addressing, over ACB, the RAM by way of AMUX by adjusting the frequency division for low frequencies where N is large. With a 256 point display repeatedly cycled at 1,uS sample increment, the maximum fundamental frequency obtainable is 3.9 KHZ.

Referring now to the D/A converter D/A CON, a ZN425E (Ferranti) digital-to-analogue converter is used having a 1 ,uS settling time, and a plus or minus 5 volt output range. The output from the D/A CON is buffered with an Lem31 8 high speed operational amplifier to reduce glitches and to increase the output accuracy.

The performance of the analogue-to-digital circuit may be improved by adding a sample and hold circuit, to reduce input conversion errors.

Referring now to the input/output hardware memory RAM two 16K bit CMOS static RAMs (6116) provide 4096 bytes of storage, which may be used to accumulate samples from the A/D CON or to supply samples to the D/A CON under the control of the programmable timer driven counter COUNT. The store is used in the execution of the fast Fourier transform computation, allowing 256, 512 and 1024 point transforms having times of 3,6.5 and 13 seconds respectively to be achieved. The computation time for 256 point auto or cross correlations is approximately 22 seconds. As far as signal generation is concerned an 8-bit (256 level) resolution is available for defining up to 4096 points. The waveforms can be generated as blocks of 256, 512, 1024, 2048 or 4096 points.The smallest sample increment time possible is 1 microsecond which gives a 256 point fundamental frequency of 3.9 KHZ.

The actual integrated circuit components required to implement one embodiment of the programmable read only memory and an analogue handling channel are shown in Figs. 4, 5, 6 and 7.

Fig. 4 shows the on-board programmable read only memory block using 2532 type EPROM's together with the program and channel selection circuits. Throughout the following description reference will be made to the integrated circuits used in Figs. 4, 5, 6 and 7 and these references relate to the types of integrated circuits (i.c.) employed. Normally the reference will define a Texal Instruments integrated circuit reference number unless otherwise stated and one or more pin number references have been included to show how the ic's are connected. The selector circuits in Fig. 4 select the read or write functions for the selected channel using i.c's 74121 (a monstrable multivibrator controlled by micro-computer signal 02) and the NAND gates (74LS00 and the hex inverter (74LS04).

The channel selection logic involves decoder/demultiplexor (74LS1 38) in which selection signals C2, C3 and C4 select channels 1 to 7 in accordance with their coded values (001 selecting channel 1 and 111 selecting channel 7). The 000 state of C2, C3 and C4 selects ROM 4 of the Signal processing program store SPPS while ROMS 1,2 and 3 are selected by control signals CO and C1 from the decoder/demultiplexor (74LS 139). Certain input/output channel functions are controlled from the signal processing program store SPPS and the octal D flip flop (74LS374).This i.c. is used to latch the control bits CO to C7 for the control of the programmable timer (addresses $EPFO~$E9F3) the input/output control (addresses $E9F4~$E9F7) the reset logic ($E9F8~$E9FB) and the control/select signal (address $E9FF).

Fig. 5 shows the input/output channel memory RAM (i.c.'s 6116's), the programmable timer PT (8253--CC-5) and the twelve bit counter COUNT (three 74LS1 61). Also shown in Fig. 5 is the address decoder ADEC (three 74LS 157) for the RAM and this selects either the counter or the address bus PAB to control the RAM address. The data input/output paths for the RAM are controlled by the transceivers (74LS245) feeding the input/output circuits over leads IDB/ODB on the host micro-computer data bus PDB.

Fig. 6 shows the analogue-to-digital converter (TRW TDC 1001 CJ) and the digital to analogue converter (Ferranti ZN425E). In Fig. 6 a number of operational amplifiers (LM318) are shown which are used to stabilise the operations of these two components. In Fig. 6 the connections to and from the channel memory RAM is not shown as this has been separated out into Fig. 7. The analogue to digital converter (TDC 1001 CJ) has an output buffer (74LS244) which drives the input part of the internal bus IDB/ODB whereas the digital-to-analogue converter (ZN425E) is provided with an input buffer (74LS374) driven from the output part of the IDB/ODB path. Also included in Fig. 7 is a power supply (7805) which allows the signal processing hardware to be independant of the host micro-computer for regulated power supplies.

In operation the host micro-computer sets up the required hardware channel by programming the programmable timer PT and setting the R or W wire and then "calls" the required micro-code routines stored in the program store SPPS of the signal processing hardware board by selecting the required start address. The called micro-code routines allow the host micro-computer to exercise control over the operation and functions of the signal processing hardware board to execute the required signal processing operations using the random access memory RAM in the channel to store the required signal samples. The signal to be evaluated may be connected to one of the input paths and a trace may be displayed by connecting an oscilloscope to one of the output paths.

The flow diagram for the operation of the equipment of the invention by way of example as a frequency spectrum analyser is shown in Fig. 8. In executing this program SPECT the host microcomputer sets-up the hardware board channel to provide the frame waveform to adjust the oscilloscope display and then asks for the parameters for the analysis. The host micro-computer then conditions the relevant channel hardware board programmable timer PT to the frequency division and sets the channel to the sample mode by actuating the A/D CON in the channel. The host microcomputer then calls the required micro-code routine in the hardware board program store SPPS to sample and save the waveform applied to the input lead IP of the channel in the channel's memory RAM. The next operation after the assembly of the required number of samples in the RAM is to call the fast fourier transform micro-code routine FFT to process the stored samples. This requires that the channel is set to the display mode allowing the host micro-computer to address the RAM in the relevant channel over PAB and to read the data addressed (i.e. the samples) from the micro-computer's data bus PDB. Upon the completion of the FFT routine the SQR and PLOT 8 micro-code routines are called to display the amplitude spectrum of the sampled waveform. The starred points in Fig. 8 show actions which involve control over the hardware board or calls to the micro-code routines. The actual BASIC language program listing for a typical SPECT program is reproduced below.It is intended that this program listing should only be by way of example and it will be apparent to those skilled in the art that many alternative programs can be designed for use with the equipment of the invention.

Program "SPECT" 10 PRINT "FREQUENCY SPECTRUM ANALYSER" 20 A0=10*256*16:M=14*256*16+9*256+128 22 POKEM+7, 64+22:POKEM+5, 4 'c' set fre. divider to 500khz for output 1 (A/D clock) 30 SYS6*256*1 6+4*256+1 4#l 6 'c' clear hardware board memory 40 POKEAO, 255:POKEAO+l, 255:POKEAO+2, 255:POKEAO+3, 255 'c' form a sync pulse 50 POKEM+7,20:POKEM+4,6 'c' set 0 to 383 khz for display 60 POKEM, 56:POKEM, 60:POKEM, 52 'c' set display mode 65 PRINT:PRINT 70 PRINT "PLEASE ADJUST THE SCOPE DISPLAY" 72 PRINT:PRINT 80 PRINT "SAMPLE lNCREMENTTlME=INPUT/2 (MICRO SEC)" 90 PRlNT:INPUT "NO. FOR FRE.DIV. (2-65535)"; A 100 PRINT "SAMPLING FREQUENCY="; 2000/A; "KHZ" 110 PRINT "SAMPLE INCREMENTTlME="; A/2000; "MS" 120 PRINT:PRINT "IS IT OK? (Y/N)" 125 GETM$:@FMS= " " THEN 125 128 IFM$="N"THEN90 130 Al =lNT(A/256):A2=A-A1 *256 140 POKE828, A2 :POKE829, Al 'c' set fre. div. output 0 150 SYS6*256*l 6+4*256+10*16 'c' call subroutine to set 160 P0KEM,57:POKEM,61 :POKEM,53 'c' sample 1024 pts.

170 IF PEEK(M)=255 THEN 170 'c' wait for sampling 180 SYS6*256*l 6+4*256+11*16+5 'c' save sampled waveform 190 P0KEM+7,20:P0KEM+4,6 200 PRINT:PRINT "NOW SCOPE DISPLAYS SAMPLED WAVEFORM" 210 POKEM,56:POKEM,60:POKEN,52 220 PRINT "SAMPLE AGAIN? (Y/N) 230 GETMS:lFM$=""THEN230 240 IF M$="Y" THEN 90 250 PRINT:PRINT "COMPUTING FFT" 260 POKE26,10:POKE827,5 'c' set mun=l 0 @@ noc=5 270 POKE59411,60:SYS6*256*16+4*256+32 'c' disable keyboard call 'FFT' 280 POKE59411,61 'c' enable keyboard 282 PRINT:PRINT 290 PRINT"DO YOU WANT THE RESULTS PRINTED? (Y/N)" 300 GETM$:IF M$=" " THEN 300 310 IFM$="N"THEN500 320 MM=5*256*16:OPEN1,4 330 PRINT:PRINT "FREQUENCY SPECTRUM" 340 PRINT::PRINT"DF=";2000/(512*A);"KHZ" 350 PRINT "HARMONIC COSINE SINE MAGNITUDE" 360 FORI=OTO511 370 C1=PEEK(MM+1024+I):C0=PEEK(MM+I) 380 S1=PEEK(MM+3072+1):S0=PEEK(MM+2048+I) 390 IF Cl < 127 THEN CC=Cl*256+C0 'c' convert l's complement numbers 400 IF Cl > 127 THEN CC=256*(Cl-255)+C0-256 'c' into basic variables 410 IF S1 < l27 THEN SS=S1*256+S0 420 IF Sl > l27 THEN SS=256*(S1--255)+S0--256 430 AM=SQR(SS*SS+CC*CC) 440 PRlNT,I,CC,SS,AM:NEXTI:CLOSEl ,4 500 MM=5*256*l6 501 POKEMM,O:POKEMMtl 024,0:POKEMM+2048,0::POKEMM+3072, O 'c' null 0th harmonic 505 SYS6*256*l 6+1024+128 'c' call for 'SQR' @t 'PLOT 8' 510 POKEM+7,20:POKEM+4, 12 520 POKEM,40:POKEM,44:POKEM,36 'c' display amplitude spectrum 524 PRlNT:PRlNT 525 PRINT:PRINT"DF=";2000/(5l2*A);"KHZ" 530 PRINT"STARTAGAlN? (Y/N)" 540 GET M$: IF M$=" " THEN 540 550 RUN c comment (not in the program) The actual machine code program loaded into the read only memories of course may be tailored to suit any required signal processing operations; the following give examples of these programs and their allocation in the read only memories on the hardware board.

Program index Note: Programs located in the $AOOO--$AFFF block 6502 Execution Basic Execution Program Name From To Address Address PROUTIL $A000--$A08B AMP1 $A000--$A01B $A000 $A000 AMP2 $A01C--$A037 $A01C $A01C SAVE $A038--$A042 $A038 -- RESAVE $A043--$A04D $A043 -- CLEAR $A04E--$A066 $A04E $Ao4E COPY $A067--$A09B $A067 $A067 PROGRAPH $A08C--$A17E $A09C $Ao9C TABLE $Ao8C4A09B PROTRIG $A180--$A27E $A280 $A280 PROFFT $A2F3--$A4F8 $A2F3 $AF1C PRODIVI $A4F9--$A58E $A4F9 PROMULTI $A58F--$A617 t $A58F PROBIT $A618--$A69F $A618 $AF29 PROSQR $A6A0--$A838 $A6A0 $AF33 PROPHASE $A839~$AA5C $A889 $AF3D PROPLOT255 $AA5D--$AB77 $AA5D $AF47 PROCORR $AB78--$AC3A $AB78 $AF51 PROSUB $AC3B--$AD37 $AC3B $AC3B PROSCALE $AD38--$AE87 $AD38 $AF65 PROSCREENA $AE88--$AEF8 $AE88 $AE88 PROSYM $AEF9--$AF1B $AEF9 $AEF9 PROCAL $AF1C --$AF6E FFT $AF1C--$AF28 $AF1C $AF1C BIT (Reversal) $AF29~$AF32 $AF29 $AF29 SQR $AF33--$AF3C $AF33 $AF33 PHASE $AF3D--$AF46 $AF3D $AF3D PLOT $AF47--$AF50 $AF47 $AF47 CORR $AF51--$AF5A $AF51 $AF51 SUB $AF5B~gAF64 $AF5B $AF5B SCALE $AF65~$AF6E $AF65 $AF65 Program descriptions Program PROUTIL AMP 1~Calculates the amplitude density of numbers from $9000--$90FF and adds results to previous results stored in the work space, $4500--$48FF. There are 256 amplitudes each stored with 32 bit resolution. The least significant bytes are at $4500--$45FF, next bytes at $4600--$46FF, . , . . . . , most significant bytes at $4800--$48FF.

AMP2-Calculates the amplitude density of numbers from $9800--$98FF. Results are added to previous results at $490O--$4CFF with 32 bit resolution.

SAVE-Save zero page ($00--$FF) atat$44OO#44FF.

RESAVE-Restore zero page.

CLEAR-Sets to zero all memory between S and D, exclusive of D. The addresses for S and D are in zero page S=($0F,$10) D=($FE,$FF) LO HI LO HI COPY-Copy N bytes from S to D. The value of N is stored in zero page, NL0=NHI-$O2.

Program PROGRAPH Double density graphics for the 40 column PET screen, plots up to 50 points horizontally by 80 points vertically. The point to be plotted has coordinates (XR,YR) where 0 XR 49 and O < YR < 79 and XR is stored at$4D11, YR at$4D12. The program is controlled by SR at$4D10. If SR=0 a point is set at (XR,YR), if SR=1 a point is reset. If SR=w the program checks to see if a point has been set at (XR,YR).

If a point is set then RE=1, if not set then RE=O, where RE is at $4D15.

Program PROTRIG Calculates the sine and cosine table needed by the fast Fourier transform (FFT) program. The table consists of 2M-' sine and 2M-'cosine values where M#10, allowing FFTs as large as 1024 points.

The table is stored with 16 bit resolution. The sine table is at$4O00#4l FF while the cosine table is at $4200--$43FF.

Program PROFFT Calculates the FFT of 2M 8 bit data values using 16 bit sine and cosine values in a table set up by PROTRIG. The program is controlled by Registers 1-8 located at $4Doo~$4DO7.

Reg 1 =M, 2M point FT Reg 2=maximum number of outer loop count after which PRODIVI is called.

Reg 3=start of array real part of FFT, low byte Reg 4=start of array real part of FFT, high byte Reg 5=start of array imaginary part of FFT, low byte Reg 6=start of array imaginary part of FFT, high byte Reg 7=start of cosine table Reg 8=start of sine table The data to be transformed is stored at the array pointed to by Reg 3, which will contain the real part of the FFT after the transform is completed. The result of the FFT calculation is in bit reversal form, and is put in standard form by PROBIT.

The amplitude and phase of the FFT may be calculated using PROSQR and PROPHASE where

phase=tan-' (imaginary/real) Multiplications in the FET are performed by PROMULTI which gives 8 bit by 16 bit products.

Program PRODIVI Numbers calculated by the FFT program are scales by dividing by 2, using Reg 1~Reg 6 as in PROFFT.

Program PROMULTI Multiples 8 bit by 1 6 bit numbers for FFT calculation.

Program PROBIT The bit reversal results from the FFT program are put in standard form and stored in the same space. Uses Reg 1 -Reg 6 as for PROFFT.

Program PROSQR Calculates /(real)2+(imaginary)2 and stores result in 16 bit resolution in the real part array pointed to by Reg 3 and Reg 4. Uses Reg 1 -Reg 6 as for PROFFT.

Program PROPHASE Calculates tan#1(imaginary/real) and stores the result in an array pointed to be Reg 7. The phase in the range 0 --360 is calculated with 8 bit resolution. A threshold is set in Reg 8, so that FFT real and imaginary values below this threshold, which would cause in accurate phase calculations, are ignored. The program must be called before PROSQR, which destroys the real and imaginary part of the FFT. Uses Reg 1~Reg 6 as for PROFFT.

Program PROPLOT 255 Scales 16 bit numbers produced by PROFFT to N bit resolution, where N+1 is stored in Reg 5.

Data start address is stored in Reg 1 (low byte) and Reg 2 (high byte), and the number of data points is stored in Reg 3 (low) and Reg 4 (high). Results are stored in a page pointed to by Reg 6.

Program PROCORR Calculates the auto or cross correlation of 8 bit numbers stored in arrays S and t.

The results (C0,C1,C2,C3,... Con~1) are calculated with 32 bit resolution, and stored at $5000--$56FF. Data is at S-4#58009#58FF and t-45CO0#5FFF. The value of m is stored in Reg 1 (low byte) and Reg 2 (high byte). The number of correlation values, n, is stored in Reg 3 (low) and Reg 4 (high).

Program PROSUB Finds the minimum value of a set of correlation values and subtract this from all values. The number of correlation values is stored in Reg 1 (low) and Reg 2 (high).

Program PROSCALE Scales 32 bit numbers produced by PROAMP 1, PROAMP2 and PROCORR to 16 bit form. The number of points to be scaled is stored in Reg 1 and Reg 2, while the 32 bit numbers to scaled are in pages pointed to be Reg 3~Reg 6. The results are stored in the pages pointed to by Reg 3 and Reg 4.

Program PROSCREENA Plots an 80 column histogram of data on the Pet screen, leaving the top and bottom line of the display free for text. Data to be plotted starting address is stored in Reg 1 (low byte) and Reg 2 (high byte). The first 80 values starting at this address are plotted.

Program PROSYM Copies data from S to D, storing n bytes at D in reverse order. Used in calculating the spectral density of correlation data, where it is assumed that C#n=Cn. S=($0F,$10), D=($FE,$FF), N=($01,$02).

Program PROCAL Program such as PROFFT must be called from PROCAL, which first saves zero page, executes the program, and restores zero page.

The above description has been one of one embodiment only and it is not intended that the invention should be limited thereto; for example alternative micro-code routines will for example readily be seen by those skilled in the art.

Claims (10)

Claims

1. An analogue signal processing system for use with a host micro-computer comprising a signal processing arrangement including a plurality of analogue signal handling input/output channels each including (a) a programmable timer, (b) a counter driven by the programmable timer, (c) a random access memory, (d) an input path including an analogue-to-digital converter and (e) an output path including a digital-to-converter, the memory being addressable (i) by the counter to store waveform samples generated by the analogue-to-digital converter or to read out waveform samples to drive the digital-to-analogue converter or (ii) by the host micro-computer to load computer generated samples into the memory or to read stored samples from the memory into the host micro-computer.

2. An analogue signal processing system according to claim 1 in which the signal processing arrangement includes a read only memory arranged to store host micro-computer machine code subroutines adapted to be executed by the host micro computer by a call operation specifying the required start address in the read only memory.

3. An analogue signal processing system according to claim 1 or 2 in which the original processing arrangement is connected to the data and address bus of the host micro-computer.

4. An analogue signal processing system according to any one of the preceding claims in which the programmable timer is adapted to be conditioned to control the storage of the required sequence of waveform samples from the host micro-computer in the random access memory.

5. An analogue signal processing system according to any one of the preceding claims in which the signal processing arrangement includes a control logic adapted to be addressed by the host micro-computer to select sub-routines and the channels to be used for the control of the signal processing arrangement in the performance of the required signal processing operations.

6. An analogue signal processing system according to claim 5 in which the host micro-computer is arranged to perform a signal processing program by executing a sequence of host computer program instructions together with calls to the required ones of the original processing machine code subroutines to manipulate and use the information held in the random access memory of a selected input/output channel.

7. An analogue signal processing system according to claim 6 in which the read only memory stores a machine code program for calculating the amplitude density of analogue signal samples stored in a channel memory.

8. An analogue signal processing system according to claim 6 in which the read only memory stores a machine code program for calculating the sine and cosine values for analogue signal samples store in a channel memory.

9. An analogue signal processing system according to claim 8 in which the read only memory stores a machine code program for calculating the fast fourier transform of the sine and cosine values in the channel memory.

10. An analogue signal processing system substantially as herein before described with reference to the accompanying drawings.