GB2248696A - Computer controlled test apparatus - Google Patents

Computer controlled test apparatus Download PDF

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Publication number
GB2248696A
GB2248696A GB9022176A GB9022176A GB2248696A GB 2248696 A GB2248696 A GB 2248696A GB 9022176 A GB9022176 A GB 9022176A GB 9022176 A GB9022176 A GB 9022176A GB 2248696 A GB2248696 A GB 2248696A
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GB
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Application
Patent type
Prior art keywords
test
instruments
unit
common
control database
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GB9022176A
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GB2248696B (en )
GB9022176D0 (en )
Inventor
Ann Ledwith
John Healey
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intepro Systems Development Ltd
INTEPRO SYSTEMS DEV Ltd
Original Assignee
* INTEPRO SYSTEMS DEVELOPMENT LIMITED
INTEPRO SYSTEMS DEV LIMITED
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3181Functional testing
    • G01R31/319Tester hardware, i.e. output processing circuit
    • G01R31/31903Tester hardware, i.e. output processing circuit tester configuration
    • G01R31/31908Tester set-up, e.g. configuring the tester to the device under test [DUT], down loading test patterns

Abstract

A test apparatus includes a control computer (8) which transmits test instructions via a serial interface circuit (7) to various instruments (3) to control the instruments while testing any type of electronic device, e.g. a power supply (2), and the set of instruments (3) may be changed without amendment of the test instructions being required. This is achieved by use of stored common control test instruction units (A-J Fig 3 not shown) which are converted to specific test units by reference to a stored control database (Fig 3a not shown) associated with a type of device under test and a stored configuration table for any configuration of test instruments. <IMAGE>

Description

"A Test Apparatus and Process" The present invention relates to the testing of electronic devices such as power supplies. More particularly, the invention relates to testing of electronic devices using a number of different test instruments.

Heretofore, one method of testing electronic devices using different instruments is to connect up each instrument in turn and to manually control the instrument to transmit test signals to the device under test and receive and monitor the corresponding output signals. This is clearly time-consuming, although a good degree of versatility is allowed. To improve the speed with which devices are tested, test apparatus has been developed which includes a number of test instruments which are connected to a controller. The test instruments are connected via suitable sockets and cables to the device under test. In use, the controller receives strings of test instructions from memory grouped into units and transmits the test units to the instruments to control operation of the instruments in testing of the device under test.Such a test apparatus is described in the United States Patent Specification No. 4812996 (Tektronix).

One problem with such a test apparatus and process is that whenever the device under test is changed to a different type of device, the test instructions stored in memory must be replaced by another set. Thus, a user must develop a whole suite of sets of test instructions and load these into the controller whenever a different type of device is to be tested. An even worse problem is that if a user wishes to change the instruments which are used for testing of a device, the set of test instructions must be analyzed and reconfigured. This allows very little versatility and in practice users avoid changing instruments, even when a change would be desirable to enable an improved test to be carried out for a device. When a user does change the instruments, the time involved in changing the set of test instructions can be prohibitive.

A still further problem with operation of such test apparatus is that there is generally a very large amount of memory required for storage of a complete set of test instructions for any one electronic device. Thus, a secondary storage device must be used, delaying access by a computer and slowing down the testing operation.

The present invention is directed towards providing a test apparatus and process to overcome at least some of these problems.

According to the invention there is provided a process carried out by a processor of a test apparatus for electronic devices, the apparatus further comprising a plurality of test instruments for generating test signals and monitoring corresponding output signals for a device under test, a memory means, user input and output interfaces, and instrument input and output interfaces, the process comprising the steps of:: storing in the memory means code for a set of common test units, each unit including one or more test instructions for test instruments; storing in the memory means a control database associated with a type of device under test, the control database having elements specifying the sequence of common test units to be used for testing of the type of device, and values for parameters included in the common test units; storing in the memory means a configuration table including code specifying characteristics of the instruments; addressing elements of the control database in a pre defined sequence and reading references for common test units in the order in which they are to be executed; for each common test unit, retrieving from the control database values for parameters of the common test unit and merging the values with the common test unit to generate a specific test unit; subsequently retrieving characteristic values for instruments to be controlled by the specific test unit and generating and transmitting command strings defined by the specific test unit to the relevant instruments according to the characteristic values for control of the instruments in testing of the device under test.

According to another aspect, the invention provides a test apparatus comprising a plurality of test instruments for generating test signals and monitoring corresponding output signals for a device under test, and a controller having a processor connected to a memory means, user input and output interfaces and user instrument input and output interfaces, the processor being operable to perform the steps of :: storing in the memory means code for a set of common test units, each unit including one or more test instructions for test instruments; storing in the memory means a control database associated with a type of device under test, the control database having elements specifying the sequence of common test unit to be used for testing of the type of device, and values for parameters included in the common test units; storing in the memory means a configuration table including code specifying characteristics of the instruments; addressing elements of the control database in a pre-defined sequence and reading references for common test units in the order in which they are to be executed; for each common test unit, retrieving from the control database values for parameters of the common test unit and merging the values with the common test unit to generate a specific test unit; subsequently retrieving characteristic values for instruments to be controlled by the specific test unit and generating and transmitting command strings defined by the specific test unit to the relevant instruments according to the characteristic values for control of the instruments in testing of the device under test.

In a preferred embodiment of the invention the pre-defined sequence of the processor addressing elements of the control database comprises sequential addressing of the elements of the database and addressing elements out of numerical order when directed by a previous element.

In another embodiment, the memory means comprises a read/write memory and a fixed disk, the control database being stored in the read/write memory for access by the processor.

The invention will be more clearly understood from the following description of some preferred embodiments thereof, given by way of example only with reference to the accompanying drawings in which: Fig 1 is a perspective view of a test apparatus of the invention; Fig 2 is a schematic diagram illustrating the test apparatus in more detail; Fig 3(a) and 3(b) are schematic representations of a control database and common test units of the apparatus.

Referring to the drawings, there is illustrated a test apparatus of the invention, indicated generally by the reference numeral 1. The test apparatus 1 is shown in use connected to a device under test (DUT) 2 which in this case is a power supply for a microcomputer. The apparatus 1 comprises a plurality of test instruments 3 which are in the form of circuit boards connected in a rack 4 having front panel connectors 5 to facilitate connection of the instruments 3 with the DUT 2. A serial interface bus 6 connects the instruments 3 with a serial interface circuit 7 connected in a control computer 8 for the apparatus 1. The control computer 8 comprises a processor 9, a fixed disk drive 10 and a floppy disk drive 11. A user output interface is provided by a visual display unit (VDU) 12 and a user input interface is provided by a keyboard 13.The control computer 8 also includes a read\write or random access memory (RAM) 16. A printer 17 is also connected to the processing unit 9.

The instruments 3 connected in the rack 4 in this embodiment include two load cards 20 and a driver card 21 to which is connected a DC source 22. The instruments 3 also include a digital volt meter (DVM) 23, a scanner card 24, a counter timer 25, a transient card 26, a power relay 27, a digital input/output card 28 and a ripple/noise meter 29.

An AC source 30 having an AC source driver 31 are also connected in the rack 4.

Briefly, in operation, under instructions from a user via the keyboard 13, the processor 9 retrieves test instructions from the various memory devices and transmits these instructions via the serial interface circuit 7 and the bus 6 to the instruments 3. These test instructions control operation of the instruments 3 to allow them transmit test signals to a device under test and to receive and monitor the corresponding output signals. The instruments 3 then transmit the monitored output signals back to the processor 9 which directs storage of the test results in memory. The results are also displayed at the visual display unit 12 and may be printed at the printer 17, if desired. In many instances, a trace record#r may also be used for output of test results.

The load cards 20 are arranged to dissipate up to 125 Watts with a maximum current of 25 amps. The loads may operate under specified constant current or constant resistance ranges and dynamic loads use low voltage field effect transistors.

In this embodiment, any number of up to a maximum of six load cards 20 may be used. The ripple/noise meter 29 is used for measuring high frequency peak-to-peak noise from the device under test. The digital volt meter (DVM) 23 is arranged to measure both DC and AC voltage levels and also resistance in two ranges which may be specified. The scanner card 24 is used to switch the DVM card 23 to the load cards 20 and to the DC source 22. The scanner card 24 has eight channels. The counter timer card 25 measures signal frequencies up to a maximum frequency and a minimum pulse width. The transient card 26 measures voltage and current transients in the device under test and the power relay card 27 is used for general purpose power switching to simulate switches or to switch in external circuits.The digital input/output card 28 has sixteen parallel logic input/output lines which may be used to read from or write to a digital circuit. The DC source 22 and the AC source 30 provide input voltage signals for the DUT 2.

Other instruments may be connected in the rack 4, depending on the tests which are to be carried out. For example, a pulse slew card may be used to control the load cards 20 with a pulse which has a programable rise time, fall time, mark time, space time and amplitude.

The following describes the manner in which the processor 9 transmits test instructions to the instruments 3. Initially, the processor 9 directs storage in the fixed disk 10 of common test units. Each common test unit comprises a set of test instructions. The test units are referred to as being common because they may be used with any type of device under test and further, they may be used with any set of instruments used for testing. A set of common test units labelled A through to J are represented schematically in Fig 3(b). One test unit may, for example, be used for inputting various AC current signals to a device under test and thus it may control operation of not only the AC source 30 but also the DVM card 23 for monitoring the corresponding outputs.Thus, each common test unit relates to a particular type of test but is not used for one particular instrument and it may, indeed, be used for controlling several instruments.

When tests are to be run on a device under test, the processor 9 retrieves the common test units from the fixed disk 10 and stores them in the RAM 16 where they may be accessed by the operating system. Further, the processor 9 directs storage in the RAM 16 of a control database associated with the particular type of device under test. For example, there would be a control database for power supplies for a particular type of microcomputer and there would be a different control database for power supplies for telecommunications equipment. Portion of a sample control database is illustrated in Fig 3(a) in which it will be seen that in reading the control database row-by-row the processor firstly sees a reference for a common test unit followed by values for parameters of that common test unit. This is described in more detail below.Finally, the processor 9 directs storage in the RAM 16 of a configuration table, not shown, which includes values for characteristics of the particular instruments connected in the test apparatus 1.

Thus, there is a configuration table for each set of instruments, however, in practice the configuration table is in modular format so that a user may add or delete modular portions of the table which relate to separate instruments so that the table may be easily modified for addition or deletion of instruments. The type of information stored in the configuration table includes addresses for the instruments, maximum and minimum voltages, current or resistance capabilities, the format of control strings (for example, IEEE) which must be used for controlling the instrument.

To initiate operation of the instruments 3, the processor 9 reads the control database element-by-element. In this example, a reference for the common test unit A is given in the first control database element and subsequently, a tolerance range for various voltage values is given. For example, the tolerance range "0.65" has a maximum display of 0.6565V and a resolution of 0.0325mV for operation of the DVM card 23. The processor 9 merges the common test unit A with the values which are specified for the parameters and subsequently reads from the configuration table stored in the RAM 16 the characteristics of the instruments which are used by the test unit A. In this example, the configuration table would include the physical address and maximum settings of the DVM card 23 which is used by the test unit A. The configuration table would also include characteristic values for other instruments used by the test unit A. The test unit A may now be regarded as a specific test unit because it includes all of the specific values for parameters to allow generation by the processor of command strings for the particular device under test and further, the processor knows the characteristics of the instruments which are used.

Command signals generated according to the specific test unit A are then transmitted to the instruments 3 which in turn carry out the various tests and transmit the results back to the processor 9 which directs output of the test results as described above. This procedure is repeated for each test unit referred to in the control database in turn. In this example, the next test unit which is run is test unit D which is run immediately after A and then test unit C and so on. To further illustrate operation, the first element includes a reference for test unit C and this is followed by a value for the first voltage range which is 0.5 volts. This is in turn followed by the minimum and maximum full scale readings for this range which in this case are 0.498 and 0.501. The values are used for control by the test unit C of the driver card 21.

The processor 9 will continue to read the control database as the tests for each test unit are completed. It does not necessarily read the control database row-by-row as an element in the control database may direct the processor to another element which is out of order. This happens most often when a test unit, say F, requires the running of test unit A as a sub-test and rather than include all of the code of test unit A in the test unit F, the test unit A is simply referred to and run in the usual manner.

It will thus be appreciated that the test apparatus of the invention may be used with any type of device under test without amendment to the common test units which are stored in the fixed disk. All that is necessary is to load a control database for the particular type of device under test.

Further, a user may change the test instruments used for any particular device under test without having to change the test code. All that is required is the loading of a configuration table which corresponds to the set of test instruments. In practice, modules of the configuration table are added or deleted as required, each module including characteristic values for a particular instrument. It will be appreciated that the addition and deletion of these modules is a relatively simple operation. Another advantage of the operation is the fact that the speed of testing is considerably improved because the common test units may be stored in RAM because they take up relatively little memory space as there is no repetition, even whereof, a particular test operation is to be carried out several times in one testing session.This is due to the fact that the control database simply refers to the same common test unit again and again as required, the common test unit being stored only once. Heretofore, because the test instructions were so lengthy, the read/write memory of most microcomputers was not large enough to store it.

The test apparatus may be supplied to a user together with a control database for each type of device which may be tested.

The control databases may be easily loaded to the control computer 8 via, for example, via the floppy disk drive 11 and further, a user will generally feel free to change instruments 3 in the rack 4 such as changing from one type of digital volt meter to another without the need to change test instructions. All that is necessary is to amend the configuration table by deletion of a module and addition of the relevant module.

This is a particularly important feature of the invention especially since instruments are being improved and modified on an on-going basis and there is often a need to replace certain instruments.

The invention is not limited to the embodiments hereinbefore described, but may be varied in construction and detail.

Claims (8)

1. A process carried out by a processor of a test apparatus for electronic devices, the apparatus comprising a plurality of test instruments for generating test signats and monitoring corresponding output signals for a device under test, a memory means, user input and output interfaces, and instrument input and output interfaces, the process comprising the steps of:: storing in the memory means code for a set of common test units, each unit including one or more test instructions for test instruments; storing in the memory means a control database associated with a type of device under test, the control database having elements specifying the sequence of common test unit to be used for testing of the type of device, and values for parameters included in the common test units; storing in the memory means a configuration table including code specifying characteristics of the instruments; addressing elements of the control database in a pre-defined sequence and reading references for common test units in the order in which they are to be executed; for each common test unit, retrieving from the control database values for parameters of the common test unit and merging the values with the common test unit to generate a specific test unit; subsequently retrieving characteristic values for instruments to be controlled by the specific test unit and generating and transmitting command strings defined by the specific test unit to the relevant instruments according to the characteristic values for control of the instruments in testing of the device under test.
2. A process is claimed in Claim 1, wherein the pre-defined sequence of the processor addressing elements of the control database comprises sequential addressing of the elements of the database and addressing elements out of numerical order when directed by a previous element.
3. A process is claimed in Claims 1 or 2, wherein the memory means comprises a read/write memory and a fixed disk, the control database being stored in the read/write memory for access by the processor.
4. A test apparatus comprising a plurality of test instruments for generating test signals and monitoring corresponding output signals for a device under test, and a controller having a processor connected to a memory means, user input and output interfaces and instrument input and output interfaces, the processor being operable to perform the steps of storing in the memory means code for a set of common test units, each unit including one or more test instructions for test instruments; storing in the memory means a control database associated with a type of device under test, the control database having elements specifying the sequence of common test unit to be used for testing of the type of device, and values for parameters included in the common test units; storing in the memory means a configuration table including code specifying characteristics of the instruments;; addressing elements of the control database in a pre-defined sequence and reading references for common test units in the order in which they are to be executed; for each common test unit, retrieving from the control database values for parameters of the common test unit and merging the values with the common test unit to generate a specific test unit; subsequently retrieving characteristic values for instruments to be controlled by the specific test unit and generating and transmitting command strings defined by the specific test unit to the relevant instruments according to the characteristic values for control of the instruments in testing of the device under test.
5. A test apparatus as claimed in claim 4, wherein the pre defined sequence of the processor addressing elements of the control database comprises sequential addressing of the elements of the database and addressing elements out of numerical order when directed by a previous element.
6. A test apparatus as claimed in claim 4, wherein the memory means comprises a read/write memory and a fixed disk, the control database being stored in the read/write memory for access by the processor.
7. A process substantially as hereinbefore described with reference to the accompanying drawings.
8. A test apparatus substantially as hereinbefore described with reference to the accompanying drawings.
GB9022176A 1990-10-12 1990-10-12 A test apparatus and process Expired - Fee Related GB2248696B (en)

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Application Number Priority Date Filing Date Title
GB9022176A GB2248696B (en) 1990-10-12 1990-10-12 A test apparatus and process
BE9001008A BE1002408A6 (en) 1990-10-12 1990-10-24 The apparatus and test method.

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GB9022176D0 true GB9022176D0 (en) 1990-11-28
GB2248696A true true GB2248696A (en) 1992-04-15
GB2248696B GB2248696B (en) 1994-11-23

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2274716A (en) * 1992-09-22 1994-08-03 Mistrock Microsystems Limited Circuit tester
GB2281631A (en) * 1993-09-07 1995-03-08 Liu Shun Fa Test apparatus
US6366924B1 (en) * 1998-07-27 2002-04-02 Caliper Technologies Corp. Distributed database for analytical instruments
EP1309238A2 (en) * 2001-10-31 2003-05-07 Agilent Technologies, Inc. Controlling data flow across an RF barrier

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2274716A (en) * 1992-09-22 1994-08-03 Mistrock Microsystems Limited Circuit tester
GB2281631A (en) * 1993-09-07 1995-03-08 Liu Shun Fa Test apparatus
US6366924B1 (en) * 1998-07-27 2002-04-02 Caliper Technologies Corp. Distributed database for analytical instruments
US6647397B2 (en) 1998-07-27 2003-11-11 Caliper Technologies Corp. Distributed database for analytical instruments
EP1309238A2 (en) * 2001-10-31 2003-05-07 Agilent Technologies, Inc. Controlling data flow across an RF barrier
EP1309238A3 (en) * 2001-10-31 2004-12-22 Agilent Technologies, Inc. Controlling data flow across an RF barrier

Also Published As

Publication number Publication date Type
BE1002408A6 (en) 1991-01-29 grant
GB2248696B (en) 1994-11-23 grant
GB9022176D0 (en) 1990-11-28 application

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PCNP Patent ceased through non-payment of renewal fee

Effective date: 19950223