GB2095916A

GB2095916A - Circuit boards

Info

Publication number: GB2095916A
Application number: GB8110019A
Authority: GB
Original assignee: Kollmorgen Technologies Corp
Current assignee: Kollmorgen Technologies Corp
Priority date: 1981-03-31
Filing date: 1981-03-31
Publication date: 1982-10-06
Also published as: GB2095916B

Abstract

A method of producing multi-layer circuit boards includes the steps of applying a mask over the circuit pattern on a base leaving - at the points to be interconnected - a window in the mask; applying an adhesive coating over the mask with the adhesive coating extending over the mask windows and onto the circuit pattern metal to form a second smaller window; treating and depositing metal on said adhesive coating to form a second circuit pattern on the plane of said adhesive and interconnecting the second circuit pattern with the first circuit pattern at said second windows; and, repeating said steps until a circuit board with the desired number of planar circuit patterns is produced.

Description

SPECIFICATION Method for producing circuit boards and products produced thereby The present invention relates to a method for producing circuit boards and, more particularly, to a method for producing such boards having circuit patterns on two or more planes.

It is well known to manufacture circuit boards with circuit patterns on opposite sides of the board composed of insulating material. In connection with such circuit boards, known under the term "doublesided circuit boards with through-plated punchedhole connections", the circuit pattern conductors disposed on opposite sides of the board and forming a current path are interconnected through metallized walls of punched holes provided throughout the insulating base or substrate. The metal coating on the metallized walls of the holes is provided in a way that the metal forms an electrical connection between the respective circuit patterns.

It has heretofore been proposed to produce multiplane circuits from a plurality of thin insulating substrates, supporting on their surfaces circuit patterns, by a method of pressing under heat. The connection between the conductors disposed on different planes is established in such multiplane circuit boards by means of punched holes provided at the respective points of connection. The walls of such punched holes are provided with a metallic coating which forms the electrical connection between the respective circuit patterns. In a variation of this process, the walls of the holes are not only metallized, but the holes themselves are filled with metal.

The use of holes filled with metal or of holes with metallized walls as interconnections between the circuit patterns of different planes of a multiplane circuit board has the disadvantage that the interconnections between the circuit patterns on the surfaces of the circuit board within the multiplane complex are unavallable for additional connections, indpendent components, and the like. This means that large areas of the circuit patterns are consumed or unavailable for connections, mounting holes, components, and the like. This leads to the necessity for making the circuit boards larger in size. Such larger size is undesirable not only from the standpoint of cost, but also because of the use of highly integrated components and the increasing trend to miniaturization, the advantages of which thus being lost.

It has been proposed to interconnect the circuit patterns on multiplane circuit boards with connecting hole perforations with small diameters. However, this results in making the process for producing such holes much more complicated and the formation of a reliable metallization of the walls of the holes more difficult without bringing the problem to a fully satisfactory solution.

It has also been proposed to produce multiplane circuit boards in a manner such that a masking layer is applied after the preparation of the conductor pattern on the first plane, the masking layer leaving those areas exposed at which electrical connections are described between the conductor pattern of the first and the conductor pattern of the next-following plane. The exposed areas permit the formation or build-up of interconnections between the conductor pattern on the first and second conductor pattern planes in the known manner by electroless metal deposition. The interconnection between the conductor patterns of subsequent layers is effected by the application of such a masking layer, with electric- al connection points exposed, on each layer before the next conductor pattern plane is applied.Interconnections between the conductor patterns are then built up during subsequent electroless deposition at the exposed connections points.

It has been found that this masking method is not suitable for producing reliable contact connections capable of withstanding mechanical and thermal stresses.

It is an objective of the method of the instant invention to produce, in an economical and spacesaving manner, circuit boards in which the connections between conductor patterns disposed on successively arranged planes are formed without the use of holes with metallized walls. The multiplane circuit boards so produced are interconnected between the circuit patterns on successively arranged planes in an improved and novel manner.

According to the present invention, a method is provided for producing printing circuit boards hav ing at least two planes of conductor patterns, in the course of which method there is first prepared the conductor pattern of the first plane which is subsequently provided with a layer of insulating mask, leaving exposed those areas of the conductor pattern of the first plane destined for building up interconnections with the corresponding conductor pattern of a next following plane of conductor patterns, and subsequently there is prepared the conductor pattern of the second plane by metal deposition, in the course of which metal deposition the simultneously formed metal coating on the exposed areas of the conductor pattern of the first plane of conductor patterns not covered with the masking layer and hereinafter referred to as the "first windows" interconnects the corresponding conductor pattern of the two planes, characterized in that, following the application and drying of the insulating masking layer, there is applied over said masking layer a layer of an adhesive capable of being rendered microporous, polar and wettable by a subsequent treatment step, said adhesive layer being applied across the edges of the first windows in the masking layer and onto the metal surface of the respective conductor pattern, but leaving a second, smaller window on the exposed metal surface of the conductor pattern; and subsequently# treating said adhesive layer with an agent thus rendering said adhesive layer microporous and wettable without attacking the metal of the conductors to any detrimental extent or at all, and depositing on said treated adhesive layer and the exposed metal surface of the conductor pattern a metal deposition by electroless metal deposition alone or in combination with galvanic deposition or by any other known method for depositing a metal coating, to form a second conductor pattern on said adhesive layer interconnected at said second, smaller windows to the first conductor pattern.

If it is intended to use in excess of two planes of conductor patterns, the steps of the method of the present invention are repeated for the number of times corresponding to the number of planes.

It has been discovered that it is particularly advantageous to use as the adhesive layer a coating containing an additive capable of rendering said layer catalytic for the electroless metal deposition, either completely or at least on its surface. Suitable catalytic additives are, e.g., organo-metallic compounds of a Group IB and VIII metal.

The use of the adhesive coating on the dielectric insulating layer in accordance with the instant invention permits the production of circuit boards which are suitable for practical applications and satisfy the requirements for mechanical and thermal stresses. Such circuit boards are compact and durable.

It has been further discovered that the manufacture of circuit boards according to the present invention requires that the adhesive coating extends beyond the edges of the windows formed in the dielectrical masking layer and up onto the exposed metal surface of the circuit pattern of the first circuit plane, said adhesive coating leaving exposed a second, smaller window. This permits the build-up of an even metal coating on the second conductor plane forming the second plane conductor pattern as well as the connections at designated connector points to the conductor pattern of the first plane in an operationally reliable way.

If the circuit boards produced according to the method of the instant invention are used in connection with components suitable for being mounted in the surface, corresponding areas of contact are produced on the ultimate conductor pattern plane of the circuit board.

If punched or drilled holes are to be used for mounting components with connecting leads, said holes may be provided in known manner with a metal coating on the walls for enhancing the properties of the soldered junctions.

According to the instant invention, such circuit boards having holes with metallized walls can be manufactured in a particularly simple manner if use is made both of an adhesive material having catalytic properteisforthe electroless metal deposition and a basematerial provided with catalyzing additive.

According to a further embodiment of the instant invention, connecting holes with metallized walls may be used for connecting, in a known manner, circuit patterns disposed on opposite sides of the basematerial. Since all or the majority of the connections between connector patterns disposed on different planes are thus formed without holes with metallized walls, the economical exploitation of the surface of the circuit boards and their excellent operational reliability are fully retained.

The first plane or planes of conductor patterns are used for building up conductor patterns with relatively low density. Such patterns are produced, e.g., by the screen printing method.

The following plane or planes are then used for building up conductor patterns with high density which, if need be, may be produced by photoprinting. In this way, it is possible to use different methods for the manufacture of conductor patterns for circuit boards with circuit patterns disposed on only two or on a plurality of planes and gain, through the use of the less costly screen printing method, a layer or layers with low conductor pattern density.

This provides an extremely economical production process.

For producing the microporous, polar and wettable area on the surface of the adhesive layer, the method according to the present invention employs an agent which does not attack the metal ofthecicuit pattern or attacks the metal only to a very limited degree. The use of an alkaline permanganate solution was found to be particularly useful where the circuit pattern is of copper.

Advantageously, the dielectrical masking layer is applied in the form of a resin coating having a dry coating film thickness of from 30 to 100 um.

Particularly suitable are epoxy resin mixtures or mixtures comprising epoxy and phenolic resins. The preferred thickness of the dry film is 50 um. Suitable adhesive coatings found useful in the practice of the instant invention are, e.g., two-phase resin systems containing a component causing, underthe influence of a suitable medium, the formation of micropores.

Tests carried out by applicant have shown that the area of the second window, thus the window in the adhesive coating layer, has advantageously a size of from at least 0,1 t 1.0 mm2, and preferably a size of at least 0,5 mm2. The method according to the present invention is explained in greater detail with the help of the following examples.

Example 1 The basematerial used for a circuit board provided with conductor patterns in two planes is a commercially available di-electric basematerial clad with copper on one side. After cutting the board to size, the cleaned copper surface is provided with a covering mask conforming with the desired conductor pattern such as, e.g., by using the screen printing process. Following the etching step and removal of the masking layer, the circuit board provided with the desired conductor pattern on the first plane is inspected.

A permanent masking layer composed of dielectric insulating material is applied to the inspected fist plane. This is achieved by applying an epoxy resin mixture by means of screen printing, leaving windows exposed on the circuit pattern where interconnections are to be made. The size of such windows is selected slightly larger than the size of the areas required for forming the interconnections. After curing the resin mixture for about 1 hour at 1200C, a dry film thickness of 50rum is obtained.

Next, an adhesive coating, composed of a phenolic resin modified with butadiene nitrile rubber and containing an organometallic compound of palladim, is applied by screen printing. The adhesive coating is applied to and extends beyond the edges of the windows provided in the dielectric masking layer and onto the metal surface of the circuit pattern, leaving a second window having a smaller area than the first window. The area of the second window has a size of 0.5 mm2 in the present example.

Subsequently, the adhesive coating is cured for 40 minutes at 160at and exposed for 1 to 3 minutes at 50 to 60aC to an alkaline permanganate solution for forming micropores as well as a polar, wettable surface on the cured adhesive coating. Such alkaline solution contains 40 to 60 g/l potassium permanganate and 40 to 60 g/l sodium hydroxide.

After washing with water, diluted hydrochloric acid and again water, the exposed copper surfaces in the second windows are briefly cleaned in an ammonium persulfate solution at 30 to 40 C. This solution contains between 100 and 250 g/l ammonium persulfate.

After washing with water, diluted hydrochloaric acid and again water, a metal coating covering both the surface of the adhesive layer and the copper surfaces in the second windows, is deposited from an electroless copper deposition bath solution. The thickness of the thus deposited copper coating is selected in the range of between 0,5 and 2,5 Fm.

A masking layer corresponding to the negative of the conductor pattern desired for the second plane is applied by photoprinting and the conductors are built up in a galvanic bath with high levelling capability.

The circuit board is finished by printing with solder stop paint and punching from the work board.

Example 2 The procedure as specified in example 1 is followed to the application and curing of the adhesive coating layer. Following the curing step, a mask corresponding to the negative of the circuit pattern desired on the second plane is imprinted again leaving exposed the second windows. The adhesive layer is subsequently treated with the potassium permanganate solution and the work board admitted, after the washing steps, into a bath for the electroless deposition of copper. The board remains in said bath until the conductor pattern has formed to the desired thickness. Following washing, a mask of solder stop paint is applied and cured, and the circuit boards are subsequently punched from such work board.

Example 3 For producing a circuit board with four planes of conductors, the procedure of examples 1 or 2 is first followed. Prior to the application of the solder stop paint mask, the following process steps are repeated two additonal times: - application and curing ofthe dielectric masking layer; - application and curing the adhesive layer: - treatment with the potassium permanganate solution; and - build-up of the conductor patterns on the respective plane.

Example 4 The method of this example is based on a dielectric base-material which is clad with Copper on both sides and which contains fully dispersed therein a substance for catalytically sensitizing the surfaces of said basematerial for the electroless metal deposition. It was found that an addition suitable for said purpose is an organometallic compound of palladium, which is added to the resin mixture used for producing the basematerial.

First, the circuit patterns of the first two planes of conductor patterns are produced is known manner on the opposite sided of the basematerial. Subsequently, each of the two surfaces supporting the conductor patterns are provided - as specified in example 1 - with the dielectric and adhesive coatings. Through-extending holes are subsequently provided at points at which the conductor patterns disposed in planes on the opposite sides of the basematerial are to be connected. Susequently, the walls of the said through-holes are built up together with the conductors of the second planes as specified in examples 1, 2 or 3, and the circuit board is finished.

Example 5 The method of this example is based on a dielectric basematerial supporting, instead of a copper cladding, an adhesive coating. The first plane of the conductor pattern is subsequently completely built up in known manners by means of electroless metal deposition alone or such metal deposition combined with subsequent galvanic deposition, in order to then proceed in the way specified in one of the preceding examples 1 through 4.

Example 6 The basematerial used is a dielectric, one-sided copper clad basematerial. Such material is first provided with the conductor pattern of the first plane and subsequently, as specified in example 1, with the dielectric masking layer and the adhesive coating. However, different from example 1, the adhesive coating used in the present example contains no additive for catalyzing the electroless metal deposition, Following the treatment with the potassium permanganate solution, the board is exposed to a catalytic sensitizing bath solution for sensitizing the board for the electroless metal deposition. In the present case, the solution used contained the reaction product of palladium (II) chloride and tin (II) chloride.

The method was then continued as specified in example 1. The method of the instant invention, as exemplified by the foregoing examples and description, produces efficiently and economically multiplane circuit boards in which the circuit patterns on the respective planes are interconnected in a manner durable to both mechanical and thermal shock.

Claims

1. A method for producing printed circuit boards having at lease two planes of conductor patterns, in the course of which method there is first prepared the conductor pattern of the first plane which is subsequently provided with a layer of insulating mask, leaving exposed those areas of the conductor pattern of the first plane destined for building up interconnections with the corresponding conductor pattern of a next following plane of conductor patterns, and subsequently there is prepared the conductor pattern of the second plane by metal deposition, in the course of which metal deposition the simultaneously formed metal coating on the exposed areas of the conductor pattern of the first plane of conductor patterns not covered with the masking layer and hereinafter referred to as the "first windows" interconnects the corresponding conductor patterns of the two planes, characterized in that, following the application and drying of the insulating masking layer, there is applied over said masking layer a layer of an adhesive capable of being rendered microporous, polar and wettable by a subsequent treatment step, said adhesive layer being applied across the edges of the first windows in the masking layer and onto the metal surface of the respective conductor pattern, but leaving a second, smaller window on the exposed metal surface of the conductor pattern; and subsequently treating said adhesive layer with an agentthus rendering said adhesive layer with an agent thus rendering said adhesive layer microporous and wettable without attacking the metal of the conductors to any detrimental extent or at all, and depositing on said treated adhesive layer and the exposed metal surface of the conductor pattern a metal deposition by electroless metal deposition alone or in combination with galvanic deposition or by any other known method for depositing a metal coating, to form a second conductor pattern on said adhesive layer interconnected at said second, smaller windows to the first conductor pattern.

2. The method as claimed in claim 1, characterized in that the second window area has an opening having a size of at least from 0,1 to 1,0 mm2.

3. The method as claimed in claim 2, characterized in that the size of the second window opening is at least .5 mm2.

4. The method as claimed in any preceding claim, characterized in that the dry film of the masking layer is composed of dielectric material and present with a thickness of from 30 to 100 ttm and the adhesive layer has a thickness of from 10 to 50 ttm.

5. The method as claimed in claim 4, characterized in that the masking layer has a thickness of 50 Ftm and the adhesive layer has a thickness of 20 um.

6. The method as claimed in any preceding claim, characterized in that the adhesive layer contains a substance which - either as such or subsequent to an appropriate treatment step - is capable of catalytically initiating on its surface the electroless deposition of the metal from suitable metal bath solutions.

7. The method as claimed in any preceding claim, characterized in that the adhesive layer is treated with an alkaline permanganate solution to render said layer microporous and wettable.

8. The method as claimed in any preceding claim, characterized in that the initial basematerial used for the circuit board contains dispersed therein a substance causing the surface and the whole walls of said circuit board to be coated with an adherent metal layer when exposed to an electroless metal deposition bath.

9. The method as claimed in any preceding claim, characterized in that the surface formed by the adhesive layer and the metal coating in the windows of the same is exposed to an electroless metal deposition bath solution, and that, subsequently, on the thus deposited metal layer a masking layer corresponding to the negative of the desired conductor pattern of the respective conductor plane is formed, and that, thereupon, the conductor pattern is built up by galvanic deposition.

10. The method as claimed in claim 9, characterized in that the elctrolessly formed layer is first reinforced by galvanic deposition and that a galvanic bath with high leveling capability is used for building up the conductor pattern.

11. The method as claimed in claims 9 and 10, characterized in that all planes of conductor patterns are arranged exclusively on one side of the basematerial for the circuit board; and that in the step of galvanic metal deposition two circuit boards are placed in the bath solution with their sides free of conductor patterns facing each other and touching each other completely or almost.

12. The method as claimed in any preceding claim, characterized in that holes with metallized walls are formed simulaneously with the build-up of the conductor pattern of one plane and the connections the conductor pattern of the next plane, said holes serving as holes for mounting components or as the connections of circuit patterns disposed on different sides of the basematerial, or for both said purposes.

13. The method as claimed in any preceding claim, characterized in that conductor patterns with a relatively low density are used for the planes of conductor patterns disposed adjacent the surface of the basematerial, and that a higher density of conductor patterns is selected for the next plane or for a number of planes of conductor patterns exceeding two and built up in each case later.

14. The method as claimed in claim 13, characterized in that the conductor patterns having the lower density are produced by screen printing and those having a high density by means of photoprinting.

15. Printed circuit board with conductor patterns in at least two planes, characterized in that said circuit board is produced according to any of preceding claims 1 to 14.