GB2095015A - Pulse shaping circuit - Google Patents

Abstract

In a keyboard e.g. a telephone push button keyset, to avoid the disturbing effects of contact bounce, each of the row (X1-X4) and column (Y1-Y3) conductors is connected via an RC filter (e.g. R1, R10, C1) to a respective one of a set of flip-flops (FF1-FF7). Also connected to these flip-flops are the outputs of a gating network (NG1-2-3-4) which enables the flip-flops as long as the voltage on a capacitor C8 exceeds the threshold of NG3. C8 is charged as long as at least one of the X filters or at least one of the Y filters is producing an (actuated) output, and proceeds to discharge when neither of these two conditions obtains. <IMAGE>

Description

SPECIFICATION Pulse shaping circuit This invention relates to a pulse shaping circuit, especially to such a circuit which, in response to signals from one or more mechanical contacts, supplies pulses each of at least a preset duration and whose level is independent of the contact characteristics. Such a circuit is useful, inter alia, for data entry keysets and telephone keysets.

Such data entry devices often use keysets with a matrix arrangement each crosspoint of which has a control key, and one or more contacts. Key depression closes the corresponding contact(s).

Electronic circuitry connected to the row and column conductors detects such a closure and in response supplies signals identifying the depressed key. The circuit operation is fast compared with that of the key contacts. Now, whatever precautions are taken during contact manufacture, one cannot avoid micro-breaks during the closing time of these contacts or amplitude variations of the signal they retransmit, i.e. contact bounce an electronic circuit, due to its high speed and sensitivity, may react to them and generate erroneous signals.

An object of the invention is thus a pulse shaping circuit, which may be inserted between the keyset outputs and the electronics for supplying pulses whose level is independent of the contact characteristics and whose duration at least equals a preset duration, allowing correct operation of the electronics. This circuit not only makes it possible to be freed from contact micro breaks but also from greater breaks of keysets whose quality has become defective.

According to the invention, there is provided a pulse shaping circuit for use in association with n signal sources, which includes n memorization means respectively associated with said n signal sources each having a signal input connected to the associated signal source, a control input, and 'an output on which the signal received on the signal input is retransmitted when a signal is supplied to the control input, and a delay circuit for each said signal source one input of which is connected to its one of the n signal sources and one output of which is connected to the control input of a respective one of the n memorization means, in which the arrangement is such that as soon as the effective presence time of the signal from a said source is equal to a preset minimum duration, the delay circuit for a signal source which supplies a signal supplies a control signal to its said memorization means, which control signal is maintained during a preset time in the absence of any signal from said n signal sources.

An embodiment of the invention will now be described with reference to the accompanying drawings, in which: Fig. 1 is a block diagram of a known telephone keyset; Fig. 2 is a detailed circuit of a pulse shaping circuit, embodying the invention; Fig. 3 shows waveforms illustrating the operation of the circuit of Fig. 2.

The keyset KB of Fig. 1 has four row conductors X1, X2, X3 and X4 and three column conductors Y1, Y2 and Y3. A crosspoint of row conductor Xi (i=1 to 4) and column conductor Yj (j=1 to 3) is associated with a contact cxtj and a contact cy connected between the reference potential (earth), and respectively the row Xi and column Yj conductors. Thus, for example, a contact cx43 between X4 and earth and a contact cy34 between Y3 and the earth are associated with the crosspoint of conductors X4 and Y3.

Upon depressing the corresponding key (not shown) these two contacts close and the reference potential appears on conductors X4and Y3. This potential is detected by a utilizing circuit (not shown) whose inputs are connected to the row and column conductors. This circuit differentiates between the accidental presence of earth potential on one of the conductors due to a spurious pulse from the presence thereof due to a key depression. To achieve this, the utilizing circuit responds only when the earth potential is present for a preset minimum time simultaneously on a row conductor and a column conductor. When these conditions are met, the utilizing circuit supplies signals identifying the depressed key.

It is usually assumed that the contact closure time due to a key depression may reach a minimum of about 40 ms, the release between two successive depressions of the same key being at least 60 ms. If the contacts associated with this key generate microbreaks or even resistance increase, the above-mentioned minimum duration may not be reached or the depressed key identification may be disturbed, causing erroneous operation of the utilizing circuit.

A pulse shaping circuit such as shown in Fig. 2 solves this problem. This circuit inserted between the keyset KB of Fig. 1 and a utilizing circuit DC, includes two four inputs, NAND gates NG 1 and NG2, seven R-S flip-flops FF1 to FF7, two resistors R8 and R9 and a capacitor C8.

The four inputs of the gate NG 1 are respectively connected to the row conductors X1 to X4 of the keyset KB. Three inputs of the logic gate NG2 are respectively connected to the column conductors Y1 to Y3 of the keyset KB, the fourth input of this gate being connected to any other input. The output of NG 1 is connected to the anode of a diode D1 whose cathode is connected to the reference potential (earth, in the present case) through two series resistors R8 and R9. The output of NG2 is connected to the anode of a diode D2 whose cathode is connected to the cathode of the diode Dl The common point of resistors R8 and R9 is connected to a capacitor C8 whose other side is earthed, and also to the R inputs of the bistables FF1 to FF7 via a pulse shaper formed by two NAND gates NG3 and NG4 series-connected.The S inputs of flip-flops FF1 to FF4 are respectively connected to the row conductors X1 to X4 of the keyset KB via respective conductors X"1 1 to X"4 and a filter. To be free from disturbances due to possible spurious pulses, such as those due, for example, to electrostatic discharges when the user lightly touches the keys before depressing one or more keys, such a filter is associated with each keyset output conductor. This filter consists of a 1 50 Kohms resistor (R10 to R16), for example, series connected with the output conductor, and a 22 nF capacitor (C1 to C7), connected in this case between this output conductor and earth.The column conductors Y1 to Y3 of this keyset are respectively connected to the input S of the flip-flops FF5 to FF7, through respective conductors Y" 1 to Y"3 and associated filters.

The complementary outputs Q of these flipflops are respectively connected to input conductors X' 1 . . ., X'4 and Y' 1 . . ., Y'4 of the utilizing circuit DC.

Each of the flip-flops FF1 to FF7 is formed by NAND logic gates. They supply a complementary output signal of logic level 1 when their input R receives a 0 logic level signal whatever the logic level of the signal supplied on their input S. They supply a complementary output signal of logic level 0 when their inputs S and R respectively receive a 0 logic level signal and a 1 logic level signal. When both inputs S and R receive a 1 logic level signal, these flip-flops remain in their previous state, and supply a complementary output signal identical to the previously complementary supplied signal.

The pulse shaping circuit of Fig. 2 also includes resistors R1 to R7 each connected between one of conductors X1,. ..,X4 and Y1, . . ., Y3 and a positive voltage source Ve (+5 V, for example).

Now we describe the operation of the circuit of Fig. 2, referring also to Fig. 3.

The circuit DC whose input conductors X' 1 to X'4 and Y'1 toY'3 are ail at "1" does not respond.

We now assume that the associated key, e.g.

at the crosspoint of X2 and Y1 is depressed. This is illustrated in Fig. 3 atKh.

As above-seen, this key depression must cause the simuitaneous closure of the associated contacts cx2 1 and cy12 (Fig. 1) (contacts cx2j and cyl i of Fig. 2). To facilitate the description, faulty contacts have been chosen; first, only the contact cx2j closes. The conductor is earthed via the resistor R1 1 and the contact cx2j, which is indicated by the passage of the chronogram cxij from the logic level 1 to the logic level 0, so a "O" signal is sent to the input S of the flip-flop FF2 and to one input of the gate NG 1. In response, the latter supplies a "1" signal (5V), so diode D1 conducts and retransmits this signal to the capacitor C8, through the resistor R8. The capacitor C8 charges.

As long as the voltage across this capacitor remains lower than the triggering threshold of the gate NG3, each of the flip-flops FF1 to FF7 receives a "0" signal on its input R. These flipflops, and in particular FF2 remain in their previous state. They supply a complementary signal of logic level 1.

The contact cyl i of Fig. 2 closes so conductor Y"1 is earthed through R14 and contact cy12, which is indicated by the passage of the waveform cyjifrom the logic level 1 to the logic level 0. A "0" signal is supplied to the input S of the flip-flop FF5 as well as to one input of the gate NG2. The flip-flop FF5 is maintained in its previous state by the "0" signal on its input R. The gate NG2 one input of which receives a "0" signal supplies in response a "1" signal (5V). The diode D2 becomes conducting and it retransmits this signal, which has no influence upon the downline circuits as an identical signal is already retransmitted by the diode D1.

As the contact cx2j is held closed, the voltage across the capacitor C8 increases and finally reaches the logic level 1, within a time t. The gates NG3 and NG4 operate and all the flip-flops FF1 to FF7 then receive a "1" signal on their input R.

The flip-flops FF2 and FF5 which receive on their input S a "0" signal and on their input R a "1" signal trigger: they supply a "O" complementary output signal. The other flip-flops each of which receives on its R and S inputs a "1" 'signal are held in their first state and their complementary output signal remains at "1".

The utilizing circuit DC two input conductors of which X'2 and Y' 1, and only two, simultaneously receive a "0" signal is started. It supplies in response, on a non-referenced output, for example, a series of dialling pulses (four in the chosen example) whose number identifies the depressed key.

This key being held depressed, accidental openings of one or of both associated contacts cx2 1 and cy12 may occur, due for example, to contact bounce.

We first assume, for example, that only cx21 opens. The corresponding conductor, X"2, is then connected to the voltage source Ve (5V) through resistors Rl 1 and R2 so that a "1" signal is applied to the input S of FF2. As the contact cyl 2 is held closed, the corresponding conductor, Y" 1, remains earthed. The logic gate NG2 thus receives a "0" signal on one of its inputs, so it holds its output at "1". The signal supplied to the input R of the flip-flops FF1 to FF7 is held at "1".

Accordingly, the flip-flop FF2 which was in its second state and whose inputs R and S receive a "1" signal is held in this second state. Its complementary output signal remains at "O".

Thus, the two "0" signals supplied by the pulse shaping signal of the figure, further to a key depression, are held at this logic level even if the contact cx21 opens and whatever the duration of this opening. It is exactly the same if the contact cy12 opens whereas the contact cx21 remains closed.

Now we consider the case when both contacts cx21 and cy12 open. By a process identical to that just described, the logic level of the signal at the input S of the flip-flop FF2 and the logic level of the signal at the input S of the flip-flop FF5 go from "0" to "1", which has no effect upon these flip-flops as long as their R inputs receive a "1" signal.

Now, the signals respectively sent to the gates NG1 and NG2 through the row and column conductors go from "0" to "1". As all the inputs of these gates are at "1", they respectively output a "0" signal (earth); The diodes D1 and D2 become non-conducting. The capacitor C8 discharges through the resistor R9. As long as the voltage across this capacitor is at least equal to the triggering threshold of FF1 to FF7, the signal supplied by the capacitor C8 to the input R of these flip-flops is at "1". FF1 to FF7 are thus held in their respective previous states. After a simultaneous opening time T of all the contacts, the discharge of the capacitor C8 is such that the signal supplied at the inputs R of FF1 to FF7 goes from "1" to "0".

Then, all of FF1 to FF7 receive a "0" signal on their input R and a "1" signal on their input S, so FF2 and FF5 trigger from the second state to the first state: their complementary output signal goes from "0" to "1". The other flip-flops are held and locked in their first state and their complementary output signal is maintained at "1".

The circuit DC all the inputs of which are at "1" operates no more. It supplies no signal. Thus we have regained the initial state.

Thus, the pulse shaping circuit inserted between a control keyboard KB having two contacts per key and a utilizing electronic circuit so designed that it operates only when two contacts simultaneously close for a minimum time, makes it possible to be freed from the effects of faulty contacts: it supplies a first closing signal as soon as the cumulative closing time of the contacts at least equals a first time t.

From that time, the flip-flops turn on and the signals present on the keyset output conductors, after filtering, will be memorized by two flip-flops, even if they are brief or distorted, which eliminates the disturbances due to micro-breaks or level variations similar to contact openings.

Moreover, it is only after a time T further to the absence of all keyboard output signals that the flip-flops are reset to their initial state, so that the circuit DC receives input signals having at least this duration.

In the above description, a control keyboard with two contacts per key was chosen as an example. The invention is also applicable to keyboards with one contact per key, the more so in circuits having only one key with one single contact intended to control, for example, machine tools through relatively slow electronic circuits operating under low voltage and intensity and requiring closing signals of relatively high minimal duration.

In the above example, the resistors R8 and R9 and the capacitor C8 are so chosen that t=2 and T=40 ms. The logic gates NG3 and NG4 as well as the flip-flops FF1 to FF7 use C-MOS integrated circuits referenced 4011 on the market, each constituted by four two input NAND gates; the two logic gates NG 1 and NG2 are C-MOS integrated circuits referenced 4012 on the market. The decoding circuit DC can be the decoding circuit referenced DF 320 on the market.

Claims (5)

Claims

1. A pulse shaping circuit for use in association with n signal sources, which includes n memorization means respectively associated with said n signal sources each having a signal input connected to the associated signal source, a control input, and an output on which the signal received on the signal input is retransmitted when a signal is supplied to the control input and a delay circuit for each said signal source one input of which is connected to its one of the n signal sources and one output of which is connected to the control input of a respective one of the n memorization means, in which the arrangement is such that as soon as the effective presence time of the signal from a said source is equal to a preset minimum duration, the delay circuit for a signal source which supplies a signal supplies a control signal to its said memorization means, which control signal is maintained during a preset time in the absence of any signal from said n signal sources.

2. A circuit according to Claim 1, and in which said memorization means are R-S type flip-flops.

3. A circuit according to Claim 1 or 2, and in which each said delay circuit is an RC circuit.

4. A circuit according to Claim 1, 2 or 3, in which the n signal sources are derived from x row conductors and y column conductor of an xxy matrix, where n=x+y, and in which gating means ensures that the memorization means are only enabled in response to the presence of both a row signal and a column signal.

5. A pulse shaping circuit substantially as described with reference to Figs. 2 and 3 of the accompanying drawings.