GB2083727A - Optical communications system - Google Patents

Abstract

An optical communications system receives ternary PCM electrical signals and converts these directly to binary line code form and transmits the resultant signals as optical signals along optical fibres. The method of conversion comprises translating the 0 level of the ternary signal to a 10 binary word and the +1 -1 to 11 and 00 binary words respectively. A receiver in the system includes a four terminal FET (21) ass first amplification stage, whose substrate is biased separately. A large valued resistor (26) biases the gate terminal and is connected to an active network acting as an equal magnitude negative resistance at low frequencies. <IMAGE>

Description

SPECIFICATION Optical communications system This invention relates to optical telecommunications systems and in particular to methods of optical coding to represent signals transmitted as Pulse Code Modulated electrical signals on conventional cables.

It is now standard to use a high density code such as HDB3 for PCM transmission. This code represents binary zeros as Ov and binary '1's as alternate +V and -V signals.

A state in which more than three zero's in succession are to be transmitted is prevented by signalling the next zero at V volts with the polarity of the previous mark signal.

Three level codes are not ideal for transmission as optical signals along optical fibres when the optical source is non-linear and it has therefore been proposed to decode received HBD3 signals to binary and then to encode them to a binary line code, e.g. 5B6B, for transmission. In one such system the HDB3 signals are transmitted at 8.448Mbits/s and the optical line code at 10.1 37MBits/s.

It is an object of the present invention in a first aspect to provide a more economical system for translating the HDB3 PCM signals to a binary line code for optical transmission, and to provide apparatus for effecting this translation.

It is an object of the present invention in a second aspect to provide an improved receiver for transmitted optical signals which may receive ternary optical signals or with a simple decoder addition receive binary line encoded optical signals.

According to the invention in a first aspect there is provided a telecommunications system utilising the transmission of optical signals in a binary line code form, wherein these signals represent the information contained in a ternary coded signal received at an input to a transmitter in the system and wherein the ternary signals are encoded directly to binary line code form.

The ternary signal may be a 2Mbits/s HDB3 and the binary line code a 1 B2B 4Mbits/s code.

The +V signals of the ternary signals may be represented as a 11 binary word, the OV signals as a 10 binary word and the -V signals as a 00 binary word.

According to the invention in a second aspect there is provided a receiverfor relatively low bit rate optical signals including as an early amplification stage a four-terminal field effect transistor whose substrate is biased separately, and which has a relatively high value resistance element biasing the gate terminal, connected to an active network which acts at lowfrequencies as a negative resistance of substantially equal magnitude to said high value resistance element.

The active network preferably comprises an operational amplifier and an RC network.

An embodiment of the invention will now be described, by way of example only, with reference to the accompanying drawings. In the drawings: Figure lisa circuit diagram of a transmitter and encoder for use with a system according to-the invention; Figure 2 is a circuit diagram of an integrated input package forming part of a receiver; Figure 3 is a circuit diagram of the receiver into which the input package of Figure 2 is located; Figure 4 is a circuit diagram of a second integrated package in the receiver of Figure 3; and Figure 5 is a circuit diagram of a regenerator/decoder for use with the receiver of Figure 3.

In a system in accordance with the first aspect of the present invention a PCM electrical signal is converted directly to a binary line code for transmission along an optical fibre. Taking HDB3 as an example of the code used for the PCM signals, each bit of the coded signal is converted to a corresponding bit word of the binary line code; as follows: HDB3 bit Binary Word +1 11 0 10 -1 00 Since +1 and -1 level signals occur only singly in the HDB3 code, the binary line code cannot have more than three consecutive identical bits. Thus there is a plentiful supply of transitions to facilitate clock recovery and the low frequency content of the line signal is small, which is an advantage in optical systems.

Furthermore rising edges occur only at the beginnings of the binary words so that synchronisation with these words is relatively easy.

Figure 1 shows a transmitter and encoder for the conversion of a 2Mbits/s HBD3 PCM electrical signal to a 4Mbit/s 1 B2B binary line code. The transmitter includes a signal splitter 1 to which the PCM signal is applied, an encoder 2 also supplied with clocking signals from a clock circuit 3 including a phase locked loop. The output from the encoder feeds a driver circuit 4 which drives the optical transmitter.

The signal splitter 1 separates the +v and -v input signals by means of a transistor TR1 connected to the input terminal such that it is rendered conducing when a +v signal occurs, and a transistor TR2 which is rendered conductive when a -v signal occurs. The collector terminals of both these transistors are at a 'high' voltage level, i.e. are not conducting when a zero level signal is received at the input terminal. Two bistable circuits 5 and 6 are connected to respective collector terminals of the transistors TR1 and TR2 and also to the clock circuit 3. The bistables improve the shape of the received pulses and re-time them with respect to the clocking signal. The Q output from each bistable is connected to a input terminal of a respective one of one NOR gates 7 and 8.The second input of the NOR gate 7 is connected to receive the clocking signals.

The second input to the NOR gate 8 receives the output of NOR gate 7. The resultant output from the NOR gate 7. The resultant output from the NOR gate 8 is the 1 B2B encoded pulse train described above.

This electrical pulse train is fed to the driver circuit 4 for conversion to the transmitted optical signal. The receiver for receiving the optical signal produced by the transmitter of Figure 1 is shown in Figures 2 to 4.

Referring to Figure 2, an input package of the receiver comprises a photo-diode on to which light from the angled end of the transmission fibre is incident. The photo-diode is preferably one which gives high quantum efficiency, low dark current, and low capacitance. In this type of receiver circuit the first transistor stage tends to be the major source of noise; and this transistor stage together with the photo diode determines the receiver sensitivity. This transistor is therefore chosen as a high quality Si JFET 21. A cascode circuit based on a transistor 22 is used to reduce Miller capacitance, increase output impedance and so enable more gain to be obtained from the first stage. A bypass resistor 23 allows the use of a high load resistor without the need for a high supply voltage.A further transistor 24 in emitter - follower configuration provides a low impedance output to a video amplifier 25 with complimentary outputs. A high bias resistor 26 (500M)- is chosen as the bias resistor to the gate terminal of the FET21 so that it contributes negligible noise.

The biasing of the FET 21 will now be described in more detail with reference to Figure 2 and to the full circuit diagram of the receiver (apart from the decoder) shown in Figure 3. The package of Figure 2 is shown as input paCkage 1 in Figure 3. The FET 21 is a 4-terminal device which as an example may have a 3mS gain and 1.5pF input capacitance. The fourth terminal is the substrate which acts as a second gate.To achieve the best noise performance, the device must be operated with VGS = 0. The drain current 1D is controlled by the source/substrate voltage VBS. Feed back from the pre-amplifier output is used to set the substrate voltage; the time constant of this feedback path sets the lower cut-off frequency of the receiver, and is chosen to eliminate as much low frequency noise as possible without distorting the signal.

To maintain the voltage VGS at zero the 500my bias resistor 26 is connected to a network 30 which acts at; low frequencies as an equal negative resistance terminated at earth. The network offsets the voltage across the bias resistor 26 due to the mean photo current that flows through it. This inclusion of a negatiye resistance stems from the need to bias the substrate separately and to keep the input capacitance low by not requiring additional components at the gate terminal of the FET 21.

The negative resistance network is shown in Figure 3 and comprises an operational amplifier in the integrated package IC3. The bias resistor 26 is connected to the inverting input terminal of the operational amplifier and also to each via a resistor 31 (10my), a resistor 32 (13KQ), a variable resistor 33 (10KQ) and a resistor 34(91 OKQ). A feedback loop from the output of the amplifier is connected to the junction between resistors 31 and 32, and the non-inverting input terminal of the amplifier is connected to this loop via a capacitor 35 (10nF); the inverting input terminal being connected to the wiper terminal of the variable resistor 33.

Referring now to Figure 4, the second package in the receiver, shown as package 2 in Figure 3 is a thick -film circuit comprising a simple RC network which compensates for the 6dB/octave roll-off due to the photo-diode and FET capacitance, and a second integrated video amplifier 40. Both complimentary amplifier inputs and both complimentary outputs from the input package are used. This is equivalent to providing 6 dB extra gain.

The two packages described with reference to Figures 2 and 4 produce an amplified output voltage waveform having the same shape as the input current waveform. This waveform is required to be equalised to give the best practical signal-to-noise ratio at the subsequent regeneration stage. In Figure 3, an equaliser is shown which has a low noise-band-width and causes minimal inter-symbol interference. An optimum 3 pole response for a PIN-FET receiver detecting rectangular pulses is designed for the equaliser and realised- by a single pole introduced by a capacitance 41,42 in parallel with the output of the inut package of Figure 2 and a 2 pole active network following the second package shown in Figure 4. The single pole is beneficial at an early stage in the circuit to limit the noise voltage at the output of the second package.A large noise voltage at this point results in limiting which, since it is a non-linear effect, distorts the signal. The active element in the equaliser network includes a first transistor TR3 from the collector of which the output signal is taken to give 6dB gain. A second transistor TR4 is an emitter-follower able to drive 50 or 75 ohms.

This receiver could be used to receive directly HBD3 coded optical signals, but if in accordance with the 6 first aspect of the present invention, it is used to receive the translation of such signals in a 1 B2B binary line code then a decoder/regenerator is required to follow the receiver. Figure 5 shows such a decoder. The receiver output is threshold detected by a comparator 50.

The resultant 1 B2B electrical signals are fed to the data input of latch circuit 51 also supplied with clock signals having the repetition rate of the binary 1 B2B waveform. The 0 output of the latch 51 is fed to one input of a NOR gate 52 and thenoutput to the input of a further NOR gate 53. A second latch circuit 54 has its data input terminal connected to itshoutput terminal. The output from the8output terminal is fed to the NOR gate 52 and the output from its Q output terminal is fed to NOR gate 53.

The output from the NOR gate 53 is fed back to the data input of a third latch circuit 55. These latching circuits and NOR gates serve to separate the 1,1; 1,0; and 0,0 binary line coded signals. The ternary HDB3 2Mb/s output signal is generated by means of a pair of transistors TR5 and TR6, the first a pnp transistor and the second an npn transistor connected between the 0v and - 5v lines. The output signal is taken from one terminal of a capacitor 56 connected to the junction between the collectors of the transistors TR5 and TR6.

Operation of the transistor TR6 is controlled by the connection of its base terminal to the output of latch circuit 55. The transistor TR5 is controlled by a further transistor TR7 whose collector is connected to the base of transistor TR5. The base terminal of transistor TR7 is connected to the output of NOR gate 52 and is controlled thereby. Thus the detection of the three possible two digit binary line sequences results in a corresponding +V, -V, or 0 voltage at the output terminal via the capacitor 56.

Claims (5)

1. A telecommunications system employing the transmission of optical signals in a binary line code form, wherein these signals represent the information contained in a ternary coded signal received at an input to a transmitter in the system, and wherein the ternary signals are encoded directly to binary line code form in the transmitter.

2. A telecommunications sytem as claimed in claim 1 in which the intermediate level of the ternary signal is represented as two different binary values in succession and each of the two other levels of the ternary signal is represented as a predetermined respective one of the two pairs of identical binary values.

3. A receiver for relatively low bit rate optical signals including as an early amplification stage a four-terminal field effect transistor, the substrate of which is biased separately, and which has a relatively high valued resistance element biasing its gate terminal, the resistance element being connected to an active network which acts at low frequencies as a negative resistance of substantially similar magnitude to said high valued resistance element.

4. A telecommunications system substantially as hereinbefore described with reference to, and as illustrated in the accompanying drawings.

5. A receiver for relatively low bit optical signals substantially as hereinbefore described with reference to, and as illustrated in, Figures 2 to 4 of the accompanying drawings.