GB2081053A

GB2081053A - Exchange Synchronisation System

Info

Publication number: GB2081053A
Application number: GB8023462A
Authority: GB
Original assignee: Standard Telephone and Cables PLC
Current assignee: STC PLC
Priority date: 1980-07-17
Filing date: 1980-07-17
Publication date: 1982-02-10
Also published as: BE889654A; FR2487145A1; GB2081053B

Abstract

In a digital telecommunication system a terminal involved in a call is synchronised to the exchange, by a sequential process, as follows:- (a) when a subscriber initiates a call a wake-up signal is sent to the exchange, e.g. a string of 0 bits. (b) when the exchange receives the wake-up signal it sends to the calling terminal a synchronisation check code signal, or flag, e.g. 01111110. (c) when the terminal detects the flag signal it replaces the wake-up signal with the flag signal which "tells" the exchange that the terminal is in synchronism. (d) when the exchange receives the flag signal it sends back a proceed to send signal (equivalent to dial tone), whereafter the caller can dial. If a batch of terminals are coupled to the exchange via a multiplex system an initial synchronisation sequence for that system is interposed, using as its check signal the inverse of the flag, i.e. 10000001.

Description

SPECIFICATION Exchange Synchronisation System This invention relates to an automatic telecommunication system in which all communication between an exchange (often nowadays referred to as a system node) and the subscribers' terminals served is effected digitally.

With such a system it is necessary when communication is in progress that synchronisation be maintained between the subscriber's terminals and the exchange. To ensure that this is done, it is possible for a quiescent terminal to continuously transmit signals to the exchange, but this involves unnecessary power consumption at the terminal, and could also lead to difficulties due to crosstalk. An aiternative technique is to allow the quiescent power to be only that needed to detect incoming signals. Although such a system might be maintained in synchronism at the terminal, it would involve the transmission of a characteristic signal from the exchange, which would also consume power and could cause cross-talk.

An object of the invention is to provide systems in which the above disadvantages are mitigated or overcome.

According to the present invention there is provided an automatic telecommunication system in whichan exchange serves a number of remote terminals with communication between the exhange and the terminals serves being effected digitally, in which on initiation of a call at one of said terminals an unsynchronised signal (hereinafter called a wake-up signal) is sent from the calling terminal to the exchange, in which on reception of the wake-up signal the exchange sends back to the calling terminal a bit stream containing a synchronisation pattern, in which on detection of the synchronisation pattern in the bit stream which it receives from the exchange the calling terminal replaces the wake-up signal with a bit stream which contains a synchronisation pattern, and in which at the exchange the detection of the said synchronisation pattern from the calling terminal indicates that that terminal is in synchronism with the exchange, with detection causes a proceed to send signal (hereinafter called a PTS signai) to be sent to the calling terminal as an instruction for the transmission therefrom of wanted terminal number or other signals.

Thus the quiescent condition of the terminals is with each such terminal awaiting the reception of signals from the exchange, which signals establish initial synchronisation.

There are two main approaches to the achievement of synchronisation using the above technique. In the first of these the operational sequence when a call is originated from a terminal is as follows: (a) an unsynchronised stream of signals is sent at the line rate (assumed to be 80 Kbits/sec.) to the exchange to form the wake-up signal.

(b) in response to the reception of this bit stream the exchange sends back a synchronised pattern, also at the line rate.

(c) on reception of the synchronised pattern from the exchange the terminal locks to that pattern and then sends a synchronised pattern to the exchange to "tell" it that it has locked (d) the exchange responds to the reception thereat of the synchronised pattern by changing from the high-rate synchronisation pattern to synchronising check code sent at 2 Kb/s in bit 9 of the ten-bit code words.

(e) when the terminal detects this lower rate synchronisation check pattern it also changes from the high rate and sends to the exchange a synchronisation check pattern at 2 Kb/s in bit 9.

(f) the exchange now sends a proceed to send (PTS) signal so that the subscriber at the calling terminal can now send the wanted number.

With such an arrangement, frame synchronisation can be achieved in, say, 8 bits of "wake-up" plus one frame, with one additional frame for checking synchronisation, plus the recognition time for the reception of the check codes at 2 Kb/s. Thus we have: 8 bits at 80 Kb/s+2 frames at 125 ys/frame+1 byte sync. check at 2 Kb/s, i.e.: 8/80 ms+.5 ms+(8x0.5 ms)=4.6 ms.

If synchronisation is lost, the re-establishment process is the same as the initial set-up process, except that any other lines inputs would be inhibited so that the synchronisation signal may be detected readiLy.

The other approach uses only the 2 Kb/s bandwidth for establishing word synchronisation between the terminal and the exchange, and vice versa. The operational sequence in this case on initiation of a call from a terminal is as follows: (i) an unsynchronised stream of signals is sent, as the "wake-up" signal to the exchange.

(ii) the exchange responds to the wake-up signal by sending a synchronisation pattern at 2 Kb/s in bit 9, with all the remaining bits at zero, any other line inputs being inhibited.

(iii) the terminal identifies the synchronisation pattern since all bits other than those of the pattern are zero. When a true synchronisation 2 Kb/s pattern has been confirmed, the terminal, sends a similar pattern to the exchange.

(iv) when the exchange detects and confirms the synchronisation pattern sent back from the calling terminal it sends a proceed to send (PTS) signal to the terminal, on reception of which the terminal can send its wanted number or other signalling information.

If loss of synchronisation is detected, either at the exchange or at the terminal, then the data and signalling channels are clamped to zero, and only the 2 Kb/s synchronisation pattern in bit 9 is sent to the line. The terminal or exchange now attempts to find synchronisation, i.e. two synchronisation check frames. When synchronisation is achieved the terminal transmits the 2 Kb/s pattern in bit 9, with the remaining data and signalling channels set to zero.

Procedure is now as from (iv).

Frame synchronisation can be achieved in the same either bits of wake-up, plus two frames at 2 Kb/s, plus the PTS signal at 6 Kb/s. Thus we have 8 bits at 80 Kb/s+2 frames at 2 Kb/s+8 bits at 6 Kb/s, i.e.

8/80 ms+(16x0.5 ms)+(8x1/6) ms, i.e.

0.1 ms+8 ms+1.33 ms=9.43 ms.

Of these two approaches, the first involves the detection of a special byte at the line rate, while the second has the advantage of using the same method for synchronisation detection as for monitoring of synchronisation.

Synchronisation can be achieved at a slower rate by using the 2 Kb/s patterns in bit 9 as in the above method but the terminal or the exchange would have no indication of where the bit 9 is, and so would have a look for the synchronisation pattern in any of the bits 1 to 10. Although slower this has the advantage that on loss of synchronisation in one direction it is not necessary to close the other channel, since the end which lost synchronisation hunts for the correct synchronisation pattern in bit 9, and would not be inhibited by information in the bit stream on the other channel. This method, although somewhat simpler, would take much longer than the second method referred to above.

Embodiments of the invention will now be described with reference to the accompanying drawings, in which: Figs. 1 and 2 are schematic representations of a first embodiment of the invention based on the second method referred to above, with Fig. 1 showing the elements of the system at a subscriber's terminal and Fig. 2 showing the elements of the system at the exchange.

Figs. 3 and 4 are similar representations of a second embodiment of the invention, also based on the second method referred to above.

In the arrangement to be described with reference to Figs. 1 and 2, simple exchangeterminal connections are set up, while in that of Figs. 3 and 4, a multiplexer is inserted between the exchange and the terminals.

Fig. 1 shows the terminal directly connected to the exchange, and to conserve power there are no line signals in either direction When the exchange initiates a call, the flag or frame signal of 01111110 is sent in bit 9 at 2 Kb/s, the other bits all being at zero. The line signals are thus the repetitive frame signal at 2 Kb/s, and this is detected at the terminal which, in response, returns a similar signal so that the exchange may lock to those signals. The exchange detects the synchronisation check signal of the flags, and sends a PTS signal in the signalling channel. This causes an acknowledge signal to be returned by the terminal, so the circuit passes to the information phase.

when the terminal initiates a call, the idle line condition is replaced by a continuous series of zeros, which are detected at the exchange as a wake-up signal since previously there was no line signal. In response to the wake-up signal the exchange returns the synchronisation check signal of flags, and this is detected by the terminal, which responds by retumlng a similar check signal. On detection of this the exchange retums the PTS signal and receives the acknowledge from the terminals; The circuit then passes into the information phase.

When the call is cleared by signal exchange, the line returns to its idle condition with no signals.

Referring particularly to Fig. 2, we now discuss in more detail the operations which occur when the exchange initiates a connection. In connection with Fig. 2, it should be noted that pulse PM is the exchange master 2 Kb/s pulse, and that PM1 is a further signal delayed from PM by half of a uniperiod.

When the exchange seizes the line to a terminal, signal LS is received from the exchange's main control equipment: this causes the synchronisation check pattem generator ESCP to be driven to send to line the flag signal 01 1 1 1 1 10 art a rate of 2 Kb/s.Thisflag signal is marked into ESCP by the set of gates shown above ESCP in Fig. 2, the first and last of which sets the appropriate stage to 0 while the middle six gates set their stages to 1. Transmission to the line occurs under the control of the counter SDBF, which divides by 40, so as to derive the 2 K bit rate from the basic 80 K bit line bit rate.The line signal thus produced is controlled by the outputs from the gates connected to the "1" output of the pattern generator ESCP via which the output of ESCP reaches the lines signal sender, andby the exchange master clock via its pulse PM Through the hybrid these signals are combined on the twowire circuit which leads to the terminal We now refer to Fig. 1, which shows as much of the subscriber's terminal as is relevant to the invention. In this circuit the reception of the flag signals (01 1 1 1 1 10) is detected by the arrangement of the synchronisation check distributor TSCD and its associated circuits. A few points about this figure are worthy of mention before its operation is described. Thus the pulse generator locks to the pulses received from the exchange after synchronisation has been achieved. It free runs after the subscriber offhooks to initiate a call until this locking has been achieved. The next point to note Is that when synchronisation and signalling share the same channel, the . 40 counter TDBF may be augmented to permit synchronisation check for a flag of eight bits every 1/(mx40) th of 80 Kb/s.

For instance, m might be in the range of 4 to 32.

The other similar counters could be affected similarly. Note also that when the arrangement is in the wakeup condition, SO (at the exchange, Fig.

2) is energised to send all zeros.

In Fig. 1, the intelligence from the exchange is received via the hybrid and the line signal receiver, whose output RO and Ri apply the intelligence to the detection circuitry, and also to the terminal proper. The actuat deeerion Is effected by the synchronisation check distributor TSCD and the set of comparator gates controlled thereby and to which the RO-R1 outputs are applied. The actual detection indication is given by a bistable TSCS which is set to its 1 state at the end of a cycle of TSCD so that it is ready to be reset to O by any signal emerging from the abovementioned gates. These gates are controlled, in effect, by the inverse of the flag signal which is to be detected. Hence only if the true signal is received will the detector bistable TSCS not be reset to 0.Thus the output of TSCS remains at 1 at the end of the reception of the flag (01 1 1 1 1 10), and this drives a divide by two counter TCT. Thus on the second occasion on which the flag to be detected is correctly received, the synchronisation flip-flop IS is set to its 1 state, which, as will be seen, causes a synchronised bit pattern to be sent to the exchange. That is, it marks that pattern into the pattern gernator TSCP, and the contents thereof are then sent to the exchange under the control of the counter TDBF. This is similar to the operation of ESCP and EDBF in Fig. 2.

The detection is effected under control of a divide by 40 counter TDBF, needed as the synchronisation pattern's bit rate is one fortieth of the line bit rate, and a start bistable ST, which is triggered to its 1 state as soon as a 1 signal is detected by the line signal receiver. The transient output STR, which occurs when ST goes to 1, sets the counter TDBF to its 2 conditions, and also sets the check distributor TSCD to its 2 condition.

As long as flags (01 1 1 1 1 10) continue to be received, the detector bistable TSCS is always reset to zero before the end of the cycle. If a signal other than a flag is received, the detector TSCS is not restored to zero. Hence the divide-by-three counter TDBT clocks up those received signals, and when three have been received signals, and when three have been received it restores the "in sync" bistable IS to zero while at the same time restoring the start bistable ST to zero. The circuit is then in a condition in which it is looking for the synchronisation signal, and when two good synchronisation signals have been received the circuit is again switched to the "in sync" condition with bistable IS at 1.

The "in sync" condition causes the return of the synchronisation check signal, using the shift register TSCP, into which the appropriate pattern is marked via a set of gates by the transient output ISR, which occurred when IS was set to 1.

Note that due to the invertor INV, when the circuit is in the wake-up condition, see below, the SO input to the line signal sender is effective to cause "all zeros" to be sent. In the present case with IS at 1 , the clock pulses Ps and the output of the shift register TSCP controls that sender, in the case of TSCP via INV and SI and SO. Hence this output is passed via the hydrid to the line.

Information from the terminal, during sending, also controls S1 via the gate shown.

At the exchange, see Fig. 2, there is a similar check detector ESCS, controlled via a similar synchronisation detection distributor ESCD and its associated counters and gates. This detects that flag signals are being received, in the same way as described for Fig. 1. When the "in sync" condition is attained, with bistable IS (in Fig. 2) at 1, a signal is extended to the appropriate portion of the exchange to initiate the PTS signal. When that signal has been received by the terminal's signalling circuit, an acknowledge signal is returned and the system may then exchange information. Clearing of the circuit is achieved by the signalling system.

We now consider Fig. 1. When the subscriber lifts his handset, the pulse generator PG is switched on via the gate shown, since the "in sync" bistable IS is then in its 0 condition. PG therefore generates the Ps pulse train, which is free-running. At this time the line signal sender had its 0 output energised, but until the P8 pulse occurs, it was not sending. However, a series of zeros is now sent from the sender and via the hydrid as a wake-up signal to the exchange. As will be seen from Fig. 2, this causes the energisation of the wake-up bistable WU, due to the zero condition from the signal receiver at the exchange maturing with the pulse P, also obtained from the receiver.The transient output WUR sets the synchronisation check pattern shift register ESCP to its flag signal state, while setting the divide-by-40 counter EDBF to condition 2.

The 1 output of WU provides a drive condition for EDBF, which therefore produces 2 Kbits/sec.

synchronisation signals, and the pattern register ESCP is driven to give the flag output required.

Thus the line signals now carry the flag signal to the terminal, where it is detected as described above with reference to Fig. 1. This again causes the return of the flag pattern to the exchange (Fig.

2), where it is detected via ESCP and its associated circuitry. As before, the bistable IS is set to 1 to record the "in sync" condition, and hence initiate the PTS signal to which the terminal responds with an acknowledgement signal, whereafter the two ends can interchange information.

We now consider the situation in which multiplexers are interposed between the line terminals and the exchange. In this case a block of n line terminals are multiplexed on to a single ine to the exchange, where they are unmultiplexed to provide inputs to the exchange.

In the idle condition, there are no line signals from the subscribers' terminals, while the multiplex highway when idle carries zeros plus the synchronisation check signal inverted. On switchon the multiplexer at the exchange synchronises to the inverted synchronisation check signal, which is then sent on channel 1, with the other channels at 0. The other multiplexer returns a similar bit stream when it is synchronisation; the detection at the exchange of the return of this signal to the exchange causes the other channels to be opened.

As will be seen from Figs. 3 and 4, much of the operation is similar to that already described with reference to Figs. 1 and 2 as is indicated by the use of similar reference numerals. The only differences called for in the operation are those called for by the need to establish synchronisation between the two ends of the multiplex, prior to the terminal-exchange synchronisation. In Fig. 3 it will be seen that the upper half of the diagram relates to a line terminal, which is very similar to the line terminal of Fig. 1, while the lower half is that for the subscriber's end of the multiplex; the other half of the multiplex is similar.

As already indicated, determination of the synchronisation condition of the multiplex uses channel 1 ofthen-channel (usually 24 or 32 channels provided) multiplex, so that channel 1 can be used to convey intelligence in addition to the multiplex synchronisation control. This is achieved by the use of the inversion of the flag signal, i.e. 10000001, to initially achieve the multiplex synchronisation condition. Thus upon switch-on, the two ends of the multiplex system achieve synchronisation by looking for the synchronisation check signal 1 0000001, the rest of the bit stream being zeros. This inversion is maintained until channel 1 is taken into use, while in due course it changes to the true flag signal, but still maintains the multiplex synchronisation.

As before, when the exchange initiates a call it sends the non-inverted flat via the multiplex to extend the wanted line via the appropriate channel. Thus, as before, the terminal returns the flag signal as an acknowledgment to the exchange. Detection of this causes the PTS signal to be sent, and this is followed by the exchange of information.

When the terminal initiates the call, it does so by sending a free-running stream of zeros via the appropriate multiplex channel, this being the wake-up signal. The exchange returns the flag signal to the terminal, whereupon the latter (as usual) sends the flag to the exchange. Detection of this causes the PTS signal to be sent to the terminal, after which information exchange occurs. the return to the idle state after clearing the connection is effected by the signalling system. Note that a regular check can be performed on the multiplex synchronisation, using the flag in its true form, or in its inverted form, in channel 1.

Thus it will be seen that the line signals between the two parts of the multiplex system continue throughout the use of the system, whereas the signals between the line terminals and the multiplex are as described with reference to Figs. 1 and 2, i.e. no signals in either direction when idle. This also affects wake-up, which appears not at the exchange but at the multiplex terminal side. Otherwise the systems are closely similar.

From Figs. 3 and 4, it will be seen that the exchange side of the multiplex system is similar to the exchange terminal described with reference to Fig. 2, while the subscriber side of the system is almost the same as that of Fig. 1 except for the differences in respect of the wake-up signal. Fig. 4 in the main "mirrors" Fig. 2, but also includes the means to detect the inverted synchronisation signal. This is still based on the sychronisation check distributor ESCD, but with a second set of gates driven from ESCD, for the inverted flag detection. In addition the circuit includes receive and send stores and the multiplex control, but these are not described as they can follow established practice.A further difference is that the pattern shift register ESCP has two sets of gates to control it, the uppermost set for marking 01111110 in to ESCP, and the lower set to mark in 10000001.

Channels 2 ton of the multiplex system are similar to channel 1, but without the facilities for inverse marking into ESCP and without the elements MSCS, MCT, MDBT and IMS. MSCS, MDBT, MCT and IMS are similar to the combination of ESCS, EDBT, ECT and IS, butused for the multiplex synchronisation function.

In the preceding descn'ptlon,it will have been noted that the systems have been described using the "all zeros" condition to assist the detection of the "ones" of the flag signal. However, the alternative of using "all ones" to enable the first zero of the flag to be detected could be used. In certain cases this may be preferable to the "all zeros" method.

In the arrangements described above, the signalling channel used is separate from the channel used for synchronisation. However, it would be possible to use a repetitive synchronisation signal associated with the signalling conditions, so that the synchronisation signal might be repeated often enough to maintain the synchronisation check condition, while still providing a signalling capability. To achieve this an additional counter would be necessary to arrange for the required appearance of the flag signal so that it coccurs every x bytes of information, x lying typically in the range 5 to 32.

When the syncronisation is in effect embedded in a signalling channel, as just mentioned, a possible solution for the provision of digital subscriber's access is for a main channel of, for instance 64 Kb/s to be augmented by at least one additional signalling channel A. This can also provide for such other data as can be handled in a manner similar to signalling (S), being defined as telemetry signals (t) or supervision signals (d').

Thus the subscriber's access becomes as a minimum Mob,, M being speech or data (64 Kb/s) and A, being s+t+d' (8 Kb/s). In some cases more than one such A channel may be needed.

in such case, as before synchronisation is considered to be attained when two consecutive flags have been detected, whereafter normal conditions apply. When no signals are being sent, the channel is stuffed with flags so that each channel of 125 fts is given a check. The other conditions which have to be taken into account are the sending of (a) an acknowledgement, (b) a single character signal, and (c) a multi-character signal. With such signals, in view pf the need for them to include selection data, identification data and the actual message, the worst case for a synchronisation check becomes one flag in 31 ms. That is, the lengths of signalling messages may be such that the channel is reserved for signalli g for such a period.Hence provision is made for the detection of the absence of flags for some period longer than this, e.g. 62 ms. A synchronisation procedure is in such case initiated if a period of 62 ms elapses with no flag detected. Such a procedure is protected by a time out.

With the s+t+d' data handled as mentioned above, that traffic uses the same format. There may in some cases be a need for the t data to be stored for later recovery and the d' data to cause an alarm to be directed to the appropriate destination. This channel cannot connect data directly to various destinations as this would involve switching.

A further consideration to be born in mind is that the flag signal must have no meaning on the s+t+d' data.

Since the above arrangement has to allow for two cycles of the worst case of selection information plus identity transfer, the system must not detect the "out of frame synchronisation" condition until 62 frames have elapsed without a flag being recognised. Hence it is necessary to substitute a 63-way counter for the 3-way counters TDBT (Figs. 1 and 3) and EDBT (Figs. 2, 3 and 4). When any of these reaches 63, it resets IS and ST, or TST or EST to zero to introduce the resynchronisation cycle. The inputs to the three-way AND gates restoring ST, TST and EST should also be controlled by the 63 outputs of these counters.

Claims

1. An automatic telecommunication system in which an exchange serves a number of remote terminals with communication between the exchange and the terminals served being effected digitally, in which on initiation of a call at one of said terminals an unsynchronised signal (hereinafter called a wake-up signal) is sent from the calling terminal to the exchange, in which on reception of the wake-up signal the exchange sends back to the calling terminal a bit stream containing a synchronisation pattern, in which on detection of the synchronisation pattern in the bit stream which it receives from the exchange the calling terminal replaces the wake-up signal with a bit stream which contains a synchronisation pattern, and in which at the exchange the detection of the said synchronisation pattern from the calling terminal indicates that that terminal is in synchronism with the exchange, which detection causes a proceed to send signal (hereinafter called a PTS signal) to be sent to the calling terminal as an instruction for the transmission therefrom of a wanted terminal number or other signals.

2. A system as claimed in claim 1, in which said transmission of the syncronisation pattern is effected at the line bit rate, in which when the exchange detects the synchronisation pattern sent from the terminal it replaces that pattern being sent to the terminal with a relatively low bit-rate synchronisation check code sent in the nth bit of the digital words used for communication, and in which on reception of said low-bit rate check code the terminal replaces its transmission by such a low-bit rate check code, whereafter said PTS signal is sent from the exchange.

3. A system as claimed in claim 1, and in which all synchronisation is effected using the nth bits of the words used for said communication.

4. A system as claimed in claim 1, 2 or 3, and in which the detection of a said synchronisation check code either at the exchange or at a said terminal involves comparison with the inverse of the said check code.

5. A system as claimed in claim 1, 2 or 3, in which a number of said terminals are connected to a multiplexer which is connected via a line forming a multiplex highway to a further multiplexer at the exchange, and in which the prior to terminal synchronisation the multiplex system is synchronised, using as its synchronisation check code the inverse of the first-mentioned check code.

6. An automatic telecommunication system, substantially as described with reference to Figs.

1 and 2 or Figs. 3 and 4 of the accompanying drawings.