GB2079022A - Liquid crystal display devices - Google Patents

Abstract

A dyed cholesteric-nematic phase change reflective liquid crystal display cell is mounted on a silicon slice 1 providing an MOS active addressing matrix of FET gates via electrode drain pads 13 preferably made of substantially no- specularly reflecting deposited metal. The multiplex function is thus transferred to the gate and source electrodes, the FET's retaining memory of the required state of their associated elements for the whole of the subsequent scanning period. <IMAGE>

Description

1 1 GB2079022A 1

SPECIFICATION

Liquid crystal display devices This invention relates to liquid crystal display 70 devices in which the liquid crystal layer is bounded on one side by a semiconductive substrate.

One such type of display device has been described by M.N. Ernstaff et al, IEEE Interna tional Electronic Devices Meeting Technical Digest 73 CH 0781-5 ED (1978) 548, and in United States Patent No. 4,100,579. The liquid crystal electro-optic effect used in that instance was dynamic scattering. This has the disadvantage that it involves relatively high currents compared with devices using field effect electro-optic phenomena. A lower cur rent is particularly desired in any system in which display elements are addressed on a time sharing basis because it means that, in order to keep the voltage decay within given limits, the charge storage requirements are less for a given interval between successive addressings of an element.

According to the present invention there is provided a dyed cholesteric-nematic phase charge liquid crystal display cell which has a positive dielectric anistropy cholesteric liquid crystal layer incorporating a pleoichroic dye or dye mixture sandwiched between an upper transparent electroded plate and lower plate formed by, or carrying, a semiconductor layer provided with a matrix array of semiconductor gates connected with an overlying matrix ar ray of electrodes adjacent the liquid crystal layer, and wherein the nature of the two surfaces confining the liquid crystal layer is such as to promote a particular molecular alignment in the layer in the absence of an applied electric field.

To achieve a display of any significant com plexity it will normally be necessary for the display elements to be multiplexed, that is the elements must be matrix addressed and the electrical addressing signals must be time shared between the elements. Direct matrix addressing of the elements requires an elec tro-optic effect with a very sharp voltage threshold, and time sharing requires one with a fast 'on' time. The well known difficulties of directly multiplexing liquid crystal displays stem from their less ideal properties in respect of both these requirements. Compromises can be greatly eased if the drive to the liquid 120 crystal element is separated from the access ing function, and incorporates storage which maintains the liquid crystal drive to each ele ment between consecutive addressing pulses to that element. The requirement for the sharp threshold can then be transferred to the ac cess circuitry. This can be provided by arrang ing a highly non-linear circuit element in asso ciation with each cross-point in the matrix.

One of the currently most practical circuit elements for this application is in the field effect transistor. Suitable matrices of such devices can be made for instance using the technology of forming thin film transistors on glass substrates, of forming silicon based transistors on sapphire substrates, or of forming silicon transistors on standard single crystal silicon wafers. The last mentioned of these technologies is the one currently preferred by us because of its extensive usage in the semiconductor industry.

In each case a co-ordinate matrix of conductors arrayed in rows and columns can be provided on the substrate with at least one transistor of each cross-point. More than one may be provided to give redundancy. At each such cross-point the gate of the or each transistor associated with that cross-point is connected to one of the conductors defining that cross-point, the drain is connected to a large area electrically conductive pad, associated with that cross-point, and through which the liquid crystal is addressed. The liquid crystal layer is either in direct contact with these pads, or preferably is separated from them only by a thin electrically insulating layer provided to prevent the possibility of electrolytic degradation of the liquid crystal medium through exposure to a direct current flow for an extended period of time.

In this way it is possible for a large number of display elements to be addressed without the performance penalties usually associated with directly multiplexed liquid crystal dis- plays. This is because each display element is provided either with substantially the full drive voltage or zero drive voltage. Therefore, if the leakage can be ignored, the limitation of the number of display elements that can be ad- dressed is set by the semiconductor matrix, and the page write time is determined by the response of the liquid crystal to its full drive voltage. Therefore, such displays should retain the same viewing angle, termperature range, and contrast ratio as their non-multiplexed directly driven counterparts.

The chosen electro-optic effect for the display is the cholesteric nematic phase change, and this effect is used to provide a visual effect by making use of a guest-host interaction between the liquid crystal and a pleochroic dye. A particular advantage of this is that there is no need to use polarisers. This is an advantage partly becuase of the difficultly in providing a polarising layer directly on top of the silicon, and also because it avoids the inevitable light attenuation involved in the use of polarisers.

The silicon backing to the liquid crystal layer precludes its use as a transmission type device, and therefore some form of reflector is required to back the liquid crystal layer. This may be a conventional specular reflector provided for instance by a conventional evapo- rated metal layer for instance of aluminium or 2 GB2079022A 2 silver. A specular reflector does however pro- of polysilicon, and then standard photolitho vide certain restraints upon viewing angle and graphic techniques are used to delineate an illumination conditions in order to avoid troub- nular gate electrodes 4 and gate electrode lesome unwanted reflections. This problem is connection strips 5 in the polysilicon, after avoided by using a non-specular reflecting 70 which the remainder of the polysilicon is resurface. If a diffusing surface is employed, moved. The slice is now ready for the creation which approximates to a Lambertian diffuser, of the sources 6 and drains 7 of the FET's by a significant proportion of the light is lost implantation of an n-type dopant through the through the operation of the window effect. gate oxide 3. Alternatively the regions of gate This window effect arises because the scatter- 75 oxide exposed by the removal of the polysili ing surface is in direct contact with a relatively con are themselves removed. This is particu high refractive index medium, and hence any larly advantageous if the sources and drains light scattered into angles greater than the are made by diffusion instead of by implanta critical angle is unable directly to escape from tion. This implantation of diffusion also forms the display. A prefferred form of reflector is 80 channels 8 of n-type material which constitute therefore one that is non-specular, but which the column conductors, and further connec scatters light predominantly into a relatively tion channels 9 of n-type material linking small solid angle centred on the specular these column conductors 8 with the FET reflection direction. Such a reflector can be sources 6. Next the slice is covered with a prepared for instance by controlled evapora- 85 conventional phosphorus doped silica layer 10 tion of aluminium to provide a slow deposition deposited by chemical vapour reaction. Win rate typically af about 0.6 rim per second on dows 11 and 12 are opened in this layer to to a hot substrate typically at about 30WC so expose, respectively, a small central region of as to promote grain growth in the deposit. the drains 7, and the ends of the gate elec- The cholesteric-nematic phase change effect 90 trode connection strips 5. This is followed by requires the surfaces confining the liquid crys- a phosphorous diffusion which deepens the tal layer to be such as to promote, at the drain diffusion under the opening and reduces surfaces of the liquid crystal layer, a particluar leakage. Following this diffusion, a layer, (not molecular alignment of the liquid crystal moleseparately shown) of titanium typically 200 to cules in the absence of any applied field. This 95 300 nm thick is deposited by electron beam alignment may be homerotropic or parallel evaporation over the surface of the device, homogenous. Parallel homogenous, which and on this is deposited, also by electron produces the Grandjean state, is preferred beam evaporation, a layer of aluminium typi becuase it has been found that this provides a cally 1.8 to 30.0 microns thick. The titanium faster response time, and, though in transmis- 100 is provided to form a barrier between the sion type devices this can have some disad- alumunium and the underlying silicon. The vantage of providing an unwelcome textured aluminium, which provides a thicker metallisa effect on relaxation from the nematic back tion than is usual in FET manufacture, is into the cholesteric state, we have found that deposited at a higher temperature than usual, this textured effect is less noticeable in reflec- 105 about 32WC instead of 20WC, and is depos tion type displays, particularly when the ited at a slower rate than usual, about 0.6 rim reflector is in close proximity to the liquid per second instead of about 3nm per second.

crystal, and more particularly when the 'reflec- The slower rate and higher substrate tem tor' is of a non-specular type. perature used for this deposition produce a There follows a description of the construcdeposit with a white predominantly matt ap tion of a liquid crystal display device embody- pearance rather than a good quality specular ing the invention in a preferred form. The reflector. This is due to the conditions of description refers to the accompanying draw- desposition being such as to provide grain ing which is a diagrammatic part-sectioned growth which leaves a grainy surface with exploded perspective view of the device. 115 grain sizes in the range 0. 5 to 10 microns, The semiconductor gates for this device are but with little depth. The shallowness of grain field effect transistors provided on a single depth can be seen by examining a cleaved crystal slice of -silicon by standard co-planar coated substrate. Typically such a surface poly-silicon MOS n-channel technology. shows substantially no fissures extending to a A p-type silicon slice 1 is provided with 120 depth than 0.5 micron.

field oxide 2 by the conventional co-planar A comparison of this surface with a good nitride mask process. The masking provides quality specular reflector was made by direct apertures in the field oxide where the field ing the same beam of light in turn at normal effect transistors are to be formed, where incidence against the two surfaces. With the -- column electrodes are to be formed, and 125 specular reflector the reflected beam extended where connections are to made between the over a 10 cone, whereas, with the non FET sources and the column electrodes. After specular surface, the cone was found to ex removal of the masking material, the exposed tend over about 40. When the non-specular silicon is covered with a layer 3 of gate oxide. surface was wetted with a liquid having a Next the whole surface is covered with a layer 130 refractive index of about 1.5 neither the 9 1 If 3 GB 2 079 022A 3 spread nor the intensity of the scattered light was greatly changed. When the substrate temperature for deposition was changed from 320'C to 280'C a non-specular surface if similar properties was provided with a layer thickness of about 3 microns. A slower deposition rate in the region of 0. 4 nm per second produces little change in the properties, but increasing the deposition rate to around 1.0 nm per second appears to produce a rougher surface which in the dry state scatters light through a slightly wider angle, but when moistened its brightness is significantly reduced compared with layers deposited at 0.6 nrn per second.

It is believed that with silver similar topogra phy should be obtainable at faster rates and/ or lower substrate temperatures an account of the greater mobility of silver.

It will be apparent that this method of 85 producing an internal reflector having a white substantialy non-specularly reflecting appear ance finds application in liquid crystal cells other than those backed by a semiconductor layer and employing the dyed cholersteric nernatic phase change effect.

After the aluminium has been deposited, standard techniques of photolithography are used to etch tracks in the metallization to delineate a matrix array of electrode pads 13 with row conductors 14 between adjacent rows of pads. The row conductors 14 register with the windows 11 in the passivation layer 10 that expose the underlying gate electrode connection strips 5. In this way a direct connection is made between the row conduc tors and the gates of their respective FET's.

The electrode pads make contact with the FET drains via the windows 11.

The drawings shows the column electrodes 105 as registering with the gaps between the columns of electrode pads 13, but it has been found preferable in the case of diffused con ductors to arrange for them to be offset so that they are covered by pads 13 so that these conductors are protected from sensitivity to light incident upon the display.

In a modification of the above decribed sequence of processing steps, after the titanium layer is deposited. it is masked and etched away except for the areas covering and immediately surrounding the windows. Only then is the aluminium deposited. In this way the amount of titanium present in the com- pleted device is reduced, and this eases the problems involved in the final annealing of the fully processed slice in hydrogen.

It will be appreaciated that there are a number of alternatives to the just-described way of providing row and column connections respectively to the gate and source electrodes of the FET's. Thus for instance the column conductors could be fabricated in aluminium and the row conductors by the n-type chan- nels. Alternatively one or other of the sets of conductors could be fabricated in polysilicon. In general, particularly for large area displays involving a large number of electrode pads, it will be desirable to make at least one of the sets of conductors in aluminium so as to take advantage of its potentially lower resistivity per unit length and its lower capacitance.

After the slice has been annealed, it is covered with a silicon barrier layer (not shown) which provides electrical insulation between the electrode pads and the liquid crystal so as to preclude the possibility of electrolytic degradation of the liquid crystal. This layer, which is typically 0.1 micros thick, is then covered with a molecular aligment layer (not shown) for promoting aligment of the liquid crystal molecules in a preferred direction in the absence of an applied field. For achieving homeotropic alignment, a surfactant such as hexadecyl trimethyl ammonium bromide may be used, however parallel homogenous aligment is preferred, and this aligment is in this instance promoted by the deposition of an obliquely evaporated layer of silicon monoxide. No tilt angle is required, and hence the deposition can be performed by an angle of about 30' to the plane of the substrate.

The silicon slice is now ready to provide one of the confining surfaces for the liquid crystal layer. The other confining surface is constituted by a glass sheet 20 provided with a transpatent electrode layer 21. This transparent electrode layer is covered with a barrier layer (not shown) and a molecular aligment layer (not shown) in the same manner, and for the same reasons, as such layers were provided on the silocon slice. In the final assembly of the cell, in which the slice 1 is secured to the sheet 20, and the relative orientation of the melecular alignment directions is of no importance.

The next stage of manufacture concerns the assembly of the silicon slice 1 and the glass sheet 20 to form an enclosure for the liquid crystal. One way of achieving this is to bond the silicon slice on to a glass backing sheet (not shown), using for instance an adhesive such as a suitable epoxy resin. A thermoplas- tics ribbon (not shown) may then be deposited by screen printing around the perimeter of the silicon slice to form a perimeter seal and spacer for the assembly. After this has been applied the glass sheet 20 is placed in posi- tion against the silicon slice 1 with the electrode layer 21 facing the silicon, and the perimeter seal is made. A gap (not shown) in the perimeter seal forms an aperture bywhich the enclosure may be filled. Once the enclo- sure has been vacuum filled the aperture is sealed off with a suitable plug.

An alternative way of forming the required enclosure for the liquid crystal filling is to etch a well the size of the display area in one surface of a glass sheet. The electrode 21 and 4 GB2079022A 4 its covering layers are then formed at the bottom of the well which is of sufficient depth for the silicon slice to be bonded direct to the region of the glass sheet surrounding the 5 etched well.

A further alternative way of forming the enclosure involves forming the perimeter seal in polysilicon, and bonding this to an electroded flat glass sheet just like the sheet 20 of the Figure.

An example of a suitable liquid crystal filling comprises the positive dielectric anistropy nematic cyano-biphenyi eutectic mixture marketed by BDH under the designation E1 8, 1.8% of the anthraquinone blue dichroic dye marketed by BDH under the designation D '16, optionally about 0. 15% of the yellow isotropic dye Waxoline Yellow (to cancel out the residual colouration arising from the imperfections in the alignment of the dye molecules when homeotropically aligned throughout the liquid crystal layer thickness), and a suitable quantity of a cyano-biphenyl chiral additive sufficient to provide a cholesteric pitch typically in the range from being equal to the thickness of the layer to being equal to a fifth of that thickness. This layer thickness is typically between 10 and 12 microns. In the Figure the orientations of the liquid crystal molecules have been represented by the smaller bars 30 while those of the pleochroic dye molecules have been represented by the larger bars 31. The diagram illustrates the situation in which there is no potential between the electrode 21 and electrode pads 13 a, so that in these regions the liquid crystal is in the Grandjean state, the pleochroic dye molecules are aligned by their liquid crystal host in a variety of orientations, and therefore these regions appear coloured. A potential exists between the electrode 21 and electrode pads 1 3b of sufficient magnitude for the liquid crystal molecules in these regions of the layer to be caused to be homeotropically aligned. In these regions the pleochroic dye molecules are also homeotropically aligned by virtue of the guest-host interaction between the liquid crystal and the dye, and hence the dye shows no colour other than the residual amount arising from departures from perfect aligment. It is this residual colouration that is preferably cancelled out by adding to the filling an appropriate amont of an isotropic dye or dye mixture of complementary colour.

No such isotropic dye is required if, instead of a single pleochroic dye, the cell contains a mixture of such dyes whose colour and relative proportions are such as to provide a black colouration as is for instance described in the specification of our Published Patent Application Serial No. 2065158A.

A typical slice geometry has a 40 X 40 array of pads at 900 micron centres with 20 wide aluminium row conductors and 40 mi- crons between adjacent sides of adjacent pads. Clearly a larger slice can accommodate a larger array of pads, and also, if greater resolution is required, the pads can be made significantly smaller since they are very much larger in area than their underlying FETs.

The row and column conductors may be connected with individual terminal pads by which electrical connection with the cell may be made. It will be appreciated that this involves having to make a relatively large number of external electrical connections with the cell. Normally at least some of the data to be used for driving the cell will be provided in serial form and thus requires processing by serial-to-parallel conversion means in order to translate it into a suitable form for applying to the row and column conductors. This conversion means can conveniently be formed in the silicon slice, with the advantage that thereby the required number of extenal connections with the cell is reduced.

It is generally desirable to have as small a gap as possible between the picture element pads of the matrix array. When using a geom- etry providing 16 micron wide row conductors 14 and a gap 12 microns between the sides of those conductors and the nearer sides of the adjacent picture element pads 13 some problems were encountered in getting a good yield when using standard photolithogrphic technology to delineate the row conductors and the pads on the relatively thick granular layer of aluminium used to provide the required optical properties for the pads. The problems concerned the need to maintain a precise balance, avoiding on the one hand the pitfall of etching too much and so destroying the electrical continuity of one of the row conductor 14, and avoiding on the other hand the pitfall of underetching and so having a pad 13 directly connected with one of the row conductors 14.

It has been found that these problems can be avoided by separating the provision of the row conductors from the provision of the white non-specularly reflecting picture element pads by the use of two metallic layers in place of one. For this purpose the step of phosphoros diffusion to deepen the drain diffusion under the windows 11 is followed by the conventional deposition of a thin metallisation layer such as is normally used in high volume integrated circuit manufacture. This layer is typically of aluminium or aluminium silicon, and it is possible that the underlying titania barrier layer is in these circumstances necessary. Standard photolithography is used to etch this layer to produce the required row conductors and drain connection pads corre- sponding approximstely in area with the required picture element pads. (The optical reflection properties of these drain connectiont pads is of no consequence). The structure is then covered with a thin insulating layer, typically 500 to 1000 nm thick of silica or dg _k i I Ad GB2079022A 5 preferably of silicon nitride. Alternatively, a plastics layer such as a polyimide may be used. This is next covered with the white nonspecularly reflecting layer of granular alumin- ium which is then etched to delineate picture element pads but no row conductors. These pads are capacitatively coupled through the thin insulating layer with the corresponding drain connection pads underlying that layer.

Claims (29)

1. A dyed cholesteric-nematic phase change liquid crystal display cell which has a positive dielectric anistropy cholesteric liquid crystal layer incorporating a pleochroic dye or dye mixture sandwiched between an upper transparent electroded plate and a lower plate formed by or carrying a semiconductor layer provided with a matrix array of semiconductor gates connected with an overlying matrix array of electrodes adjacent the liquid crystal layer, and wherein the nature of the two surfaces confining the liquid crystal layer is such as to promote a particular molecular alignment in the layer in the absence of an applied electric field.

2. A cell as claimed in claim 1 wherein said nature of the two surfaces is such as to produce, in hte absence of an applied electrical field, molecular alignment of the liquid crystal layer in the Grandjean state.

3. A cell as claimed in claim 1 or 2 wherein the semiconductor layer is provided by a layer of silicon.

4. A cell as claimed in claim 1, 2 or 3 wherein the semiconductor layer is provided by a single crystal slice.

5. A cell as claimed in any preceding claim wherein the semiconductor gates are accessed by row and column indicators and wherein either the row conductors or the column conductors are formed in a semiconductr layer by channels of one conductivity type material bounded by material of the opposite conductivity type.

6. A cell as claimed in any preceding claim wherein the semiconductor gates are accessed by row and column conductors, and wherein either the row conductors or the column conductors, are formed in polysilicon deposited upon as electrically insulating layer covering the semiconductor layer.

7. A cell as claimed in any preceding claim wherein the semiconductor gates are accessed by row and column conductors, and wherein either the row conductors or the column conductors are formed in metal depos itied upon an electrically insulating layer cov ering the semiconductor layer.

8. A cell as claimed in any preceding 125 claim wherein each one of said matrix array of electrodes is acessed via two or more gates connected in parallel.

9. A cell as claimed in any preceding claim wherein the gates are provided by field effect transistors.

10. A cell as claimed in claim 9 wherein the field effect transistors are provided on a single crystal slice of silicon by co-planar polysilicon MOS technology.

11. A cell as claimed in any preceding claim wherein the semiconductor gates are accessed by row and column conductors which are electrically connected with individ- ual terminal pads by which external electrical connection with the cell may be made.

12. A cell as claimed in any preceding claims 1 to 10 wherein the semiconductor gates are accessed by row and column con- ductors at least some of which conductors are electrically connected with the output of serial to parallel conversdion means fabricated in the semiconductor layer.

13. A cell as claimed in any preceding claim wherein the matrix array of electrodes provide a reflecting background for the liquid crystal layer.

14. A cell as claimed in claim 13 wherein the matrix array of electrodes is provided by a metal layer whose exposed surface has a white substantially non- specularly reflecting appearance.

15. A cell as claimed in claim 14 wherein the matrix array of electrodes is provided by a metal layer deposited by evaporation in such a way as to promote grain growth to provide a grainy surface topography with grain sizes in the range 0. 5 to 10 microns extending to a depth substantially no greater than 0.5 mi- crons.

16. A cell as claimed in claim 15 wherein the members of the matrix array of electrodes are capacitatively coupled with the matrix array of semiconductor gates, the members of the matrix array of electrodes being capacitatively coupled through an electrically insulating layer with the members of a corresponding matrix array whose members are of pads in direct electrical connection with the corre- sponding members of the matrix array of gates, wherein the matrix array of pads is delineated by selective removal of material from an electrically conductive layer and wherein said selective removal of material from that electrically conductive layer is also used to delineate a set of row or column conductors by which the gates are accessed.

17. A cell as claimed in claim 13, 14, 15 or 16 wherein the matrix array of electrodes is made of aluminium.

18. A cell as claimed in claim 17 wherein the aluminium of the matrix array of electrodes is backed over at least a portion of their area by a layer of titanium preventing direct contact between the aluminium and the underlaying semiconductor.

19. A cell as claimed in claim 13, 14, 15 or 16 wherein the matrix array of electrodes is fabricated in silver.

20. A cell as claimed in any preceding 6 GB 2 079 022A 6 claim wherein the matrix array of electrodes is covered with an electrically insulating layer electrically isolating the array from direct cur rent contact with the liquid crystal layer.

21. A cell as claimed in claim 20 wherein the electrode or electrodes of the upper elec troded plate is covered with an electrically insulating layer electrically isolating the elec trode and electrodes of that plate from direct current with the liquid crystal layer.

22. A cell as claimed in any preceding claim wherein the liquid crystal layer incorporates with the pleochroic dye or dye mixture an isotropic dye or dye mixture of comple- mentary colour and in sufficient amount substantially to cancel the residual colouration shown by the pleochroic dye where the liquid crystal layer is held in the homeotropically aligned nematic state under the influence of an applied electric field across the thickness of the layer.

23. A dyed cholesteric-nematic phase change liquid crystal display cell substantially as hereinbefore described with reference to the accompanying drawing.

24. A liquid crystal display cell provided with an internal metal surface having a white substantially non-specularly reflecting appearance provided by deposition of a metal layer by evaporation in such a way as to promote grain growth to provide a graining surface topography with grain sizes in the range 0.5 to 10 microns extending to a depth substantially no greater than 0.5 microns.

25. A cell as claimed in claim 24 wherein the metal layer is made of aluminium-

26. A cell as claimed in claim 25 wherein the metal layer is made of silver.

27. A method of making a cell as claimed in claim 25 or 26 wherein the internal metal surface is deposited by electron beam evaporation at a controlled rate.

28. A method as claimed in claim 27 wherein the deposition by electron beam eva- poration is at a rate of substantially 0.6 nm per second.

29. A method as claimed in claim 27 wherein the deposition be electron beam evaporatin is by the method substantially as here- inbefore described.

Printed for Her Majesty's Stationery Office by Burgess & Son (Abingdon) Ltdl 982. Published at The Patent Office, 25 Southampton Buildings, London, WC2A 1AY, from which copies may be obtained.

tl :X 7 1 f i 1