GB2078421A

GB2078421A - Liquid crystal display device

Info

Publication number: GB2078421A
Application number: GB8020040A
Authority: GB
Original assignee: Standard Telephone and Cables PLC
Current assignee: STC PLC
Priority date: 1980-06-19
Filing date: 1980-06-19
Publication date: 1982-01-06
Also published as: JPS5727289A; GB2078421B; GB2079022A; GB2079022B

Abstract

In a dyed cholesteric nematic phase-change liquid crystal display cell a single crystal silicon slice 1 provides a MOS FET addressing matrix. Electrode pads 13 are preferably made of substantially non- specularly reflecting deposited metal, eg Al on Ti. Electrode 21 on glass 20, is transparent, and both 21 and 13 are insulated eg with SiO2 and carry liquid crystal alignment layers. <IMAGE>

Description

SPECIFICATION Liquid crystal display device This invention relates to liquid crystal display devices in which the liquid crystal layer is bounded on one side by a semiconductor substrate.

One such type of display device has been described by M. N. Ernstaff et al, IEEE Inter national Electronic Devices Meeting Technical Digest 73 CH 0781-5 ED (1973) 548, and in United States Patent No. 4,100,579. The liquid crystal electro-optic effect used in that instance was dynamic scattering. This has the disadvantage that it involves relatively high currents compared with devices using field effect electro-optic phenomena. A lower cur rent is particularly desired in any system in which display elements are addressed on a time sharing basis because it means that, in order to keep the voltage decay within given limits, the charge storage requirements are less for a given interval between successive addressings of an element.

According to the present invention there is provided a dyed cholesteric-nematic phase change liquid crystal display cell which has a positive dielectric anisotropy cholestric liquid crystal layer incorporating a pleochroic dye or dye mixture sandwiched between an upper transparent electroded plate and a lower plate formed by, or carrying, a semiconductor layer provided with a matrix array of semiconductor gates connected with an overlying matrix ar ray of electrodes adjacent the liquid crystal layer, and wherein the nature of the two surfaces confining the liquid crystal layer are such as to promote a particular molecular alignment in the layer in the absence of an applied electric field.

To achieve a display of any significant com plexity it will normally be necessary for the display elements to be multiplexed, that is the elements must be matrix addressed and the electrical addressing signals must be time shared between the elements. Direct matrix addressing of the elements requires an elec tro-optic effect with a very sharp voltage threshold, and time sharing requires one with a fast 'on' time. The well-known difficulties of directly multiplexing liquid crystal displays stem from their less than ideal properties in respect of both these requirements. Compro mises can be greatly eased if the drive to the liquid crystal element is separated from the accessing function and incorporates storage which maintains the liquid crystal drive to each element between consecutive addressing pulses to that element.The requirement for the sharp threshold can then be transferred to the access circuitry. This can be provided by arranging a highly non-linear circuit element by association with each cross-point in the matrix. One of the currently most practical circuit elements for this application is the field effect transistor. Suitable matrices of such devices can be made for instance using the technology of forming thin film transisitors on glass substrates, of forming silicon based transisitors on sapphire substrates, or of forming silicon transistors on standard single crystal silicon wafers. The last mentioned of these technologies is the one currently preferred by us because of its extensive usage in the semiconductor industry.

In each case a co-ordinate matrix of conductors arrayed in rows and columns can be provided on the substrate with at least one transistor at each cross-point. More than one may be provided to give redundancy. At each such cross-point the gate of the or each transistor associated with that cross-point is connected to one of the conductors defining that cross-point, the drain is connected to a large area electrically conductive pad, associated with that cross-point, and through which the liquid crystal is addressed. The liquid crystal layer is either in direct contact with these pads, or preferably is separated from them only by a thin electrically insulating layer provided to prevent the possibility of electrolytic degradation of the liquid crystal medium through exposure to a direct current flow for an extended period of time.

In this way it is possible for a large number of display elements to be addressed without the performance penalties usually associated with directly multiplexed liquid crystal displays. This is because each display element is provided either with substantially the full drive voltage or zero drive voltage. Therefore, if the effects of leakage can be ignored, the limitation of the number of display elements that can be addressed is set by the semiconductor matrix, and the page write time is determined by the response of the liquid crystal to its full drive voltage. Therefore such displays should retain the same viewing angle, temperature range, and contrast ratio as their non-multiplexed directly driven counterparts.

The chosen electro-optic effect for the display is the cholesteric nematic phase change, and this effect is used to provide a visual effect by making use of a guest-host interaction between the liquid crystal and a pleochroic dye. A particular advantage of this is that there is no need to use polarisers. This is an advantage partly because of the difficulty in providing a polarising layer directly on top of the silicon, and also because it avoids the inevitable light attenuation involved in the use of polarisers.

The silicon backing to the liquid crystal layer precludes its use as a transmission type device, and therefore some form of reflector is required to back the liquid crystal layer. This may be a conventional specular reflector provided for instance by a conventional evapo rated metal layer for instance of aluminium or silver. A specular reflector does however provide certain restraints upon viewing angle and illumination conditions in order to avoid troub lesome unwanted refiections. This problem is avoided by using a non-specular reflecting surface. If a diffusing surface is employed.

which approximates to a Lambertian diffuser, a significant proportion of the light is lost through the operation of the window effect.

This window effect arises because the scatter ing surface is in direct contact with a relatively high refractive index medium. and hence any light scattered into angles greater than the critical angle is unable directly to escape from the display. A preferred form of reflector is therefore one that is non-specular. but which scatters light predominately into a relatively small solid angle centred on the specular relection direction. Such a reflector can be prepared for instance by controlled evaporation of aluminium to provide a slow deposition rate typically of about 0.6 nm per second on to a hot substrate typically at about 3009C so as to promote grain growth in the deposit.

The cholesteric-nematic phase change effect requires the surfaces confining the liquid crystal layer to be such as to promote, at the surfaces of the liquid crystal layer, a particular molecular alignment of the liquid crystal molecules in the absence of any applied field. This alignment may be homeotropic or parallel homogeneous. Parallel homogeneous, which produces the Grandjean state, is preferred because it has been found that this provides a faster response time, and, though in transmission type devices this can have some disadvantage of providing an unwelcome textured effect on relaxation from the nematic back into the cholesteric state, we have found that this textured effect is less noticeable in reflection type displays, particularly when the reflector is in close proximity to the liquid crystal, and more particularly when the 'reflector' is of a non-specular type.

There follows a description of the construction of a liquid crystal display device embodying the invention in a preferred form. The description refers to the accompanying drawing which is a diagramatic part-sectioned exploded perspective view of the device.

The semiconductor gates for this device are field effect transistors provided on a single crystal slice of silicon by standard co-planar polysilicon MOS n-channel technology.

A p-type silicon slice 1 is provided with field oxide 2 by the conventional co-planar nitride mask process. The masking provides apertures in the field oxide where the field effect transistors are to be formed, where column electrodes are to be formed, and where connections are to be made between the FET sources and the column electrodes.

After removal of the masking material the exposed silicon is covered with a layer 3 of gate oxide. Next the whole surface is covered with a layer of polysilicon, and then standard photolithographic techniques are used to deli neate annular gate electrodes 4 and gate electrode connection strips 5 in the polysilicon, after which the remainder of the polysilicon is removed. The slice is now ready for the creation of the sources 6 and drains 7 of the FET's by implantation of an n-type dopant through the gate oxide 3. Alternatively the regions of gate oxide exposed by the removai of the polysilicon are themselves removed.

This is particularly advantageous if the sources and drains are made by diffusion instead of by implantation. This implantation of diffusion also forms channels 8 of n-type material which constitute the column conductors. and further connection channels 9 of ntype material linking these column conductors 8 with the FET sources 6. Next the slice is covered with a conventional phosphorus doped silica layer 1 0 deposited by chemical vapour reaction. Windows 11 and 1 2 are opened in this layer to expose respectively a small central region of the drains 7 and the ends of the gate electrode connection strips 5.

This is followed by a phosphorus diffusion which deepens the drain diffusion under the opening and reduces leakage. Following this diffusion, a layer (not separately shown) of titanium typically 200 to 300 nm thick is deposited by electron beam evaporation over the surface of the device, and on this is deposited, also by electron beam evaporation, a layer of aluminium typically 1.8 microns thick. The titanium is provided to form a barrier between the aluminium and the underlying silicon. The aluminium, which provides a thicker metallisation than is usual in FET manufacture, is deposited at a higher temperature than usual, about 320"C instead of 200"C, and is deposited at a slower rate than usual, about 0.6 nm per second instead of about 3 nm per second.

The slower rate and higher substrate temperature used for this deposition produce a deposit with a white predominately matt appearance rather than a good quality specular reflector. This is due to the conditions of deposition being such as to provide grain growth which leaves a grainy surface with grain sizes in the range 0.5 to 10 microns, but with little depth. The shallowness of grain depth can be seen by examining a cleaved coated substrate. Typically such a surface shows substantially no fissures extending to a depth greater than 0.5 micron.

A comparison of this surface with a good quality specular reflector was made by directing the same beam of light in turn at normal incidence against the two surfaces. With the specular reflector the reflected beam extended over a 10 cone, whereas, with the nonspecular surface, the cone was found to extend over about 40g. When the non-specular surface was wetted with a liquid having a refractive index of about 1.5 neither the spread nor the intensity of the scattered light were greatly changed. When the substrate temperature for deposition was changed from 320'C to 280"C a non-specular surface of similar properties was provided with a layer thickness of about 3 microns.A slower deposition rate in the region of 0.4 nm second produces little change in the properties, but increasing the deposition rate to around 1.0 nm per second appears to produce a rougher surface which in the dry state scatters light through a slightly wider angle, but when moistened its brightness is significantly reduced compared with layers deposited at 0.6 nm per second.

It is believed that with silver similar topography should be obtainable at faster rates and/or lower substrate temperatures an account of the greater mobility of silver.

It will be apparent that this method of producing an internal reflector having a white substantially non-specularly reflecting appearance finds application in liquid crystal cells other than those backed by a semiconductor layer and employing the dyed cholesteric nematic phase change effect.

After the aluminium has been deposited, standard techniques of photolithography are used to etch tracks in the metallization to delineate a matrix array of electrode pads 1 3 with row conductors 1 4 between adjacent rows of pads. The row conductors 1 4 register with the windows 11 in the passivation layer 10 that expose the underlying gate electrode connection strips 5. In this way a direct connection is made between the row conductors and the gates of their respective FET's.

The electrode pads make contact with the FET drains via the windows 11.

In a modification of the above described sequence of processing steps, after the titanium layer is deposited, it is masked and etched away except for the areas covering and immediately surrounding the windows. Only then is the aluminium deposited. In this way the amount of titanium present in the completed device is reduced, and this eases the problems involved in the final annealing of the fully processed slice in hydrogen.

It will be appreciated that there are a number of alternatives to the just-described way of providing row and column connections respectively to the gate and source electrodes of the FET's. Thus for instance the column conductors could be fabricated in aluminium and the two conductors by the n-type channels. Alternatively one or other of the sets of conductors could be fabricated in polysilicon In general.

particularly for large area displays involving a large number of electrode pads, it will be desirable to make at least one of the sets of conductors in aluminium so as to take advantage of its potentially lower resistivity per unit length and its lower capacitance.

After the slice has been annealed it is covered with a silica barrier layer (not shown) which provides electrical insulation between the electrode pads and the liquid crystal so as to preclude the possibility of electrolytic degradation of the liquid crystal. This layer, which is typically 0.1 microns thick, is then covered with a molecular alignment layer (not shown) for promoting alignment of the liquid crystal molecules in a preferred direction in the absence of an applied field. For achieving homeotropic alignment a surfactant such as hexadecyl trimethyl ammonium bromide may be used, however parallel homogeneous alignment is preferred, and this alignment is in this instance promoted by the deposition of an obliquely evaporated layer of silicon monoxide.No tilt angle is required, and hence the deposition can be performed at an angle of about 30 to the plane of the substrate.

The silicon slice is now ready to provide one of the confining surfaces for the liquid crystal layer. The other confining surface is constituted by a glass sheet 20 provided with a transparent electrode layer 21. This transparent electrode layer is covered with a barrier layer (not shown) and a molecular alignment layer (not shown) in the same manner, and for the same reasons, as such layers were provided on the silicon slice. In the final assembly of the cell, in which the slice 1 is secured to the sheet 20, the relative orientation of the molecular alignment directions is of no importance.

The next stage of manufacture concerns the assembly of the silicon slice 1 and the glass sheet 20 to form an enclosure for the liquid crystal. One way of achieving this is to bond the silicon slice on to a glass backing sheet (not shown), using for instance an adhesive such as a suitable epoxy resin. A thermoplastics ribbon (not shown) may then be deposited by screen printing around the perimeter of the silicon slice to form a perimeter seal and spacer for the assembly. After this has been applied the glass sheet 20 is placed in position against the silicon slice 1 with the electrode layer 21 facing the silicon, and the perimeter seal is made. A gap (not shown) in the perimeter seal forms an aperture by which the enclosure may be filled. Once the enclosure has been vacuum filled the aperture is sealed off with a suitable plug.

An alternative way of forming the required enclosure for the liquid crystal filling is to etch a well the size of the display area in one surface of a glass sheet. The electrode 21 and its covering layers are then formed at the bottom of the well which is of sufficient depth for the silicon slice to be bonded direct to the region of the glass sheet surrounding the etched well.

A further alternative way of forming the enclosure involves forming the perimeter seal in polysilicon, and bonding this to an electroded flat glass sheet just like the sheet 20 of the Figure.

An example of a suitable liquid crystal filling comprises the positive dielectric anisotropy nematic cyano-biphenyl eutectic mixture marketed by BDH under the designation El 8, 1.8% of the anthraquinone blue dichroic dye marketed by BDH under the designation D16, optionally about 0.15% of the yellow isotropic d.e Waxoline Yellow (to cancel out the residual colouration arising from imperfections in the alignment of the dye molecules when homeotropically aligned throughout the liquid crystal layer thickness), and a suitable quantity of a cyano-biphenyl chiral additive sufficient to provide a cholesteric pitch typically in the range from being equal to the thickness of the layer to being equal to a fifth of that thickness. This layer thickness is typically between 10 and 1 2 microns.In the Figure the orientations of the liquid crystal molecules have been represented by the smaller bars 30 while those of the pleochroic dye molecules have been represented by the larger bars 31.

The diagram illustrates the situation in which there is no potential between the electrode 21 and electrode pads 1 3a, so that in these regions the liquid crystal is in the Grandjean state, the pleochroic dye molecules are aligned by their liquid crystal host in a variety of orientations, and therefore these regions appear coloured. A potential exists between the electrode 21 and electrode pads 1 3b of sufficient magnitude for the liquid crystal molecules in these regions of the layer to be caused to be homeotropically aligned. In these regions the pleochroic dye molecules are also homeotropically aligned by virtue of the guest-host interaction between the liquid crystal and the dye, and hence the dye shows no colour other than the residual amount arising from departures from perfect alignment.It is this residual colouration that is preferably cancelled out by adding to the filling an appropriate amount of an isotropic dye or dye mixture of complementary colour.

No such isotropic dye is required if, instead of a single pleochroic dye, the cell contains a mixture of such dyes whose colour and relative proportions are such as to provide a black colouration as is for instance described in the specification of our Patent Application No.

7943075 (D. Coates-8).

A typical slice geometry has a 40 X 40 array of pads at 900 micron centres with 20 micron wide aluminium row conductors and 40 microns between adjacent sides of adjacent pads Clearly a larger slice can accommodate a larger array of pads, and also, if greater resolution is required, the pads can be made significantly smaller since they are very much larger in area than their underlying FET's.

The row and column conductors may be connected with individual terminal pads by which electrical connection with the cell may be made. It will be appreciated that this involves having to make a relatively large number of external electrical connections with the cell. Normally at least some of the data to be used for driving the cell will be provided in serial form and thus requires processing by serial-to-parallel conversion means in order to translate it into a suitable form for applying to the row and column conductors. This conversion means can conveniently be formed in the silicon slice with the advantage that thereby the required number of external connections with the cell is reduced.

Claims

1. A dyed cholesteric-nematic phase change liquid crystal display cell which has a positive dielectric anisotropy cholesteric liquid crystal layer incorporating a pleochroic dye or dye mixture sandwiched between an upper transparent electroded plate and a lower plate formed by or carrying a semiconductor layer provided with a matrix array of semiconductor gates connected with an overlying matrix array of electrodes adjacent the liquid crystal layer. and wherein the nature of the two surfaces confining the liquid crystal layer are such as to promote a particular molecular alignment in the layer in the absence of an applied electric field.

2. A cell as claimed in claim 1 wherein said nature of the two surfaces is such as to produce, in the absence of an applied electric field, molecular alignment of the liquid crystal layer in the Grandjean state.

3. A cell as claimed in claim 1 or 2 wherein the semiconductor layer is provided by a layer of silicon.

4. A cell as claimed in claim 1, 2 or 3 wherein the semiconductor layer is provided by a single crystal slice.

5. A cell as claimed in any preceding claim wherein the semiconductor gates are accessed by row and column conductors and wherein either the row conductors or the column conductors are formed in the semiconductor layer by channels of one conductivity type material bounded by material of the opposite conductivity type.

6. A cell as claimed in any preceding claim wherein the semiconductor gates are accessed by row and column conductors, and wherein either the row conductors or the column conductors are formed in polysilicon deposited upon an electrically insulating layer covering the semiconductor layer.

7. A cell as claimed in any preceding claim wherein the semiconductor gates are accessed by row and column conductors, and wherein either the row conductors or the column conductors are formed in metal deposited upon an electrically insulating layer covering the semiconductor layer.

8. A cell as claimed in any preceding claim wherein each one of said matrix array of electrodes is accessed via two or more gates connected in parallel.

9. A cell as claimed in any preceding claim wherein the gates are provided by field effect transistors.

10. A cell as claimed in claim 9 wherein the field effect transistors are provided on a single crystal slice of silicon by co-planar polysilicon MOS technology.

11. A cell as claimed in any preceding claim wherein the semiconductor gates are accessed by row and column conductors which are electrically connected with individual terminal pads by which external electrical connection with the cell may be made.

1 2. A cell as claimed in any claim of claims 1 to 10 wherein the semiconductor gates are accessed by row and column conductors at least some of which conductors are electrically connected with the output of serial to parallel conversion means fabricated in the semiconductor layer.

1 3. A cell as claimed in any preceding claim wherein the matrix array of electrodes provide a reflecting background for the liquid crystal layer.

14. A cell as claimed in claim 1 3 wherein the matrix array of electrodes is provided by a metal layer whose exposed surface has a white substantially non-specularly reflecting appearance.

1 5. A cell as claimed in claim 14 wherein the matrix array of electrodes is provided by a metal layer deposited by evaporation in such a way as to promote grain growth to provide a grainy surface topography with grain sizes in the range 0.5 to 10 microns extending to a depth substantially no greater than 0.5 microns.

16. A cell as claimed in claim 13, 14 or 1 5 wherein the matrix array of electrodes are made of aluminium.

1 7. A cell as claimed in claim 16 wherein the aluminium of the matrix array of electrodes is backed over at least a portion of their area by a layer of titanium preventing direct contact between the aluminium and the underlaying semiconductor.

18. A cell as claimed in claim 13, 14 or 1 5 wherein the matrix array of electrodes is fabricated in silver.

1 9. A cell as claimed in any preceding claim wherein the matrix array of electrodes is covered with an electrically insulating layer electrically isolating the array from direct current contact with the liquid crystal layer.

20. A cell as claimed in claim 1 9 wherein the electrode or electrodes of the upper electroded plate is covered with an electrically insulating layer electrically isolating the electrode and electrodes of that plate from direct current contact with the liquid crystal layer.

21. A cell as claimed in any preceding claim wherein the liquid crystal layer incorporates with the pleochroic dye or dye mixture an isotropic dye or dye mixture of complementary colour and in sufficient amount substantially to cancel the residual colouration shown by the pleochroic dye where the liquid crystal layer is held in the homeotropically aligned nematic state under the influence of an applied electric field across the thickness of the layer.

22. A dyed cholesteric-nematic phase change liquid crystal display cell substantially as hereinbefore described with reference to the accompanying drawing.

23. A liquid crystal display cell provided with an internal metal surface having a white substantially non-specularly reflecting appearance provided by deposition of a metal layer by evaporation in such a way as to promote grain growth to provide a graining surface topography with grain sizes in the range 0.5 to 10 microns extending to a depth substantially no greater than 0.5 microns.

24. A cell as claimed in claim 23 wherein the metal layer is made of aluminium.

25. A cell as claimed in claim 24 wherein the metal layer is made of silver.

26. A method of making a cell as claimed in claim 23, 24 or 25 wherein the internal metal surface is deposited by electron beam evaporation at a controlled rate.

27. A method as claimed in claim 26 wherein the deposition by electron beam evaporation is at a rate of substantially 0.6 nm per second.

28. A method as claimed in claim 26 wherein the deposition be electron beam evaporation is by the method substantially as hereinbefore described.

CLAIMS (13 Jan 1981)

1. A dyed cholesteric-nematic phase change liquid crystal display cell which has a positive dielectric anisotropy cholesteric liquid crystal layer incorporating a pleochroic dye or dye mixture sandwiched between an upper transparent electroded plate and a lower plate formed by or carrying a single crystal semiconductor layer provided with a matrix array of semiconductor gates connected with an overlying matrix array of electrodes adjacent the liquid crystal layer, and wherein the nature of the two surfaces confining the liquid crystal layer are such as to promote a particular molecular alignment in the layer in the absence of an applied electric field.