GB2079020A - Method of generating input signals for subtractive combination - Google Patents

Method of generating input signals for subtractive combination Download PDF

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Publication number
GB2079020A
GB2079020A GB8017718A GB8017718A GB2079020A GB 2079020 A GB2079020 A GB 2079020A GB 8017718 A GB8017718 A GB 8017718A GB 8017718 A GB8017718 A GB 8017718A GB 2079020 A GB2079020 A GB 2079020A
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GB
United Kingdom
Prior art keywords
voltage
sequence
input signals
signals
rails
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GB8017718A
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GB2079020B (en
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Hughes Microelectronics Ltd
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Hughes Microelectronics Ltd
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Publication date
Application filed by Hughes Microelectronics Ltd filed Critical Hughes Microelectronics Ltd
Priority to GB8017718A priority Critical patent/GB2079020B/en
Priority to JP7876781A priority patent/JPS5720787A/en
Publication of GB2079020A publication Critical patent/GB2079020A/en
Application granted granted Critical
Publication of GB2079020B publication Critical patent/GB2079020B/en
Expired legal-status Critical Current

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Classifications

    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/04Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of a single character by selection from a plurality of characters, or by composing the character by combination of individual elements, e.g. segments using a combination of such display devices for composing words, rows or the like, in a frame with fixed character positions
    • G09G3/16Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of a single character by selection from a plurality of characters, or by composing the character by combination of individual elements, e.g. segments using a combination of such display devices for composing words, rows or the like, in a frame with fixed character positions by control of light from an independent source
    • G09G3/18Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of a single character by selection from a plurality of characters, or by composing the character by combination of individual elements, e.g. segments using a combination of such display devices for composing words, rows or the like, in a frame with fixed character positions by control of light from an independent source using liquid crystals
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611Control of matrices with row and column drivers
    • G09G3/3696Generation of voltages supplied to electrode drivers

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal (AREA)

Abstract

In a method of generating input signals for subtractive combination in a circuit such as a multiplexed liquid crystal driver circuit, the respective signals to the substrate (S) and back plate (BP) electrodes have voltage levels representing the logic states Son, Soff, BPon, BPoff taken from the rails or tappings of a voltage divider typically formed from substantially equal resistors R1, R2, R3. The signals comprise two alternate parts produced by switching over, e.g. by MOS drivers, the supply to the voltage rails A, B of the voltage divider, thus ensuring minimal DC component in the subtractively combined output voltages S-BP, in spite of any mismatch in the resistors. <IMAGE>

Description

SPECIFICATION Method of generating input signals for subtractive combination The present invention relates to a method of generating input signals for subtractive combination in pairs in an electronic circuit, in particular a muitiplexing LCD (liquid Crystal Display) driver circuit.
In various electronic circuits a voltage is produced by the subtractive combination of two input signals. It is sometimes a requirement that the voltage should be an alternating voltage with no overall DC component and the voltage levels of the input signals are arranged to give this. However, these voltage levels are usually generated from a resistive voltage divider connected between fixed voltage rails and any variation in the resistance values, such as can easily occur with diffused resistors, will cause an error in the voltage levels which can lead to an overall DC component in the alternating voltage.
This problem is particularly acute in the driving of Liquid Crystal displays (LCDs) where DC component across the LCD plates reduces the life of the LCD, and where such LCDs are driven by multiplexing circuits in which two sets of signals are subtractively combined to give the drive voltages.
According to the present invention there is provided a method of generating input signals for subtractive combinations in pairs in an electronic circuit, each input signal comprising a first sequence of voltage levels followed by a second sequence of voltage levels each sequence represent the same sequence of logic states and each voltage level of each input being taken from a respective tapping on the same voltage divider connected between two voltage rails, wherein each tapping determines both the voltage level in the first sequence and that in the second sequence representing a given logic state, the voltages on the two voltage rails being switched over after the first sequence.
A method of generating input signals according to the present invention will now be described by way of example and with reference to the accompanying drawings in which Figure 1 shows a known resistor network for generating a pair of input signals for subtractive combination, Figure 2 shows a resistor network for generating a pair of signals according to the present invention for subtractive combination; Figure 3 shows two signals generated by the network of Figs. 1 and 2 and the voltages resulting from their subtractive combination.
Referring to Fig. 1, there is shown a voltage divider 1 comprising three equal resistors in series connected between voltage rails carrying voltages of + V and 0 respectively. Tapp ings on this voltage divider provide voltage levels for a pair of input signals 'S" and "BP" These input signals are to be applied to input terminals on a multiplexed LCD driver circuit one signal determining whether a parti cular segment of each of the liquid crystal units in the display is to have its electrode on or off (signal "S") and the other determining whether a particular unit in the display is to have its backplane electrode on or off (signal "BP"). The voltage levels for S on, S off BP on and BP off are taken from the tappings as shown in Fig. 1 and are selected by suitable gates operated by logic signals, which gives a sequence of voltage levels representing a cer tain sequence of on/off logic states for each input signal. The driver circuit substactively combines the two input signals in order to produce an output voltage which is large enough to activate the particular segment of the particular unit of the LCD only when both input signals are "on". In this example the subtractive combination of (S-BP) will give + y V in all cases except for Son-BP on which gives + V. This is a conventional V/3 multiplex arrangement and is commonly used in the driving of LCDs.
LCD units are driven by alternating voltages since any direct voltage across the electrodes damages the units and limits their life. This alternating voltage is obtained by having input signals as shown in Fig. 3. Each signal com prises a first sequence of voltage levels S or BP, generated as described above, followed by a second sequence of voltage levels S or 1MP. The second sequence of voltage levels represents the same sequence of on/off logic states as the first sequence but the voltage levels are chosen to ensure that g-BP for any pair of logic states is always equal and oppo site to S-BP, thus giving an alternating volt age for the subtractive combination. in Fig. 3 a sequence of three on/off logic state is shown for each signal.
In the conventional network shown in Fig. 1 the voltage levels for S on, S off, BP on and BP off are taken from the tappings as shown and a switching arrangement is needed to apply each of these voltage levels during the second sequence to the same logic operated gate as the corresponding one of the voltage levels S on, S off, BP on and BP off was applied during the first sequence. However, the resistors in the voltage divider 1 are usually laid down on a substrate by diffusion techniques which are not precise enough to ensure that the resistors have equal values.
Any errors in these resistor values will pro duce overall DC components in the alternating voltage applied to the LCD and reduce its life.
In Fig. 2 is shown a voltage divider 2 comprising three resistors in series connected between voltage rails carrying voltages of A and B respectively. As in Fig. 1 the divider has voltage taps providing voltage levels for the input signals S and BP and for the input signal S and BP. However, in this case the voltage taps are the same for S and S and for BP and BP, the voltage levels being changed by changing the voltages on the voltage rails.
The input signals S and BP are produced by having B as voltage Vand A as zero voltage, and the input signals S and BP are produced by having B as zero voltage and A as voltage V, i.e. by switching the voltage over. The voltage tappings are directly connected to the logi operated gates so that the complex switching arrangement of the conventional network is not needed.
It the diffused resistors in Fig. 2 are not precisely equal then the tappings will have different voltages from those shown in the graphs. If S offls a voltage xand BP off is a voltage y then S off will be a voltage V - x and BP off will be a voltage V - y. This can be seen in that S off must be the voltage across resistor R3 and S off is the voltage across resistors R1 and R2 due to the switching of the voltage rails and this must be the full voltage V minus the voltage across R3 i.e.
V-x.
Thus the voltage levels in the signals S and BP are the negative of the corresponding voltage levels in the signals S and BP, with a constant voltage V added on. When the two signals are subtractively combined this constant voltage V is cancelled out leaving only the negative voltages. This means that the output voltage is a true alternating voltage whatever the values of the voltages x and y.
The above description deals with application of the inventive method to a V/3 multiplexed driver circuit for an LCD, but it could equally be applied to any multiplexing circuit using subtractive combination and requiring a true alternating voltage output or to any other simple subtractive circuit such as might be used to provide biasing in a linear circuit design. It is particularly applicable to integrated circuits where resistor values are difficult to establish accurately.
The switching of the voltage rails A and B can be simply achieved by MOS drivers of impedance substantially lower than the resistance of the diffused resistors, to ensure a negligible drop in voltage across the drivers.

Claims (6)

1. A method of generating input signals for subtractive combination in pairs in an electronic circuit, each input signal comprising a first sequence of voltage levels followed by a second sequence of voltage levels each sequence representing the same sequence of logic states and each voltage level of each signal being taken from a respective tapping on the same voltage divider connected between two voltage rails, wherein each tapping determines both the voltage level in the first sequence and that in the second sequence representing a given logic state, the voltages on the two voltage rails being switched over after the first sequence.
2. A method according to claim 1, where in the input signals consist of two sets of input signals, and pairs of signals comprising one from each set of signals are subtractively : combined in the electronic circuit.
3. A method according to claim 2, wherein each input signal has two possible logic states.
4. A method according to claim 3, wherein the voltage divider comprises three substantially equal resistive elements in series and each logic state of each set of input signals is represented by a different voltage level in the first sequence of voltage levels.
5. A method of generating input signals for subtractive combination substantially as herein described with reference to and as illustrated by Figs. 2 and 3 of the accompanying drawings.
6. A circuit for generating signals by the method claimed in any preceding claim comprising a voltage source connected through switching means to a pair of voltage rails between which is connected a voltage divider having voltage tappings at fixed positions on the divider, the switching means being capable of switching over the voltages on the two voltage rails.
GB8017718A 1980-05-30 1980-05-30 Method of generating input signals for subtractive combination Expired GB2079020B (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
GB8017718A GB2079020B (en) 1980-05-30 1980-05-30 Method of generating input signals for subtractive combination
JP7876781A JPS5720787A (en) 1980-05-30 1981-05-26 Method of generating input signal for subtraction combination

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB8017718A GB2079020B (en) 1980-05-30 1980-05-30 Method of generating input signals for subtractive combination

Publications (2)

Publication Number Publication Date
GB2079020A true GB2079020A (en) 1982-01-13
GB2079020B GB2079020B (en) 1983-12-21

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Application Number Title Priority Date Filing Date
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Country Status (2)

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JP (1) JPS5720787A (en)
GB (1) GB2079020B (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2551245A1 (en) * 1983-08-25 1985-03-01 Sfena METHOD AND DEVICE FOR DISPLAYING SYMBOLS USING A LIQUID CRYSTAL MATRIX
EP0171202A2 (en) * 1984-08-02 1986-02-12 Standard Telephones And Cables Public Limited Company Thermal imager

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SE8400302L (en) * 1984-01-20 1985-08-18 Munters Ab Carl Contact body

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2551245A1 (en) * 1983-08-25 1985-03-01 Sfena METHOD AND DEVICE FOR DISPLAYING SYMBOLS USING A LIQUID CRYSTAL MATRIX
EP0142385A1 (en) * 1983-08-25 1985-05-22 Societe Francaise D'equipements Pour La Navigation Aerienne (S.F.E.N.A.) Method and device for displaying symbols on a liquid-crystal matrix display
EP0171202A2 (en) * 1984-08-02 1986-02-12 Standard Telephones And Cables Public Limited Company Thermal imager
EP0171202A3 (en) * 1984-08-02 1986-12-30 Standard Telephones And Cables Public Limited Company Thermal imager

Also Published As

Publication number Publication date
GB2079020B (en) 1983-12-21
JPS5720787A (en) 1982-02-03

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PCNP Patent ceased through non-payment of renewal fee