JP2005025179A - Driving circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve such a problem as to cause a period when an output terminal of a driver and a common power source are short-circuited. <P>SOLUTION: A source driving circuit 10 for driving source line groups S<SB>1</SB>-S<SB>m</SB>of a liquid crystal display is provided with source driver groups SD<SB>1</SB>-SD<SB>m</SB>that output a drive signal, an analog switch group B that connects the output terminal of the source driver groups to the source line group and separates the same from the source line group, an analog switch group A that connects the source line group to a common power source and separates the same from the common power source and a switch control circuit 100 that controls switch operation of the analog switch group A and the analog switch group B. The switch control circuit 100 detects that all analog switches of the analog switch group B are turned off, then, turns the analog switch group A on, and detects that all analog switches of the analog switch group B are turned off and, then, turns the analog switch group B on. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

The present invention relates to a drive circuit (a source drive circuit, a gate drive circuit, etc.) for driving a matrix line group (a gate line group, a source line group, etc.) arranged on a liquid crystal panel of a liquid crystal device (liquid crystal display).

In the conventional driving circuit, in one-dot inversion driving or multi-dot inversion driving, the source line (matrix line) is separated from the driver output terminal of the driving circuit and another source separated from the common power supply or driver output terminal. Some have realized high-speed driving by a precharge operation for short-circuiting to a line (for example, see Patent Document 1).

  FIG. 14 is a block diagram of such a conventional liquid crystal display. This conventional liquid crystal display includes a liquid crystal panel 1, a gate driving circuit 2, a source driving circuit 3, a source line group (m source lines S1 to Sm), and a gate line group (n gate lines G1 to G1). Gn).

  FIG. 15 is a circuit configuration diagram of a conventional source driving circuit 3. As shown in FIGS. 14 and 15, the conventional source drive circuit 3 includes a source driver group (m source lines SD1 to SDm), an analog switch group A (m analog switches A1 to Am), and an analog driver group. A switch group B (m analog switches B1 to Bm) and an inverter I are provided.

  In this conventional source drive circuit 3, when the input signal PC is "0" and the output signal PCB of the inverter I is "1", the analog switch group A is OFF and the analog switch group B is ON. The output terminals OUT1 to OUTm (source lines S1 to Sm) of the source driving circuit 3 are connected to the outputs of the source drivers SD1 to SDm, respectively, and the output signals of the source drivers SD1 to SDm are output to the source lines S1 to Sm, respectively.

  When the input signal PC becomes “1” and the output signal PCB of the inverter I becomes “0”, the analog switch group A is turned on, the analog switch group B is turned off, and the output terminal OUT1 of the source drive circuit 3 is turned on. ˜OUTm (source lines S1 to Sm) are disconnected from the outputs of the source drivers SD1 to SDm, shorted to the common power supply Vcom, and precharged.

When the input signal PC returns to “0” and the output signal PCB of the inverter I returns to “1”, the analog switch group A is turned off, the analog switch group B is turned on, and the output terminal of the source drive circuit 3 OUT1 to OUTm (source lines S1 to Sm) are disconnected from the common power supply Vcom and connected to the outputs of the source drivers SD1 to SDm, respectively.
Japanese Patent Laid-Open No. 11-30975

  However, in the above conventional liquid crystal drive circuit, two analog switch groups are controlled by the same input signal PC, so that the switching timing of both analog switch groups is delayed due to the analog switch capacitance, wiring capacitance, etc. The analog switch of the other analog switch group may be turned on before the analog switch of the other analog switch group is completely turned off.

In such a case, the matrix line is short-circuited to the common power supply before being disconnected from the driver output terminal. In such a case, the matrix line is connected to the output terminal of the driver before being disconnected from the common power source.
This causes a period in which the output terminal of the driver and the common power supply are short-circuited. As a result, there is a problem that overcurrent flows and the original effect of the precharge operation cannot be obtained. Also,
The present invention has been made to solve such a conventional problem, and an object of the present invention is to provide a driving circuit and a driving method capable of preventing an overcurrent during precharging.

The present invention has been made to solve the above-described problems, and typical ones are as follows. That is, the drive circuit of the present invention is a drive circuit that drives a matrix line group of a liquid crystal device,
A group of drivers that output drive signals;
A first switch group having a conductive state for connecting between the output of the driver group and the matrix line group and a non-conductive state for disconnecting;
A second switch group having a conductive state for connecting between the matrix line group and the precharge power source and a non-conductive state for disconnecting;
Switch control means for controlling the switch operation of the first switch group and the second switch group,
The switch control means sets the second switch group to a conductive state after detecting that all the switches of the first switch group are in a non-conductive state, and sets all the second switch groups to a conductive state. The first switch group is set to a conductive state after detecting that the switch is turned off.

  According to the present invention, it is possible to reliably prevent the first switch group and the second switch group from being simultaneously turned on. Therefore, there is an effect that liquid crystal driving with high speed and low power consumption can be realized.

  Example 1 is shown below.

FIG. 1 is a configuration diagram of a liquid crystal display according to Embodiment 1 of the present invention, and the same components as those in FIG. 14 are denoted by the same reference numerals. The liquid crystal display according to the first embodiment includes a liquid crystal panel 1, a gate driving circuit 2, a source driving circuit 10 according to the first embodiment, a source line group, and a gate line group.
[Matrix line group]
The source line group is composed of m source lines S1, S2,..., Sm (m is an arbitrary integer of 2 or more), and the gate line group is n (n is an arbitrary integer of 2 or more). ) The gate lines G1, G2,..., Gn. These source line group and gate line group constitute a matrix line group for driving switch transistors of m × n liquid crystal cells arranged in a matrix.

[LCD panel 1]
The liquid crystal panel 1 includes mxn switch transistors TR11, TR21, ..., TRm1, TR12, TR22, ..., TRm2, ..., TR1n, TR2n,. , ..., CXm1, CX12, CX22, ..., CXm2, ..., CX1n, CX2n, ..., CXmn. The switch transistor TRij (i is any integer from 1 to m, j is any integer from 1 to n) and the liquid crystal cell capacitor CXij constitute one liquid crystal cell. In the liquid crystal panel 1, these m × n liquid crystal cells are arranged in a matrix.

  The source and drain of the switch transistor TRij are connected between the source line Si and the cell electrode of the liquid crystal cell capacitor CXij, and the gate of the switch transistor TRij is connected to the gate line Gj. The common electrode of the liquid crystal cell capacitor CXij is connected to the common power supply Vcom.

[Gate drive circuit 2]
The gate drive circuit 2 includes n gate drivers GD1, GD2,. The gate driving circuit 2 drives the gate line Gj of the gate line group by a gate driver GDj.

  FIG. 2 is a circuit configuration diagram of the source drive circuit 10 according to the first embodiment. Components similar to those in FIG. 15 are denoted by the same reference numerals.

[Source Drive Circuit 10]
As shown in FIGS. 1 and 2, the source drive circuit 10 according to the first embodiment includes a source driver group, an analog switch group A, an analog switch group B, and a switch control circuit 100. FIG. 17 shows a layout diagram on the chip of the analog switch group A, the analog switch group B, the switch control circuit 100, signal lines Line A and Line A ′, and signal lines Line B and Line B ′ described later. The source drive circuit 10 is formed on a semiconductor chip. In general, there are several tens to hundreds of output terminals of the source driver circuit, so that one pair of sides of the semiconductor chip on which the source driver circuit is formed is longer than the other pair of sides. Become.

[Source Driver Group]
The source driver group includes m source drivers SD1, SD2,. The source driver group drives the source line Si of the source line group by the source driver SDi.

[Analog switch group A]
The analog switch group A is configured by m analog switches (MOS switches) A1, A2,. The analog switch Ai is provided between the output terminal OUTi (source line Si) of the source driving circuit 10 and the common power supply Vcom (potential of the common electrode of the liquid crystal cell capacitor). The analog switch Ai shorts the output terminal OUTi (source line Si) to the common power supply Vcom or disconnects it from the common power supply Vcom according to the level of the signal supplied to the signal lines Line A and Line A ′. The position near the output terminal of the NOR gate N1 of the signal line Line A is shown as a, and the position near the input terminal of the NOR gate N2 of the signal line Line A is shown as a '. The signal line Line A extends in the direction in which the output terminal OUT is arranged, that is, in the long side direction of the chip. The position a is located on the left side of the chip, and the position a ′ is located on the right side of the chip. In the first embodiment, the precharge power source that short-circuits the output terminal (source line) of the source drive circuit for precharge is the common power source Vcom.

[Analog switch group B]
The analog switch group B is composed of m analog switches (MOS switches) B1, B2,. The analog switch Bi is provided between the output of the source driver SDi and the output terminal OUTi (source line Si) of the source driving circuit 10. This analog switch Bi is in accordance with the level of the signal supplied to the signal lines Line B and Line B ′.
The output terminal OUTi (source line Si) is connected to the output terminal of the source driver SDi or disconnected from the output terminal of the source driver SDi. The position near the input terminal of the NOR gate N1 of the signal line Line B is shown as b, and the position near the output terminal of the NOR gate N2 of the signal line Line B is shown as b '. The signal line Line B extends in the direction in which the output terminal OUT is arranged, that is, in the long side direction of the chip. The position b is located on the left side of the chip, and the position b ′ is located on the right side of the chip.

[Switch control circuit 100]
As shown in FIG. 2, the switch control circuit 100 includes NOR gates N1 and N2 and inverters I1, I2 and I3, and controls the switch operations of the analog switch groups A and B according to the input signal PC.
The input signal PC is input to the NOR gate N1 and the inverter I3, and the output of the inverter I3 is connected to the input of the NOR gate N1. This input signal PC is a control signal that triggers the switch operation of the analog switch groups A and B.
The output of the NOR gate N1 is connected to the input of the inverter I1, the input of the NOR gate N2, and the NMOS gates of the analog switches A1 to Am. The output of the inverter I1 is connected to the PMOS gates of the analog switches A1 to Am.
The output of the NOR gate N2 is connected to the input of the inverter I2, the input of the NOR gate N1, and the NMOS gates of the analog switches B1 to Bm. The output of the inverter I2 is connected to the PMOS gates of the analog switches B1 to Bm.

In the switch control circuit 100, the NOR gates N1 and N2 and the inverter I3 constitute a flip-flop circuit. In the analog switches A1 to Am of the analog switch group A, the signal appearing at the point a of the signal line Line A (output signal of the NOR gate N1) and the signal appearing at the point a ′ (input signal of the NOR gate N2) are “0”. All the signals are turned OFF when “a” (the output signal of the NOR gate N1) and the signal appearing at the point a ′ (the input signal of the NOR gate N2) are all “1”. Further, the analog switches B1 to Bm of the analog switch group B have a signal appearing at the point b ′ of the signal line Line B (output signal of the NOR gate N2) and a signal appearing at the point b (input signal of the NOR gate N1). All are turned off when "0", and all signals are turned on when the signal appearing at point b '(output signal of NOR gate N2) and the signal appearing at point b (input signal of NOR gate N1) are "1". Further, as shown in FIGS. 1 and 17, the switch control circuit 100 is arranged in two regions on the semiconductor chip. Specifically, a part 100L of the switch control circuit 100 including the NOR gate N1 and the inverter I3 is disposed in the peripheral region 100A on the left side of the semiconductor chip, and a part 100R of the switch control circuit 100 including the NOR gate N2 is The semiconductor chip is disposed in the peripheral region 100B on the right side of the semiconductor chip. Further, the signal line Line A and the signal line Line B that connect the NOR gate N1 and the NOR gate N2 extend on the central region between the peripheral region 100A and the peripheral region 100B. Therefore, as shown in FIG. 18, the signal line Line A has a resistance component and a wiring capacitance. Further, a parasitic capacitance is added between the point a of the signal line Line A and the point a ′ of the signal line Line A. Similarly, a resistance component and wiring capacitance exist in the signal line Line B. Further, a parasitic capacitance is added between the point b of the signal line Line B and the point b ′ of the signal line Line B. However, the switch control circuit 100 is divided into two regions with the analog switch group A and the analog switch group B interposed therebetween, and the length of the signal line Line A is equal to the length of the signal line Line B. The resistance value, wiring capacitance, and parasitic capacitance of the signal line Line A are set substantially equal to the resistance value, wiring capacitance, and parasitic capacitance of the signal line Line B.
[Operation of Embodiment 1]

  FIG. 3 is a timing chart in the one-dot inversion driving of the source driving circuit 10 according to the first embodiment of the present invention. 3, (1) is the output signal OUT of the source drive circuit 10 (OUTi (Si) in FIG. 2), (2) is the input signal PC, (3) is the signal PCB, and (4) is the signal line Line B. Waveforms at points b and b ′, (5) are waveforms at points a and a ′ of the signal line Line A. Td is a one-dot period of the liquid crystal display, and Tp is a precharge period.

  FIG. 4 is an enlarged view of the precharge period Tp in FIG. 4, (1) is an input signal PC, (2) is a signal PCB, (3) is a waveform at points b and b ′ of the signal line Line B, and (4) is a points and a of the signal line Line A. 'It is the waveform at the point.

  With reference to FIG. 3 and FIG. 4, the operation of the source drive circuit 10 of the first embodiment will be described below. In the following description, logic “0” is “L” level and logic “1” is “H” level.

[Driver output period]
In the driver output period, the input signal PC (input signal of the NOR gate N2 and the inverter I3) is “0”, and the signal PCB (input signal of the NOR gate N1 and output signal of the inverter I3) is “1”. Accordingly, the point a (output signal of the NOR gate N1) and the point a ′ (input signal of the NOR gate N2) are “0”, and the output signal of the inverter I1 is “1”, so the analog switch group A is turned off. The output terminals OUT1 to OUTm (source lines S1 to Sm) of the source drive circuit 10 are disconnected from the common power supply Vcom.
Further, since the point b ′ (output signal of the NOR gate N2) and the point b (input signal of the NOR gate N1) are “1” and the output signal of the inverter I2 is “0”, the analog switch group B is turned on. The output terminals OUT1 to OUTm (source lines S1 to Sm) of the source driving circuit 10 are respectively connected to the output terminals of the source drivers SD1 to SDm, and the output signals of the source drivers SD1 to SDm are output to the source lines S1 to Sm, respectively. Has been.

[Operation to switch from driver output period to precharge period]
Next, when the input signal PC becomes “1”, the point b ′ first becomes “0”, and the point b also becomes “0” with a delay due to the wiring capacity or the like (see FIGS. 4 (1) and (3)). Similarly, since the output signal of the inverter I2 is also “1”, the analog switch group B is turned OFF, and the output terminals OUT1 to OUTm (source lines S1 to Sm) of the source drive circuit 10 are the outputs of the source drivers SD1 to SDm. Each is disconnected from the terminal and becomes high impedance.

  Further, when the input signal PC becomes “1”, the signal PCB becomes “0” (see FIGS. 4 (1) and (2)). When the signal PCB is “0” and the point b becomes “0”, the point a first becomes “1”, and the signal a ′ point becomes “1” with a delay due to the wiring capacity or the like (FIG. 4 (3)). Similarly, since the output signal of the inverter I1 is also "0", the analog switch group A is turned on, and the output terminals OUT1 to OUTm (source lines S1 to Sm) of the source drive circuit 10 are common. Shorted to power supply Vcom.

  Here, when the point b becomes “0”, all the analog switch groups B are already OFF. As described above, in the switch control circuit 100, even if the signal PCB becomes “0”, if the point b does not become “0”, the point a does not become “1”. Unless the source line group is completely disconnected from the source driver group, the analog switch group A is not turned ON and the source line group is not short-circuited to the common power source Vcom. That is, the switch control circuit 100 indicates that the signal PCB is “0” (the input signal PC is “1”) and the point b is “0” (= the analog switch group B is all OFF). ) Is detected, the point a is set to “1”, and the analog switch group A is turned ON.

[Precharge period]
In the precharge period, the input signal PC (input signal of the NOR gate N2 and the inverter I3) is “1”, and the signal PCB (input signal of the NOR gate N1 and output signal of the inverter I3) is “0”. Therefore, the point b ′ (output signal of the NOR gate N2) and the point b (input signal of the NOR gate N1) are “0”, and the output signal of the inverter I2 is “1”. Therefore, the analog switch group B is turned off. The output terminals OUT1 to OUTm (source lines S1 to Sm) of the source drive circuit 10 are separated from the outputs of the source drivers SD1 to SDm, respectively.
Further, since the point a (output signal of the NOR gate N1) and the point a ′ (input signal of the NOR gate N2) are “1”, the analog switch group A is ON and the output terminals OUT1 to OUTm of the source drive circuit 10 are ON. (Source lines S1 to Sm) are short-circuited to the common power supply Vcom and precharged.

[Operation to switch from precharge period to driver output period]
Next, when the input signal PC becomes “0”, the signal PCB becomes “1” (see FIGS. 4A and 4B). When the signal PCB becomes “1”, the point “a” first becomes “0”, and the point a ′ also becomes “0” after a delay due to the wiring capacity or the like (see FIGS. 4 (2) and (4)). Since the output signal of I1 is also “1”, the analog switch group A is turned OFF, and the output terminals OUT1 to OUTm (source lines S1 to Sm) of the source drive circuit 10 are disconnected from the common power supply Vcom and become high impedance. .

  Further, when the signal PC is “0” and the point a ′ becomes “0”, the point b ′ first becomes “1”, and the point b also becomes “1” with a delay due to the wiring capacity or the like (FIG. 4). Similarly, since the output signal of the inverter I2 is also “0”, the analog switch group B is turned on, and the output terminals OUT1 to OUTm (source lines S1 to Sm) of the source drive circuit 10 Are respectively connected to the outputs of the source drivers SD1 to SDm, and the output signals of the source drivers SD1 to SDm are output to the source lines S1 to Sm, respectively.

  Here, when the point a ′ becomes “0”, all the analog switch groups A are already OFF. As described above, in the switch control circuit 100, even if the signal PC becomes “0”, if the point a ′ does not become “0”, the point b ′ does not become “1”. The analog switch group B is not turned on and the source line group is not connected to the output of the source driver group unless the source line group is disconnected from the common power supply Vcom. That is, the switch control circuit 100 detects that the signal PC is “0” and the point a ′ is “0” (= the analog switch group A is all OFF), and then the point b ′. Is set to "1" and the analog switch group B is turned ON.

  As described above, according to the first embodiment, the switch control circuit 100 detects that all the analog switch groups B are turned off, then turns on the analog switch group A, and detects that all the analog switch groups A are turned off. Then, by turning on the analog switch group B, the output terminals OUT1 to OUTm (source lines S1 to Sm) of the source drive circuit 10 are disconnected from the output terminals of the source driver group or the common power supply Vcom, and always have a high impedance. Since it is connected to the common power supply Vcom or the output terminal of the source driver group after the above, overcurrent between the output of the source driver group and the common power supply Vcom during precharging can be prevented, which is the original effect of precharging. High-speed and low power consumption liquid crystal drive can be realized.

  Further, since it is detected by the flip-flop circuit that all the analog switch groups are turned off, the delay amount due to the resistance / capacitance can be automatically complemented. Furthermore, according to the present embodiment, the flip-flop circuits constituting the switch control circuit are divided and arranged on the left and right sides of the analog switch group on the semiconductor chip. As a result, the resistance values, wiring capacitances, and parasitic capacitances of the plurality of wirings (signal line Line A and signal line line B) that connect the constituent elements of the flip-flop circuits that are separately arranged are set to be approximately equal. Therefore, a period during which the analog switch group A is turned off (a period from when the point a changes to the L level until the point a ′ changes to the L level) and a period during which the analog switch group B is turned off (the point b ′). The period from when point B changes to the L level until point b changes to the L level can be set to be approximately equal without providing a special circuit. Therefore, it is possible to easily realize a high-speed circuit operation while preventing the two switch groups from being turned on at the same time.

FIG. 5 is a block diagram of the liquid crystal display according to the second embodiment of the present invention, and the same components as those in FIG. FIG. 6 is a circuit configuration diagram of the source drive circuit 20 according to the second embodiment of the present invention shown in FIG. 5, and the same components as those shown in FIG.
The liquid crystal display of Example 2 in FIG. 5 includes a liquid crystal panel 1, a gate driving circuit 2, a source driving circuit 20 of Example 2, a source line group, and a gate line group. The liquid crystal display according to the second embodiment has a configuration in which the source driving circuit 10 is replaced with the source driving circuit 20 in the liquid crystal display according to the first embodiment (see FIG. 1).

[Source Drive Circuit 20]
As illustrated in FIGS. 5 and 6, the source drive circuit 20 according to the second embodiment includes a source driver group, an analog switch group A, an analog switch group B, and a switch control circuit 200. The source drive circuit 20 has a configuration in which the source drive control circuit 100 is replaced with the source drive control circuit 200 in the source drive circuit 10 (see FIGS. 1 and 2) of the first embodiment.

[Switch control circuit 200]
As shown in FIG. 6, the switch control circuit 200 includes NOR gates N1 and N2, inverters I1, I2 and I3, and an AND gate AN, and the analog switch groups A and B according to two input signals PC and LP. Controls switch operation. This switch control circuit 200 has a configuration in which an AND gate AN for inputting a signal LP is provided in the switch control circuit 100 (see FIG. 1) of the first embodiment. The AND gate AN is arranged in the peripheral region on the left side of the semiconductor chip shown in FIG. That is, the AND gate AN is arranged in the peripheral region 100A.

  The AND gate AN receives the input signal LP and a signal appearing at the point c (an output signal of the NOR gate N1) and outputs a signal at the point a. This input signal LP is a control signal for permitting / prohibiting the ON operation of the analog switch group A.

[Operation of Embodiment 2]
FIG. 7 is a timing chart in the 2-dot inversion driving of the source driving circuit 20 according to the second embodiment of the present invention. 7, (1) is the output signal OUT of the source drive circuit 20 (OUTi (Si) in FIG. 6), (2) is the input signal LP, (3) is the input signal PC, (4) is the signal PCB, ( 5) is a waveform at points b and b ′ of the signal line Line B, (6) is a waveform at point c (output of the NOR gate N1), and (7) is a waveform at points a and a ′ of the signal line Line A. It is. Td is a one-dot period of the liquid crystal display, and Tp is a precharge period.

  FIG. 8 is an enlarged view of the precharge period Tp in FIG. 8, (1) is an input signal LP, (2) is an input signal PC, (3) is a signal PCB, (4) is a waveform at points b and b ′ of the signal line Line B, and (5) is c The waveform at the point (6) is the waveform at the points a and a ′ of the signal line Line A.

The operation of the source drive circuit 20 according to the second embodiment will be described below with reference to FIGS. In the following description, logic “0” is “L” level and logic “1” is “H” level.
The basic operation of the source drive circuit 20 of the second embodiment is the same as that of the source drive circuit 10 of the first embodiment. The difference from the first embodiment is that the switch control circuit 200 can control permission / prohibition of the ON operation of the analog switch group A by the input signal LP.

[Driver output period]
In the driver output period, the input signal PC (the input signal of the NOR gate N2 and the inverter I3) is “0”, the signal PCB (the input signal of the NOR gate N1, the output signal of the inverter I3) is “1”, and point c (Output signal of NOR gate N1) is “0”. Therefore, since the point a (output signal of the AND gate AN) and the point a ′ (input signal of the NOR gate N2) are “0” and the output signal of the inverter I1 is “1”, the analog switch group A is turned off. The output terminals OUT1 to OUTm (source lines S1 to Sm) of the source driving circuit 20 are disconnected from the common power supply Vcom.

  Further, since the point b ′ (output signal of the NOR gate N2) and the point b (input signal of the NOR gate N1) are “1” and the output signal of the inverter I2 is “0”, the analog switch group B is turned on. The output terminals OUT1 to OUTm (source lines S1 to Sm) of the source driving circuit 20 are connected to the outputs of the source drivers SD1 to SDm, respectively, and the output signals of the source drivers SD1 to SDm are output to the source lines S1 to Sm, respectively. Has been.

[Operation to switch from driver output period to precharge period]
Next, when the input signal PC becomes “1”, the point b ′ first becomes “0”, and the point b also becomes “0” with a delay due to the wiring capacity or the like (see FIGS. 8 (2) and (4)). Similarly, since the output signal of the inverter I2 is also “1”, the analog switch group B is turned OFF, and the output terminals OUT1 to OUTm (source lines S1 to Sm) of the source drive circuit 20 are the outputs of the source drivers SD1 to SDm. Are separated from each other and become high impedance.

  When the input signal PC becomes “1”, the signal PCB becomes “0” (see FIGS. 8 (2) and 8 (3)). When the signal PCB is “0” and the point b becomes “0”, the point c becomes “1” (see FIGS. 8 (4) and (5)). At this time, if the input signal LP is “1” (see FIG. 8 (1)), when the point c becomes “1”, the point a first becomes “1”, and the point a ′ is delayed by the wiring capacity or the like. Is also “1” (see FIGS. 8 (5) and (6)), and similarly, the output signal of the inverter I 1 is also “0”, so that the analog switch group A is turned ON and the output terminal OUT 1 of the source drive circuit 20. ˜OUTm (source lines S1 to Sm) are short-circuited to the common power supply Vcom.

  Here, when the point b becomes “1”, the analog switch group B is all OFF. As described above, in the switch control circuit 200, even if the signal PCB becomes “0”, if the point b does not become “0”, the point a does not become “1”. Unless the source line group is completely disconnected from the source driver group, the analog switch group A is not turned ON and the source line group is not short-circuited to the common power source Vcom. That is, the switch control circuit 200 detects that the signal PCB is “0” and the point b becomes “0” (= the analog switch group B is all OFF), and then the point a is “ 1 "and the analog switch group A is turned ON.

[Precharge period]
In the precharge period, the input signal PC (input signal of the NOR gate N2 and the inverter I3) is “1”, and the signal PCB (input signal of the NOR gate N1 and output signal of the inverter I3) is “0”. Therefore, the point b ′ (output signal number of the NOR gate N2) and the point b (input signal of the NOR gate N1) are “0” and the output signal of the inverter I2 is “1”, so the analog switch group B is turned off. The output terminals OUT1 to OUTm (source lines S1 to Sm) of the source drive circuit 10 are separated from the outputs of the source drivers SD1 to SDm, respectively.

  If the input signal LP is "1", the point a (the output signal of the NOR gate N1) and the point a '(the input signal of the NOR gate N2) are "1", so the analog switch group A is turned on. The output terminals OUT1 to OUTm (source lines S1 to Sm) of the source driving circuit 10 are short-circuited to the common power supply Vcom and precharged.

[Operation to switch from precharge period to driver output period]
Next, when the input signal PC becomes “0”, the signal PCB becomes “1” (see FIGS. 8 (2) and (3)). When the signal PCB becomes “1”, the point c becomes “0” (see FIGS. 8 (3) and (5)). At this time, if the input signal LP is “1” (see FIG. 8 (1)), when the point c becomes “0”, the point a first becomes “0”, which is delayed by the wiring capacity and the point a ′. Becomes “0” (see FIGS. 8 (5) and (6)), and similarly, the output signal of the inverter I 1 also becomes “1”, so that the analog switch group A is turned OFF and the output terminal OUT 1 of the source drive circuit 20. ˜OUTm (source lines S1 to Sm) are disconnected from the common power supply Vcom and become high impedance.

  Further, when the signal PC is “0” and the point a ′ becomes “0”, the point b ′ first becomes “1”, and the point b also becomes “1” with a delay due to the wiring capacity or the like (FIG. 8). Similarly, since the output signal of the inverter I2 is also “0”, the analog switch group B is turned on, and the output terminals OUT1 to OUTm (source lines S1 to Sm) of the source drive circuit 10 are turned on. Are respectively connected to the outputs of the source drivers SD1 to SDm, and the output signals of the source drivers SD1 to SDm are output to the source lines S1 to Sm, respectively.

  Here, when the point a ′ becomes “0”, all the analog switch groups A are already OFF. Thus, in the switch control circuit 200, even if the signal PC becomes “0”, if the point a ′ does not become “0”, the point b ′ does not become “1”. The analog switch group B is not turned on and the source line group is not connected to the output of the source driver group unless the source line group is disconnected from the common power supply Vcom. That is, the switch control circuit 200 detects that the signal PC is “0” and that the point a ′ is “0” (= the analog switch group A is all OFF), and then the point b ′. Is set to "1" and the analog switch group B is turned ON.

  Further, in the switch control circuit 200, if the input signal LP is “0” in the precharge period, even if the point c becomes “1”, the points a and a ′ remain “0” (see FIG. 7 (7)), similarly, since the output signal of the inverter I1 remains “1”, the analog switch group A remains OFF, and the output terminals OUT1 to OUTm (source lines S1 to Sm) of the source drive circuit 20 remain. Remains disconnected from the common power supply Vcom and is not precharged (see FIG. 7 (1)). In this way, the switch control circuit 200 can control whether or not to perform the precharge operation during the precharge period by the input signal LP (control signal for permitting / inhibiting the ON operation of the analog switch group A).

  For example, a polarity inversion signal can be used as the input signal LP. If the input signal LP is fixed to “1”, the operation of the switch control circuit 200 is the same as that of the switch control circuit 100 of the first embodiment.

  FIG. 7 is a timing chart in the case where the precharge operation is performed only at the time of dot inversion by using the polarity inversion signal as the input signal LP in the 2-dot inversion driving. On the other hand, FIG. 16 is a timing chart in the 2-dot inversion driving of the conventional source driving circuit 3 of FIG. In FIG. 16, (1) is an output signal OUT (OUTi (Si) in FIG. 1) of the source drive circuit 3, (2) is an input signal PC, and (3) is a signal PCB. Td is a one-dot period of the liquid crystal display, and Tp is a precharge period.

  As shown in FIG. 16, in the conventional source drive circuit 3, a precharge operation is performed for each dot, and thus a precharge operation is performed even in a precharge period Tp in which dot inversion is not performed. The charging operation consumes useless power.

  On the other hand, as shown in FIG. 7, in the source drive circuit 20 of the second embodiment, the precharge operation is performed only in the precharge period Tp at the time of dot inversion by the input signal LP (polarity inversion signal), and dot inversion is not performed. In the precharge period Tp, the precharge operation is not performed and wasteful power is not consumed, so that power consumption can be reduced in the multiple dot inversion drive such as the 2-dot inversion drive.

  As described above, according to the second embodiment, the same effect as in the first embodiment can be obtained, and whether or not the precharge operation is performed in the precharge period by the input signal LP (whether or not the analog switch group A is turned on). By controlling (), it is possible to eliminate a useless precharge operation in the multi-dot inversion driving, so that power consumption can be reduced.

  In the first and second embodiments, the NOR circuit and the inverter are used to configure the switch control circuits 100 and 200. However, the present invention can be realized by other corresponding logic circuits. Further, the switch control circuits 100 and 200 are configured with the logic “0” at the “L” level and the logic “1” at the “H” level, but the logic “0” is at the “H” level and the logic “1” is at the “L” level. "It can be realized as a level.

  FIG. 9 is a circuit configuration diagram of the source drive circuit according to the third embodiment of the present invention. Components similar to those in FIG. 1 or FIG. The source drive circuit according to the third embodiment includes a source driver group, an analog switch group A, an analog switch group B, and a switch control circuit 1000.

  The switch control circuit 1000 in FIG. 9 is the switch control circuit 100 (see FIGS. 1 and 2) of the first embodiment or the switch control circuit 200 of the second embodiment (see FIGS. 5 and 6). As described above, the switch control circuit 1000 in FIG. 9 is divided into two parts with the analog switch group interposed therebetween. Therefore, in FIG. 9, a part of the switch control circuit 1000 arranged on the left side of the semiconductor chip is shown as a switch control circuit 1000L, and a part of the switch control circuit 1000 arranged on the right side of the semiconductor chip is shown as a switch control circuit. It is shown as 1000R. As shown in FIG. 9, the source drive circuit of the third embodiment is the same as the source drive circuit 10 of the first embodiment (see FIGS. 1 and 2) or the source drive circuit 20 of the second embodiment (see FIGS. 5 and 5). 6), the configuration of the analog switch group A is changed.

  The analog switch group A of the third embodiment is configured by m analog switches (MOS switches) A1, A2,..., Am and m resistors R1, R2,. The analog switch Ai and the resistor Ri are provided in series between the source line Si (the output terminal of the source driving circuit) and the common power supply Vcom (the potential of the common electrode of the liquid crystal cell capacitor). The analog switch Ai shorts the source line Si (the output terminal of the source driving circuit) to the common power source Vcom via the resistor Ri in accordance with the signals supplied to the signal lines Line A and Line A ′, and disconnects it from the common power source Vcom. .

  As described above, according to the third embodiment, the same effects as those of the first or second embodiment can be obtained, and the peak current and noise in the precharge can be reduced by performing the precharge through the resistor.

FIG. 10 is a circuit diagram of a source drive circuit according to the fourth embodiment of the present invention. Components similar to those in FIGS. 1, 2, and 9 are denoted by the same reference numerals.
As shown in FIG. 10, the source drive circuit of the fourth embodiment is the same as the source drive circuit 10 of the first embodiment (see FIGS. 1 and 2) or the source drive circuit 20 of the second embodiment (see FIGS. 5 and 6). ), The configuration of the analog switch group A is changed.

In the analog switch group A of the fourth embodiment, the analog switch Ai is provided between the source line Si (the output terminal of the source driving circuit) and the power source VDS / 2. The analog switch Ai shorts the output terminal OUTi (source line Si) to the power source VDS / 2 and disconnects it from the power source VDS / 2 in accordance with signals supplied to the signal lines Line A and Line A ′.
Here, the power source VDS / 2 is a power source having a potential that is ½ of the power source VDS supplied to the source drivers SD1 to SDm, and is a potential power source that is the center of the amplitude of the output of the source drivers SD1 to SDm.

  In the first to third embodiments, the precharge power source that short-circuits the source line Si (the output terminal of the source drive circuit) for precharging is the common power source Vcom. However, the common power source Vcom is used for flicker removal and the like. There is a case where the potential is deviated from the power source VDS / 2. In such a case, it is desirable that the precharge power source is the power source VDS / 2 in order to realize liquid crystal driving with high speed and low power consumption.

  As described above, according to the fourth embodiment, the same effects as those of the first or second embodiment can be obtained, and liquid crystal driving with higher speed and lower power consumption can be realized by using the power supply VDS / 2 as the precharge power supply. it can.

FIG. 11 is a circuit diagram of a source driving circuit according to the fifth embodiment of the present invention. Components similar to those in FIGS. 1, 2, and 9 are denoted by the same reference numerals.
As shown in FIG. 11, the source driving circuit of the fifth embodiment is the source driving circuit 10 of the first embodiment (see FIGS. 1 and 2) or the source driving circuit 20 of the second embodiment (see FIGS. 5 and 6). ), The configuration of the analog switch group A is changed.

  The analog switch group A of the fifth embodiment includes m-1 analog switches (MOS switches) A1, A2,..., Am-1. The analog switch Ak (k is any integer from 1 to m−1) is provided between the source line Sk (the output terminal of the source driving circuit) and the source line Sk + 1 (the output terminal of the source driving circuit). . The analog switch Ak short-circuits between the source line Sk (the output terminal of the source driving circuit) and the source line Sk + 1 (the output terminal of the source driving circuit) in accordance with signals supplied to the signal lines Line A and Line A ′. This disconnects the short circuit between the source lines (between the output terminals of the source drive circuit). In the fifth embodiment, the precharge power supply is used as another source line (another output terminal of the source drive circuit).

  As described above, according to the fifth embodiment, the same effects as those of the first or second embodiment can be obtained, and the source lines can be short-circuited between the source lines (between the output terminals of the source driving circuit) and precharged. Since it is not necessary to supply the common power supply Vcom to the drive circuit, the power consumption can be further reduced.

FIG. 12 is a circuit diagram of a source drive circuit according to Embodiment 6 of the present invention. Components similar to those in FIG.
As shown in FIG. 12, the source drive circuit of the sixth embodiment is obtained by changing the configuration of the analog switch group A in the source drive circuit of the fifth embodiment (see FIG. 11).

  The analog switch group A of the sixth embodiment includes m−1 analog switches (MOS switches) A1, A2,..., Am−1 and m−1 resistors R1, R2,. Has been. The analog switch Ak and the resistor Rk are provided in series between the source line Sk (output terminal of the source driving circuit) and the source line Sk + 1 (output terminal of the source driving circuit). The analog switch Ak has a resistor Rk between the source line Sk (the output terminal of the source driving circuit) and the source line Sk + 1 (the output terminal of the source driving circuit) in accordance with signals supplied to the signal lines Line A and Line A ′. And the short circuit between the source lines (between the output terminals of the source drive circuit) is disconnected.

  As described above, according to the sixth embodiment, the same effects as those of the fifth embodiment can be obtained, and the peak current and noise in the precharge can be reduced by performing the precharge through the resistor.

FIG. 13 is a circuit diagram of a source driving circuit according to the seventh embodiment of the present invention. Components similar to those in FIG.
As shown in FIG. 12, the source drive circuit of the sixth embodiment is not provided with the analog switches A2, A4,..., Am-2 of the analog switch group A in the source drive circuit of the fifth embodiment (see FIG. 11). It is what I did. However, in the sixth embodiment, m is an even number.

  The analog switch group A of the sixth embodiment includes m / 2 (where m is an even number in the sixth embodiment) analog switches (MOS switches) A1, A3,..., Am-3, Am-1. An analog switch Ak is provided only between the source line Sk (output terminal of the source driving circuit) where k is an odd number and the source line Sk + 1 (output terminal of the source driving circuit) where k is an odd number, and the source line Sk where k is an even number No analog switch is provided between Sk + 1. That is, in the analog switch group A of the sixth embodiment, the number (m / 2) of analog switches which is 1/2 of the number of source lines (m) is provided in proportion to one source line. It is.

  As described above, according to the seventh embodiment, the same effects as those of the fifth embodiment can be obtained, and the source line Sk (output terminal of the source driving circuit) and the source line Sk + 1 (output of the source driving circuit) where k is an odd number. By providing the analog switch Ak only between the terminals), the number of analog switches in the analog switch group A can be reduced.

  In the first to seventh embodiments, the example in which the liquid crystal driving circuit of the present invention is applied to the source driving circuit has been described. Similarly, the liquid crystal driving circuit of the present invention can be applied to the gate driving circuit.

It is a block diagram of the liquid crystal display of Example 1 of this invention. It is a circuit block diagram of the source drive circuit of Example 1 of this invention. 4 is a timing chart in 1-dot inversion driving of the source driving circuit according to the first exemplary embodiment of the present invention. FIG. 4 is an enlarged view of a precharge period in FIG. 3. It is a block diagram of the liquid crystal display of Example 2 of this invention. It is a circuit block diagram of the source drive circuit of Example 2 of this invention. It is a timing chart in 2 dot inversion drive of the source drive circuit of Example 2 of this invention. FIG. 8 is an enlarged view of a precharge period in FIG. 7. It is a circuit block diagram of the source drive circuit of Example 3 of this invention. It is a circuit block diagram of the source drive circuit of Example 4 of this invention. It is a circuit block diagram of the source drive circuit of Example 5 of this invention. It is a circuit block diagram of the source drive circuit of Example 6 of this invention. It is a circuit block diagram of the source drive circuit of Example 7 of this invention. It is a block diagram of the conventional liquid crystal display. It is a circuit block diagram of the conventional source drive circuit. It is a timing chart in 2 dot inversion drive of the conventional source drive circuit. 1 is a layout diagram on a chip of a source drive circuit of Example 1 of the present invention. FIG. It is a circuit block diagram of the switch control circuit 100 of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Liquid crystal panel 2 Gate drive circuit 10,20 Source drive circuit 100,200,1000 Switch control circuit A, B Analog switch group G Gate line S Source line GD Gate driver SD Source driver TR Switch transistor CX Liquid crystal cell capacitance I1, I2, I3 Inverter N1, N2 NOR gate AN AND gate

Claims (15)

A driving circuit for driving a matrix line group of a liquid crystal device,
A group of drivers that output drive signals;
A first switch group having a conductive state for connecting between the output of the driver group and the matrix line group and a non-conductive state for disconnecting;
A second switch group having a conductive state for connecting between the matrix line group and the precharge power source and a non-conductive state for disconnecting;
Switch control means for controlling the states of the first switch group and the second switch group,
The switch control means detects that all the switches of the first switch group are in a non-conductive state, sets the second switch group to a conductive state, and sets all the switches in the second switch group to a conductive state. A drive circuit comprising: detecting that a switch is in a non-conductive state; and setting the first switch group to a conductive state. The switch control means includes
After the input control signal changes from the first logic value to the second logic value, the first switch group is turned off.
Detecting that the input control signal is the second logical value and all the switches of the first switch group are in a non-conductive state, and sets the second switch group in a conductive state;
After the input control signal changes from the second logic value to the first logic value, the second switch group is turned off,
Detecting that the input control signal is the first logical value and all the switches of the second switch group are in a non-conductive state, and sets the first switch group to a conductive state. The drive circuit according to claim 1. Each of the first switch group and the second switch group includes a plurality of analog switches,
The switch control means includes
A first NOR gate having the input control signal as one of inputs;
A first inverter having the output of the first NOR gate as an input;
A second inverter having the input control signal as an input;
A second NOR gate having the output of the second inverter as one input;
A third inverter having the output of the second NOR gate as an input,
The output of the first NOR gate is connected to the NMOS gates of all analog switches of the first switch group and the inputs of the second NOR gate,
The output of the first inverter is connected to the PMOS gates of all the analog switches of the first switch group,
The output of the second NOR gate is connected to the NMOS gates of all analog switches of the second switch group and the inputs of the first NOR gate,
The drive circuit according to claim 2, wherein the output of the third inverter is connected to PMOS gates of all analog switches of the second switch group. The switch control means includes
When the first input control signal changes from the first logic value to the second logic value, the first switch group is turned off.
When the second input control signal is at the first logic value, the first input control signal is at the second logic value, and all the switches in the first switch group are turned off. Even if it is detected, the second switch group remains in a non-conductive state,
When the second input control signal is at the second logic value, the first input control signal is at the second logic value, and all the switches in the first switch group are in a non-conductive state. And the second switch group is turned on,
When the second input control signal is the second logic value and the first input control signal is changed from the second logic value to the first logic value, the second switch group Is turned off,
When it is detected that the first input control signal is the first logical value and all the switches of the second switch group are in a non-conductive state, the first switch group is turned on. The driving circuit according to claim 1, wherein the driving circuit is in a state. Each of the first switch group and the second switch group includes a plurality of analog switches,
The switch control means includes
A first NOR gate having one input of the first input control signal;
A first inverter having the output of the first NOR gate as an input;
A second inverter having the first input control signal as an input;
A second NOR gate having the output of the first inverter as one input;
An AND gate having the second input control signal and the output of the second NOR gate as inputs;
A third inverter whose input is the output of the AND gate;
With
The output of the first NOR gate is connected to the NMOS gates of all analog switches of the first switch group and the inputs of the second NOR gate,
The output of the first inverter is connected to the PMOS gates of all the analog switches of the first switch group,
The output of the AND gate is connected to the NMOS gates of all analog switches of the second switch group and the inputs of the first NOR gate,
The drive circuit according to claim 4, wherein an output of the third inverter is connected to PMOS gates of all analog switches of the second switch group. 2. The drive circuit according to claim 1, wherein the first switch group short-circuits the matrix line group to a common power source of the liquid crystal device. 2. The drive circuit according to claim 1, wherein the first switch group short-circuits the matrix line group to a power source having a potential that is ½ of a power supply of the driver group. 2. The drive circuit according to claim 1, wherein the first switch group short-circuits two matrix lines of the matrix line group. 9. The configuration according to claim 8, wherein the first switch group is configured such that one half of the number of matrix lines of the matrix line group is provided between two matrix lines. Liquid crystal drive circuit. 2. The drive circuit according to claim 1, wherein the first switch group short-circuits the matrix line group via a resistor. A drive circuit formed on a semiconductor chip for driving a plurality of matrix lines of a liquid crystal device,
A driver group disposed in a central region of the semiconductor chip and outputting a drive signal;
A first switch group disposed in a central region of the semiconductor chip and having a conductive state connecting the output of the driver group and the matrix line and a non-conductive state disconnecting;
A second switch group disposed in a central region of the semiconductor chip and having a conductive state for connecting between the matrix lines and a precharge power source and a non-conductive state for disconnecting;
A switch control means disposed in a peripheral region of the semiconductor chip, for controlling a conduction state of the first switch group and the second switch group;
The switch control means detects that all the switches of the first switch group are in a non-conductive state, sets the second switch group to a conductive state, and sets all the switches in the second switch group to a conductive state. A drive circuit comprising: detecting that a switch is in a non-conductive state; and setting the first switch group in a conductive state. The switch control circuit includes a first switch control circuit unit formed in one peripheral region across the central region, and a second switch control formed in the other peripheral region across the central region. A circuit unit, and an output terminal of the first switch control circuit unit and an input terminal of the second switch control circuit unit are connected via a first wiring extending to the central region, 12. The output terminal of the second switch control circuit unit and the input terminal of the first switch control circuit unit are connected via a second wiring extending to the central region. The drive circuit described. The drive circuit according to claim 12, wherein a length of the first wiring is equal to a length of the second wiring. 13. The drive circuit according to claim 12, wherein a resistance value of the first wiring and a resistance value of the second wiring are equal. 12. The drive circuit according to claim 11, wherein the switch control circuit is a flip-flop circuit.

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