GB2075726A

GB2075726A - Electronic timepiece

Info

Publication number: GB2075726A
Application number: GB8111934A
Authority: GB
Original assignee: Suwa Seikosha KK
Current assignee: Suwa Seikosha KK
Priority date: 1980-05-02
Filing date: 1981-04-15
Publication date: 1981-11-18
Also published as: DE3117270A1; FR2481826B1; HK88785A; CH647639GA3; GB2075726B; FR2481826A1; DE3117270C2

Abstract

An electronic timepiece has 7- segment digital display sections and a dot matrix display section (25). Circuitry is provided to produce a display of characters and/or pictures on the dot display section to illustrate function modes of the electronic timepiece. Slightly altered pictures may be displayed sequentially to give the impression of movement. Thus for example a running figure may be represented. This indicates that the watch is being used as a chronograph. The drive circuit includes a dot matrix pattern generator (22) and a scanning electrode drive circuit (24) for the dot matrix. <IMAGE>

Description

SPECIFICATION Electronic timepiece This invention relates to electronic timepieces.

Recently, much attention has been paid to electronic timepieces using liquid crystal display devices, as marketable commodities. The reason for this is that, for instance, electronic timepieces, unlike mechanical timepieces are technically easy to manufacture at relatively low cost. However, because electronic timepieces are technically easy to manufacture, electronic timepieces from different manufacturers tend to be identical or at least verysimilar: in other words it is difficult to manufacture electronic timepieces which are different from those of other manufacturers and this results in keen price competition.

The present invention seeks to provide an electronic timepiece which can produce various displays. The conventional electronic timepieces with a liquid crystal display device have relatively-low operability although they can be modified to perform various functions. That is, in general, heretofore in a conventional electronic timepiece, the functional operations are illustrated with aliphatic letters but these tend to be too small to read and are not of an acceptable design.

According to the present invention there is provided an electronic timepiece comprising: a time standard signal generating circuit for producing a time standard signal; a frequency divider circuit for frequency dividing the time standard signal; a driving circuit connected to receive output signals from the divider circuit; a display device driven by the driving circuit to display time information, the display device comprising a 7-segment digital display section and a dot matrix display section; and a circuit for generating a display of characters and/or pictures on the dot display section illustratihg function modes of the electronic timepiece.

The 7-segment display-section and the dot matrix display section may be composed of liquid crystal display elements, electrochromic display elements or photodiode display elements and may be the same or different.

In one embodiment the 7-segment display section and the dot matrix display section are parts of the same liquid crystal display panel.

In another embodiment the 7-segmentdisplay section is constituted by one layer of-a multilayer liquid crystal display panel and the dot matrix display device is constituted by a second layer thereof.

Preferably the driving circuit is such that, in operation, the display device is driven by multiplex drive signals, the duty of the drive signals applied to the 7-segment display section' being different from the duty of the drive signals applied to the dot matrix display section.

The electronic timepiece may include a switch circuit which switches the characters-and/or pictures on the dot display section in synchronism with the output of a function counter circuit Preferably the display device comprises signal electrodes of the dot display section and segment electrodes of the 7-segment display section formed on one substrate, scanning electrodes of the dot display section and common electrodes of the 7-segment display section formed on a second.substrate,.and a liquid crystal layer disposed between the substrate, the signal electrbdes and the scanning electrodes forming picture elements of the dot display section and the-segment electrodes and common electrodes forming picture elements of the 7-segment display section, the driving circuit being so arranged that, in operation, the effective voltage applied to energise the picture elements of the dot display section substantially equal to the effective voltage applied to energise picture elements ofthe7-segment display section, by ensuring that a segment signal applied to the segment electrodes and a common signal applied to thecommon electrodes have the same potential at least once during a frame interval.

The invention is illustrated, merely by way of example, in the accompanying drawings, in which: Figure 1 is an external view of one embodiment of an electronic timepiece accdrding to the present invention; Figures 2-a to 2-c illustrate displays produced in different modes of the electronic timepiece of Figure 1; Figures 3-a and 3-b illustrate displays produced when the electronic timepiece of Figure 1 is in a time correction mode; Figures 4-a to 4-e illustrate displays produced when the electronic timepiece of Figure 1 is in a chronograph mode; Figures 5-a to 5-e illustrate displays produced when the electronic timepiece of Figure 1 is in a imer mode;; Figure 6 is a block diagram of the circuitry of an electronic timepiece according to the present invention; Figure 7 is an explanatory diagram of a dot matrix display section of the electronic timepiece of Figure 6; Figure 8 is a block diagram of a dot matrix pattern generator of the electronic timepiece of Figure 6 and its peripheral circuits; Figures 9-a and 9-b are timing charts illustrating the operation of the dot matrix pattern generator of Figure 8; Figure 10 illustrates graphically variation of effective voltage with contrast in 9 twisted riematic-type liquid crystal display device; Figure 11(a) is an explanatory diagram showing scanning electrodes of a dot matrix display section of an electronic timepiece according tithe present invention;; Figure 11{by is an explanatory diagram showing signal electrodes of the dot matrix display section; Figure 12aha) is an explanatory diagram showing common electrodes of a 7-segment display section of an electronic timepiece according to the present invention; Figure 12(b) is an explanatory diagram showing segment electrodes of a 7-segment display section; Figures 13(aJ and 13{by illustrate displays produced by the dot display section; Figures 14fay to 14(eel are timing charts illustrating multiplex drive waveforms for the dot matrix display section;; Figures 75(at to 15bet are timing charts showing multiplex drive waveforms for the 7-segment display section; and Figure 16 is a circuit diagram showing a circuit for common electrodes of the 7-segment display section.

A liquid crystal display device is advantageous in that its power consumption is relatively small and it can be operated on a relatively low voltage and can be miniaturised. Accordingly, liquid crystal display devices are extensively used in timepieces and portable calculators etc. There has developed a demand for liquid crystal display devices which can display a variety of information and to satisfy this demand a multiplex drive system hays been developed for driving a dot matrix liquid crystal-display device. A dot matrix liquid crystal display device is one in which display picture elements are formed at the intersections of a plurality of scanning electrodes and a-plurality of parallel signal electrodes so that characters or figures can be readily displayed.

Referring first to Figure 1, there is shown one embodiment of an electronic timepiece according to the present invention. The electronic timepiece comprises 7-segment display sectionsl a to 1 C, a dot matrix display section 2 and push-button switches 3 to 6. The electronic timepiece can operate in a time of day mode (T mode), a chronograph mode (CH mode), an alarm set mode (AL mode), a timer mode (TR mode) and a time set mode (TS mode). These modes can be selected by appropriately operating the pushbutton switch 5. More specifically, the modes are selected cyclically (one at a time) each time the push-button switch 5 is operated. The push-button switch 3 serves as a start switch in the CH mode or in the TR mode and as a select switch in the AL mode or in the TS mode.The push-button switch 4 serves as a lap switch and a reset switch in the CH mode, as a set switch in the AL mode and in the TS mode, and as a timer set in the reset switch in the TR mode. The push-button switch 6 serves to energise a lamp (nnt shown) in all modes.

The 7-segment display sections la to Ic displaynumerical values and characters A and P as follows.

In the T mode, the 7-segment display sections 1 a to 1 C, display hours, minutes, seconds respectively. In the CH mode, the 7-segment display sections la, ib display minutes and seconds respectively, and the 7-segment display section 1 C displays 1/100 seconds IIN THE AL mode, the 7-segment display sections 1 a, 1b display alarm set hours and alarm set minutes respectively, and the 7-segment display section 1 C displays either the letter A standing for AM or the letter P standing for PM.In the TR mode the 7-segment display section 1 a produces no display, the 7-segment display section 1 b displays minutes and the 7-segment display section 1 C displays seconds which have elapsed after the start of the timer. In the TS mode, the 7-segment display sections la, 1b display hours and minutes respectively, and the 7-segment display section 1 C displays seconds in the period other than the period during which the time is corrected, and either the letter A or P in the period during which the time is corrected.

The dot matrix display section 2 displays characters or figures representing various operating modes.

Figure 2 shows examples of figures representing the various modes. In this embodiment a 16 x 17 dot matrix is formed by arranging picture elements in 16 columns and in 17 rows, signal electrodes being divided at the centre into two groups so that a multiplex drive of 1/8 duty is carried out. In the CH mode, the dot matrix display section 2 displays a running person (Figure 2-a). In the AL mode the dot matrix display section 2.displays a picture representing a buzzer sound (Figure 2-b). In the TR mode the dot matrix display section 2 displays a figure representing an hourglass (Figure 2-c). Thus the modes can be.distinguished visually. In the T mode the dot matrix display section 2 displays month and day of the week in a 5 x 7 dot matrix (Figure 3-a).In the TS mode the dot matrix display section 2 displays SET in the upper line to indicate the TS mode and nothing in the lower line in the case where seconds, minutes and hours are corrected but it displays one of the day, month and day of the week to be corrected when day, month, day of the week are to be corrected (Figure 3-b).

Furthermore, the various states within each mode can be indicated by Figures. For instance, in the CH mode, before the chronograph is started, the running person in the Figure takes a posture standing on the start line as shown in Figure 4-a. Upon operation of the push-button switch 3, the five patterns in Figures 4-b, 4-c, 4-d, 4-e and 4-a are successively displayed which appears to an observer as a person running. If, in this condition, the push-button switch 3 is operated again, the counter stops its counting operation, the 7-segmen;t display sections 1 a to 1 C display the time, and the movement of the running person is stopped.If the push-button switch 4 is operated while the chronograph is being operated, thepersori displayed on the dot matrix display section continues to appear running, but the time indicated by the 7-segment display sections is stopped to indicate lap time. Thus, the operational states of the electronic timepiece can be visually determined instantly. Similarly, the TR mode can be indicated by five patterns shown in Figures 5-a to 5-e. In the TR-mode,-first a desired timer time is set by operating the push-button switch 4. The timer can be set up to 99 minutes in units of 1 minute. In this case, the pattern as shown in Figure 5-a is displayed on the dot matrix display section. When in this condition, the pushbutton. switch 3 is operated, the patterns shown in Figures 5-a to 5-e are successively displayed which gives the appearance to an observer of sand falling in an hourglass. This indicates that the timer is in operation. Upon operation of the switch 3 again, the timer is stopped, and the picture displayed is also stopped. The display of the remaining time of the timer is reset by operating the push-button switch 4. This it will be appreciated that the electronic timepiece described above is such that its operating modes can be visually determined at a glance and this is particujarly convenient for the user.

Figure 6 is a block diagram of the circuitry of an electronic timepiece according to the present invention.

The electronic timepiece comprises a standard time signal generating circuit 7, a frequency divider circuit 8, a time counter 9 and a chatter preventing circuit 10, a control circuit 11, an alarm setting counter 12, a chronograph counter 13, a latch circuit 14, a timer counter 15, an alarm detecting circuit 16, a timer zero detecting circuit 17, a multiplexer 18 for displaying data, a 7-segment display decoder 19, a segment drive circuit 20 for the 7-segment display sections, a common electrode drive circuit 21 for the 7-segment display sections, a dot matrix pattern generator 22, a signal electrode drive circuit 23 for the dot matrix.display sections, a scanning electrode drive circuit 24 forthe dot matrix display section, a liquid crystal display panel 25 including the 7;;segment display sections of the dot matrix display section, a booster circuit 26, a battery 27, a buzzer drive circuit 50, and a buzzer 51.

A standard time signal (32768 Hz) from the standard signal generating circuit 7is frequency divided by the frequency divider ci rcu it 8 into a 1 Hz signal, which is fed to the time counter 9. The time counter 9 counts the signal in the order of seconds, minutes and hours. The outputs from the time counter are applied through the multiplexer 18 to the decoder 19, in which they are converted into 7-segment signals. The 7-segment signals are applied through the segment electrode drive circuit 20 to the liquid, crystal display panel 25 to drive the 7-segment display sections.

In the AL mode, the CH mode and the TR mode, the multiplexer 18 is switched with the aid of a signal M from the control circuit 11, so that the output data from the relevant counter is.displayed by the 7-segment display sections. This operation is the same as that of a conventional alarm chronograph and therefore further description thereof will be omitted.

The display produced by the dot matrix display section will now be described. The following Table indicates the type of data which is displayed by the dot matrix display section in the various modes. It will be noted from the following Table that 16 x 17 picture elements are divided into three blocks U1, U2 and Ug in the upper line and one block D in the lower line as shown in Figure 7.

TABLE U1 U2 U3 D Time of day Space Space. Day of Week mode 1,2,3 0-9 Chronograph Runner Runner Runner Runner mode Alarm mode Alarm mark Alarm mark Alarm mark Alarm mark Timer mode Sandglass Sandglass Sandglass Sandglass Time correction mode Second S E T Space Minute S E E Space Hour S E T Space Day Space 1,2,3 0-9 Space SET Space Month 1 0-9 Space SET Day of S E T Dayofweek week As will be apparent from the Table there are ten modes, and therefore it is necessary to use 4-bit mode.

codes to specify these modes. In each mode, a code necessary for switching the patterns is determined according to the largest number of patterns displayed. For instance, in blocks U1 U9 the chronograph mode and the timer mode have the largest number (5) of patterns. Therefore, in this case, 3-bit pattern codes are required. In the block U2, it is necessary to display the digits 0 to 9 and therefore 4-bit pattern codes are required. In the block D, 3-bit pattern codes are necessary to display a day of the week in the time of day mode and the time set mode. In order to specify dot matrix display data, scanning codes (3 bits with 1/8 duty) specifying scanning electrodes as well as the above mode codes and pattern codes are required.

Figure 8 is a block diagram showing the dot matrix pattern generator 22 and the peripheral circuits thereof.

The circuit shown in Figure 8 comprises, address decoders 28a to 28d, memory sections 29ato 29d in a pattern generator ROM, output latch and level shifter circuits 30a to 30d in the pattern generator ROM, multiplexers 31a to 31 d, a ten-days counter 32! a one-days counter 33, a days of the week counter 34, a ten-months decoder 46, a month decoder 47, and clock gate groups 35, 36, 38 to 45, 48 and 49. It should be noted that, in Figure 8, circuit elements having numerals suffixed a are for the block U1, circuit elements having numerals suffixed by bare for the block U2, circuit elements having numerals sufficed by c are for the block U3, and circuit elements having numerals suffixed by door the block D.In addressing the blocks, a mode code (MD1 - MD4) and a scanning code (S1 - S3) are fed commonly to terminals Ao to A3 (4-bits) -and terminals A4 to A6 (3 bits) of the address decoders 28a to 28d respectively. Pattern codes peculiar to the blocks are fed to terminals A7 to A10 of the address decoders 28a to 28d. In the time mode, the clock gate groups 42 to 45 are closed (OFF) while the clock gate groups 38 to 41 are opened (ON), as a result of which outputs a10d and ss10dfrom the ten-days counter 32 are applied to the terminals A7 and As in the block U1, and the space or the digit 1,2 or 3 which is specified by the outputs α10d and #ss10d is displayed on the block U1.

Similarly, the digit 0, 1, 2... or 9 which is specified by outputs ad, pd, yd and bd of the one-days counter 33 is displayed on the block U2. A space is displayed on the block U3. The day of the week which is specified by the 3-bit outputs aDY, ssDY and yDY of the days of the week counter 34 is displayed in the block D. Inihe chronograph mode, the clock gate groups 38 to 41, 36, 37 are closed, while theclock data groups 42 to 45 and 35 are opened. As a result, patterns shown in Figures 4-a to 4-e are switched by the outputs of 1/10 seconds BCD counters of the chronograph counter 13.

Figure 9-a is a timing chart wherein the patterns are switched by the outputs 1 1 1 BC S, γC S and #C S.

10 10 10 When the cronograph counter 13 is maintained reset, the pattern shown in Figure 4-a is displayed. However, after the level of a CRUN signal becomes level H to start the chronograph counter, the states of the outputs 1 1 ssCyCand an10s are changed, and according!y the patterns shown in Figures 4-a to 4-e are switched every 200 ms in the stated order. When the CRUN signal is set to level L, the chronograph counter 13 is stopped, and in response to the outputs 1 1 1 ssC S, γC S or #C S 10 10 10 at that time instant the patterns displayed, i.e. the runner, is stopped. In the lap operation, the counter is being operated, and therefore the patterns displaying the runner are being switched, however, the 7-segment display sections are stopped with the lap time displayed.The time display of the 7-segment display sections is effected again upon releasing the lap operation.

In the timer mode, the clock gate groups 38 to 41 and 35 are closed, while the clock gate groups 42 to 45 and 36 are opened as a result of which outputs pTRS, yTRS and #TRS are a seconds counter in the timer counter 15 which may be a NCD up-down counter, are applied to the terminals A7 to Ag of the address decoders 28a to 29d, to switch the display patterns. Figure 9-b illustrates the timing for switching the patterns. When the timer is initially set, the seconds counter is set to zero and therefore the pattern shown in Figure 5-a is displayed. After the level of a TRRUN signal becomes level H to start a subtraction timer, the patterns shown in Figures 5-a to 5-e are switched in synchronisation with the outputs ssTRS to yTRS. That is, the patterns are switched every two seconds, and the first pattern repeats after ten seconds.

In the alarm mode, the alarm mark (as shown in Figure 2-b) is always displayed irrespective of the data applied to the terminals A7 to Ag. In the time set mode, the displays depend on the set modes from seconds to days of the week. In the set modes from seconds to hours, irrespective of the data applied to the terminals A7 to A9, S, E and Tare displayed on the blocks U1, U2, U3 respectively and a space is displayed on the block D. In the day correction mode, a date is displayed on the blocks U1, U2 by the outputs from the ten-days counter 32 and the one-days counter 33, similarly as in the time of day mode, and thecharncter D representing the day correction mode is displayed on the block U3. At the same time, the term SET representing the time correction mode is displayed by the block D.In the month correction mode, only the clock gate groups 48, 49 and 40 are opened. As a result, the output data of the month decoder is applied to the terminals A7 to Ag so that a month is displayed on the blocks U1, U2 while the character M representing the month correction mode is displayed by the block U3 and similarly as in the case of the day correction mode, the term SET isdisplayed on the block D. In the days of the week correction mode, the term SET is displayed on the blocks U1, U2, U3 and the day of the week which is specified by the output signal aDY, ssDY and yDY from the days of the week counter 34 is displayed in three English characters on the block D.

The pattern generator ROM thus addressed applies the data which corresponds to the number of segments in the blocks (six for U1 and U2, five for U3 and 17 for D) to the respective parallel data latch circuits 30a to 30d, where the data is latched with suitable timing and is held as a control signal for the multiplexers 31a to 3ldfor a period of time of one scanning signal. Since the signalsforthesignal electrodes are processed in a parallel mode, as described above, it is unnecessary to perform series-parallel conversion, which results in a reduction of power consumption.

The capacity of storage which is required for the pattern generator ROM is one corresponding to about 17.8 pieces of pattern. As it is necessary to use 272 bits for each pattern, about 5K-(5,000) bits are required for the pattern generator. As the degree of element integration has been remarkably improved recently, the bits can be readily provided on a single chip. On the other hand, the power consumption for transferring the display data is increased but this problem can be solved by using lithium batteries or solar batteries.

In the above described embodiment, the dot matrix display section and the 7-segment display sections are arranged on the same planar panel. However, two panels laid one on top of another to perform a multi-layer liquid crystal display device may be employed in such a manner that the 7-segment display sections are provided on the first layer and the dot matrix display section is provided on the second layer. In addition, the 7-segment display sections and the dot matrix display section can be displayed in using two liquid crystal display panels side by side. In this case the so-called active matrix panel in which an active element is formed for each picture element may be used for the dot matrix display section.

In the above-described embodiment of the present invention, the pattern generator circuit is controlled by addressing the pattern generator ROM. However, the pattern generator ROM may be so designed that outputs in all the modes are provided in a parallel fashion and are controlled by a multiplexer.

The present invention is not limited to the 7-segment display sections and the dot matrix display section being liquid crystal display sections but they may be composed of electrochromic display elements or photodiode display elements and bit may be the same or different.

Figure 10 illustrates graphically variation of effective voltage with contrast in a conventional twisted nematic type liquid crystal display device. In Figure 10, reference letter A designates an effective voltage when the contrast is 10% of the difference between the contrast and an effective voltage of zero and the contrast with a saturated effective voltage, and reference letter B designates an effective voltage when the contrast is 90% of this difference. The effective voltages A and B are referred to as "threshold voltage Vth" and "saturated effective voltage Vs" respectively.The threshold voltage Vth is such that the contrast with an effective voltage lower than the threshold voltage Vth can be substantially regarded as equal to the contrast with zero effective voltage E,ff. It is essential that Eoff is less than Vth in order to prevent the production of half tones. If Eoff is set between the effective voltages A and B, then haif tones will be produced. in the case of a multiplex drive system, the effective voltage Eon in a turn-on operation and the effective voltage Eoff in a turn-off operation are respectively given by:

where N is the number of scanning electrodes, a the bias ratio, and V,,is the drive voltage.

As will be apparent from these equations, the range of the ratio Eon to Eoff ( on ) Eoff is reduced as N is increased; that is the contrast is reduced with increase of N. Accordingly, N should be as small as possible. However, in the case of a dot matrix display device, a number of picture elements are employed, and accordingly it is difficult to have a satisfactory display because of the number of electrode terminals, without using data signals with a duty of 1/7 or 1/8. In the case of a regular configured display device such as a dot matrix display device, even half tones are produced to some extent, non-uniformity due to such half tones is not as significant as expected.However, if N is set to a duty of 117 or 1/8, for instance, in the case of a 7-segment display section, then there is considerable difficulty in reading the display produced because of the half tones, and so usually N is limited to a duty of 1/4 to provide a satisfactory display. In the case where a display is produced by a liquid crystal display device having a dot matrix display section with a duty of 1/8 and a 7-segment display section with a duty of 1/4, the effective voltages in the turn-on operation are V0/3 and vVo/3, respectively (when a = 3). Accordingly, this liquid crystal display device has sections of different contrast when it is turned on and the non--uniformity due to the different contrast is significant.

Figure 11 (a) rshows eight horizontally arranged transparent scanning electrodes Y1, Y2....Y8 on one side of a dot matrix display section of an electronic timepiece according to the present invention. Figure 11(b) shows 34 vertically arranged transparent signal electrodes Xf, X2.... X34 on the other side of the dot matrix display section. A liquid crystal layer (not shown) is interposed between the scanning electrodes and the signal electrndes.--The intersections of the scanning electrodes and the signal electrodes form picture elements.

Thus, in this embodiment, a 16 x 17 dot matrix display section is formed.

Figure 12(a) shows a transparent common electrode pattern of a 7-segment display section which includes four so-called "common" electrodes COM1, COM2, COM3,COM4. Figure 12(tor) shows a transparent segment electrode pattern of the 7-segment display section which includes 12 so-called "segment" electrodes SEG1, SEG2...SEG12. A liquid crystal layer (not shown) is interposed between the common electrodes and the segment electrodes so that picture elements are formed at the intersections of the common electrodes and the segment electrodes.

Figure 13(a) shows a display of a liquid crystal display device of an electronic timepiece according to the present invention such as a wrist watch. A 7-segment display section displays 10 hours, 24 minutes, 35 seconds. The hours, minutes and seconds are indicated by the letters H, M and S respectively. The dot matrix display section displays 20th Sunday. Figure 13(b) shows a display in the chronograph mode. The 7-segment display section displays 2 minutes, 23.54 seconds and the dot matrix display section displays a running man.

If about five pictures of motion are provided and are successively displayed, an observer can appreciate visually at a glance that the time is being counted in the chronograph mode.

Figures 14(a) to 14(e) illustrate conventional multiplex drive waveforms for the dot matrix display section.

Figure 14(a) illustrates one example of a signal applied to the scanning electrodes. One period T of the signal is fromt = 0 to t4. In the period T, the first frame is from t=0 to t2 (where t2 = t4/2), and the second frame is from t2 to t4. In the second frame, the polarity of the voltage applied to the liquid crystallayer is inverted in order to prevent the deterioration. The section time interval in the first frame is t=0 tot1, and the selection time interval in the second frame is from two tot3. The on and off states of picture elements is determined by signals which are applied to the signal electrodes while the scanning electrodes are selected: that is, the on and off states are not determined by signals which were applied to the signal electrodes while the scanning electrodes are not selected.

The ratio of a time interval in which one scanning electrode is selected to one period, i.e.(t1 + (t3 - t2))/t4 in Figure 14(a) is the so-called drive duty. Therefore, in the case where the number of scanning electrode is N and each scanning electrode is scanned independently, the drive duty is 1/N. Figures 14(b) to 14(c) illustrate a signal applied to a signal electrode selected in a full period and a signal applied to a signal electrode not selected, respectively. The voltage waveforms which, in this case, are applied between the scanning electrode and the signal electrodes are as shown in Figures 14td) and 14(e) respectively. The effective voltages applied to picture elements in on and off states are obtained from the above-described expression.

In the case where the dot matrix display section is driven with a drive duty of 1/8 Eon = < Vo/3 and Eoff = Vo/3 (where a = 3).

When the conventional multiplex drive as described above is applied to a 1/4 duty drive of a 7-segment display section, Eon = vVJ3. A means of allowing this value to coincide with the Eon effective voltage of the dot matrix display section will be described as follows.

Figures 15(a) to 15(e) illustrate drive voltage waveforms for the 7-segment display section. Figure 15(a) shows one example of a signal which is applied to the common electrodes. One period of this signal is from t = o tot'5. In one period, the first frame is from t=0 to a, and the second frame is from a tot'5. The selection time intervals in the first and second frames are from t=0 tot'1 and from t=t'3 tot'5 respectively. In the time interval t'2 - a of the first frame and in the time interval t'4 - t'5 of the second frame, the effective voltage is zero irrespective of selection and non-selection. Figure 15(c) shows a signal which is selected in the time interval 0 - t'2 and is not selected in the time interval a - t'4. In this case, voltage waveforms as shown in Figures 15(d) and 15(e) are applied to the common electrodes and the segment electrodes.

In order to make the on state effective voltage in the case where the 7-segment display section has a duty of 1/4 equal to that in the case where the dot matrix display section has a duty of 1/8, the ratio of the time interval in which one common electrode is selected to one period, i.e.

t1 + (t'3 - a) t'5 is set to 1/6, and the ratio of a time interval in which the effective voltage. is set to zero, i.e.

(a1 - t'2) + (t'5 - t'4) t'5 is set to 2/6. Then the on state effective voltage is WVJ3 which is equal to that of the dot matrix display section. The off state effective voltage is

which is lower than the ordinary 1/4 duty drive effective voltage, and therefore half tones rarely occur even at low angles of vision.

Figure 16 shows a circuit for producing the signals applied to the common electrodes. The circuit comprises a power source circuit 71, three voltage level converting multiplexers 72, two liquid crystal AC drive multiplexers 73, and four analog multiplexers 74. In Figure 16, reference letter W designates a signal whose level is changed every frame. That is, the signal W is at a low level in the first frame (0 - a in Figure 15 (a)) and at a high level in the second frame (a - t'5 in Figure 15(a)). Further in Figure 16 reference letter Go designates a signal to control the time intervals (t'2 - a, and t'4 - t'5 in Figure 15(a)) in which the effective voltage is set to zero and the signal is at a high level for the time intervals.In Figure 16, reference letters G1, G2, G3, G4 designate signals which control the common electrodes COM1, COM2, COM3, COM4 respectively.

These signals G1 to G4 are at high level while they select the respective common electrodes. The description of the segment electrode signals will be omitted because the segment electrode signals can be provided in the same manner.

As will be apparent from the above description where a liquid crystal display device has a dot display section and a 7-segment display section the time intervals in which the effective voltage is set to zero is provided to make the on state effective voltages almost equal. The liquid crystal display device can be observed with ease and has a beautiful appearance. Thus the liquid crystal display device can be used in a wrist watch where design and visual appearance is all important.

Claims

1. An electronic timepiece comprising: a time standard signal generating circuit for producing a time standard signal; a frequency divider circuit for frequency dividing the time standard signal; a driving circuit connected to receive output signals from the divider circuit; a display device driven by the driving circuit to display time information, the display device comprising a 7-segment digital display section and a dot matrix display section; and a circuit for generating a display of characters and/or pictures on the dot display section illustrating function modes of the electronic timepiece.

2. An electronic timepiece as claimed in claim 1 in which the 7-segment display section and the dot matrix display section are composed of liquid crystal display elements, electrochromic display elements or photodiode display elements and may be the same or different.

3. An electronic timepiece as claimed in claim 1 in which the 7-segment display section and the dot matrix display section are parts of the same liquid crystal display panel.

4. An electronic timepiece as claimed in claim 1 in which the 7-segment display section is constituted by one layer of a multilayer liquid crystal display panel and the dot matrix display device is constituted by a second layer thereof.

5. An electronic timepiece as claimed in any preceding claim in which the driving circuit is such that, in operation, the display device is driven by multiplex drive signals, the duty of the drive signals applied to the 7-segment display section being different from the duty of the drive signals applied to the dot matrix display section.

6, An electronic timepiece as claimed in any preceding claim including a switch circuit which switches the characters and/or pictures on the dot display section in synchronism with the output of a function counter circuit.

7. An electronic timepiece as claimed in claim 1 in which the display device comprises signal electrodes of the dot display section and segment electrodes of the 7-segment display section formed on one substrate, scanning electrodes of the dot display section and common electrodes of the 7-segment display section formed on a second substrate, and a liquid crystal layer disposed between the substrate, the signal electrodes and the scanning electrodes forming picture elements of the dot display section and the segment electrodes and common electrodes forming picture elements of the 7-segment display section, the driving circuit being so arranged that, in operation, the effective voltage applied to energise the picture elements of the dot display section substantially equal to the effective voltage applied to energise picture elements of the 7-segment display section, by ensuring that a segment signal applied to the segment electrodes and a common signal applied to the common electrodes have the same potential at least once during a frame interval.

8. An electronic timepiece substantially as herein described with reference to and as shown in the accompanying drawings.

9. An electronic timepiece comprising a standard signal generating circuit, a frequency division circuit, a time counter circuit, a display decoder circuit, display elements, external operating means, and a battery, characterised in that in addition to 7-segment type digit display section, a dot matrix section is provided, and a circuit is provided with carries out function mode displays by displaying characters or pictures on said dot matrix section.

10. A liquid crystal display device in which a plurality of segment electrodes and signal electrodes are provided on one substrate, a plurality of common electrodes and scanning electrodes are provided on the other substrate, to perform segment display and dot matrix display, said segment display and dot matrix display being multiplex driven with different drive duties, characterised in that the effective voltage applied to the ON picture elements of said segment display and of said dot matrix display are made almost equal by making the effective voltage of said segment display device low by means of the segment signal and the common signal which come in the same electric potential at least once during one frame interval.