GB2073519A - Complementary metal oxide semiconductor integrated circuit including a voltage regulator for a section operated at low voltage - Google Patents

Complementary metal oxide semiconductor integrated circuit including a voltage regulator for a section operated at low voltage Download PDF

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Publication number
GB2073519A
GB2073519A GB8011323A GB8011323A GB2073519A GB 2073519 A GB2073519 A GB 2073519A GB 8011323 A GB8011323 A GB 8011323A GB 8011323 A GB8011323 A GB 8011323A GB 2073519 A GB2073519 A GB 2073519A
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Prior art keywords
transistor
low voltage
node
supply terminal
voltage
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GB8011323A
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GB2073519B (en
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National Semiconductor Corp
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National Semiconductor Corp
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Classifications

    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/24—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only
    • G05F3/242—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage
    • G05F3/247—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage producing a voltage or current as a predetermined function of the supply voltage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Nonlinear Science (AREA)
  • Electromagnetism (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

A CMOS integrated circuit includes a high voltage section operable in a range from 3 to 15 volts and a low voltage section which is operated at a voltage corresponding to the sum of the thresholds of a P-channel and an N-channel field effect transistor. This voltage is developed between one of the supply terminals for the circuit and a node which is connected directly or indirectly to the low voltage section and is also connected by way of a voltage regulator, constituted by a transistor which acts as a current sink, to the other supply terminal for the high voltage section. The low voltage section is thereby always operated at an optimum voltage, the aforementioned sum of the threshold voltages, irrespective of variations in manufacturing tolerances. Accordingly even though the integrated circuit includes a low voltage section it can be operated throughout the normal range of voltages for CMOS circuits as if it contained only "high voltage" devices. <IMAGE>

Description

SPECIFICATION Complementary metal oxide semiconductor. integrated circuit including a voltage regulator for a section operated at low voltage This invention relates to integrated circuits and particularly to complementary metal oxide semiconductor circuits. Such circuits employ N-channel transistors and P-channel transistors in various networks that have many desirable qualities. Such circuits can normally operate from supply voltages ranging from 3 to 15 volts; they may tolerate a supply voltage as great as 18 volts. In order to facilitate the increase of density of components on a given area of chip, it has been proposed to reduce the spacing between the various devices which a circuit contains to provide a new class of devices commonly known as high density, low voltage CMOS devices. They normally operate from a supply voltage which has an upper limit of about 7 volts.These figures for supply voltage are given by way of example and it is not intended to limit the invention to them. Merely by way of example, the differences between "high voltage" and "low voltage" devices may be seen by consideration of United States Patent Specification No 3983620 and, in particular, Figures 15 and 19 thereof. The major difference between the "high voltage" structure shown in the former Figure and the low voltage structure shown in the latter Figure is that in the "low voltage" construction, the space between N+ guard rings and P+ regions has been eliminated so as to provide a limit of operating voltage defined by a zener voltage of the P+ to N+ junctions.
The lower limit of operating voltage for a CMOS circuit is determined by the higher of the threshold voltages of the P-channel transistors and N-channel transistors employed in it. The optimum voltage is equal to the sum of the thresholds for the P-channel and N-channel transistors in the circuit. However, the sum of the thresholds varies from circuit to circuit by reason of variations in the manufacturing process. It is the object of the present invention to facilitate the use of a high voltage section and a low voltage section in an integrated circuit by compensating automatically for those variations, due normally to manufacturing tolerances, in threshold voltages of the low voltage section of the circuit.
According to the invention, a complementary metal oxide semiconductor integrated circuit contains first section disposed for operation at a relatively high voltage and a second section disposed for operation at a relatively low voltage, the circuit having two supply terminals of which one is common to the first and second sections, includes a network comprising two transistors of different conductivity type connected to provide a voltage equal to the sum of their threshold voltages, the circuit being arranged to supply this voltage to the second section for the operation thereof.~ Reference will now be made to the accompanying drawings in order to describe by way of example several embodiments of the invention.In the draw ings: Figure 1 is a schematic diagram of one embodi mentofthe invention; Figure 2 is a diagram of the second embodiment of the invention; Figure 3 is a schematic diagram of a modification of the embodiment shown in Figure 2; and Figure 4 is a schematic representation, shown in section, of part of a semiconductive chip, to illustrate the physical construction of part of the circuit shown in Figure 3.
The circuit shown in Figure 1 has two terminals 10 and 11 constituted by power supply rails. They are marked +VDD and -Vss respectively to denote the positive and negative potentials of the external voltage supply. A node 12, of potential V'ss, constitutes a second supply terminal for a low voltage section 13 connected between the node 12 and the supplyterminal 10 which is thereby common to first the low voltage section and the high voltage section of the circuit.
Between the supplyterminals 10 and 11 is connected a network comprising fourtransistors 14, 15, 16 and 17 and a resistor 18. This network may be regarded as forming part of the high voltage section of the integrated circuit which, in general, is not shown but is feed from the terminals 10 and 11.
The transistor should be constructed for operation at "high voltage", that is to say between 3 and 15 volts, butthetransistors 14,15 and 16 may be constructed for either "high voltage" or "low voltage" as desired.
The network offourtransistors and a resistor constitute a voltage regulator. The transistors 14 and 16 are arranged so that their gates are connected to their respective drain electrodes and are coupled in series with a resistor 18 between the supply terminals 10 and 11. The resistor 18 should be of high resistance, typically between 1 and 5 megohms, so that only a very small current, of the orderofa few microamperes, flows in the transistors 14 and 16.
The source-dra in circuits of the transistors 15 and 17 are connected in series between the supply terminals 10 and 11. The gate of the transistor 15 is biassed by the voltage drop across the transistor 14 whereas the gate of transistor 17 is biassed by the voltage drop across the transistor 16. The transistors 14 and 15 preferably have their substrate connections returned to their respective source electrodes so that they are substantially free of "body effect".
The voltage drop across the transistor will be one threshold voltage for a P-channel transistor. Owing to the action of the transistor 15, the potential at the node 12 will be at the threshold voltage of an N-channel transistor below the potential of the drain electrode of transistor 14. Thus the difference in potential between the node 12 and the supply terminal 10 will be the sum of the thresholds of a P-channel transistor and an N-channel transistor.
The transistor 17 constitutes a currentsinkwhich conducts the currents flowing through the transistor 15 and the low voltage section 13.
If the potential of the node 12 should tend to vary, for example as a result in a change of the current flowing in the section 13, the conduction of the trans- istor 15 will vary in compensation. In effect, the transistor 15 appears, from node 12, to be a source follower. Thereby the current in the transistor 17 is maintained substantially constant The transistor 15 must have a current carrying capacity sufficient to accommodate the changes of current in the section 13 and the transistor 17 must be of sufficient current carrying capacity to accommodate the total power flowing through the section 13 and the transistor 15.
The transistors 14 and 16 can be of much lessercur rent carrying capacity, and therefore of much smal ler physical size; their function is to provide a bias only and they need only conduct the very small cur rent that flows through the resistor 18 when the sup ply voltage is a maximum. Most of the supply voltage will appear across the resistor 8.
Figure 2 illustrates an embodiment which is arranged to develop a different voltage corresponding to the sum of the thresholds of a P-channel and N-channel transistor that differs from the embodiment of Figure 1 in that this voltage is supplied indi directly to the low voltage section. In the embodiment shown in Figure 2, there are complementary transis- tors 20 and 21 which have their gate electrodes coupled to their respective drains and are connected in series to develop, at a node 25, a potential differs from the potential of the supply terminal 10 by the sum of the threshold voltages of the two transistors.
The current which flows in the transistors 20 and 21 also flows through a transistor 22, connected in series with them, and a resistor 24, which connects the drain of the transistor 22 to the negative supply terminal 11. The potential of the gate of the transistor 22 will be three threshold voltages below the potential of the positive supply terminal. This gate is connected directly to the gate of a source follower transistor 23 of which the source is connected to the node 12 forthe low voltage section 13 and of which the drain is connected to the negative supply terminal. Since the transistors 22 and 23 are of the same conductivity type, their thresholds will be substantially equal, and will cancel so that the potential of the node 12 is for practical purposes at the potential of the node 25.The transistor 23 acts as a source follower for this purpose.
In the circuit of Figure 2, the current flowing through the resistor 24 varies according to the voltage between the terminals 10 and 11. Although the current is small, the variability of it is a slight disadvantage. Figure 3 illustrates a modification in which the variation is substantially reduced. The circuit of Figure 3 is the same of that shown in Figure 2 except thatthe resistor24 has been supplanted byajunc- tion field effect transistor 26. In this embodiment the junction field effect transistor is P-channel device which, as shown, has its source-drain circuit coupled in series with the transistors 20, 21 and 22. The gate of the transistor 26 is biassed to ensure conduction of this transistor and is for this purpose connected to the positive supply terminal.The gate-to-source potential of the resistor 26 is fixed at about three threshold voltages, namely the threshold voltages of transistors 20,21 and 22, below the positive supply terminal, the conduction of the transistor will decrease as the source to drain voltage increases.
Thus even Though the supply voltage may vary quite widely, for example between 3 and 15 volts, there will be very little change in the flow of current through the junction field effect transistor. The lack of variation in the current flow is desirable and helps to stabilize the bias voltages of the transistors 20, 21 and 22. It is moreover that is in practice to fabricate a junction field effecttransistor in a CMOS circuit The length to width ratio of this transistor should of course be large enough to accommodate the desired current; a ratio of the order of 100 to 1 is suitable in normal practice.
Figure 4 illustrates schematically the physical construction of the transistors 20, 21. 22 and 26 of Figure 3. The drawing is intended only to illustrate the layout of the respective part of the chip and by way of explanation only. The upper oxide and metallization layers have been omitted and the interconnections of the circuit are shown schematically. Moreover, the particular illustration is for a low voltage circuit. The "chip" partly shown in Figure 4 has an N-type substrate 30. The transistor 20 comprises a pairofdif- fused P+ regions 31 and 32 for constituting the source and drain regions of this transistor. A N+ guard ring 33 surrounds the transistor and is connected to the source 31 to provide an ohmic connection to the substrate 30 which is coupled to the positive supply terminal.A gate electrode 34 is connected to the drain region 32 and to the transistor 21.
This transistor, which is an N-channel transistor, is fabricated into a P-well 35 which is ringed by a P+ guard ring 36. A drain 37 is connected to transistor 20 and to a gate electrode 39. A source region 38 is connected to the guard ring 36 and to transistor 22.
This transistor is a P-channel transistor with construction like that of transistor 20 and includes a source region 40 connected to the transistor 21 and a drain region 41 connected to a gate 43 and to transistor 26. The transistor 22 has a guard ring 42.
The junction field effect transistor 26 is constituted by a P-channel 45 fabricated from a P-well diffusion similar to the well 35. The channel is made very narrow and is capped by a gate 46 which is an N+ diffusion similar to that used for the guard rings 33 and 42. The top gate is directly and ohmically connected to the substrate 30. A channel 45 terminates in a P+ diffusion 47 which constitutes its source and is connected to the transistor 22. The other end of the channel 45 will normally terminate in a second P+ diffusion which constitutes the drain region and would be connected to the negative supply. The length of the channel is made long enough to produce the desired conductivity for the transistor 26.

Claims (9)

1. Acomplementary metal oxide semiconductor integrated circuit which contains a first section constructed for operation from a comparatively high voltage supply and a second section constructed for operation from a comparatively low voltage supply, the two sections having a common supply terminal and there being a second supply terminal for the high voltage section, the circuit including a network which is fed from the said two supply terminals and includes a P-channel transistor and an N-channel transistor arranged to develop'a voltage equal to the sum of the threshold voltages thereof, the network being arranged to apply this voltage to the low voltage section for the operation thereof.
2. A circuit according to claim 1, in which the aforementioned voltage for the low voltage section is developed between the-said common supply terminal and a node which is directly or indirectly coupled to the low voltage section and means are provided for stabilising the potential atthis node relative to the potential at the common supply terminal.
3. A circuit according to claim 2 in which the node is connected to the common supply terminal through a transistor which is constituted by one of the aforementioned transistors operating as a source follower and a further transistor is connected between the node and the other supply terminal so as to provide stabilisation of the potential at the node and to conduct the current through the source follower and the low voltage section.
4. A circuit according to claim 2 in which the network includes two transistors of substantially equal threshold voltages arranged to transfer the potential at the node to a further node constituting a second supply terminal for the low voltage section, one of these transistors constituting an active source follower for stabilising the potential at the latter node.
5. A circuit according to claim 4 in which the source follower transistor is connected between the further node and the second supply terminal for the circuit, the other transistor being connected in series with the first two mentioned transistors and is connected via an active or passive resistance to the second supply terminal for the circuit.
6. Acircuit substantially as hereinbefore described with reference to Figure 1 of the accompanying drawings.
7. A circuit substantially as hereinbefore described with reference to Figure 2 of the accompanying drawings.
8. A circuit substantially as hereinbefore described with reference to Figure 3 of the accompanying drawings.
9. A circuit substantially as hereinbefore described with reference to Figures 3 and 4 of the accompanying drawings.
GB8011323A 1980-04-03 1980-04-03 Complementary metal oxide semiconductor integrated circuit including a voltage regulator for a section operated at low voltage Expired GB2073519B (en)

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Application Number Priority Date Filing Date Title
GB8011323A GB2073519B (en) 1980-04-03 1980-04-03 Complementary metal oxide semiconductor integrated circuit including a voltage regulator for a section operated at low voltage

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Application Number Priority Date Filing Date Title
GB8011323A GB2073519B (en) 1980-04-03 1980-04-03 Complementary metal oxide semiconductor integrated circuit including a voltage regulator for a section operated at low voltage

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GB2073519A true GB2073519A (en) 1981-10-14
GB2073519B GB2073519B (en) 1984-04-18

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2207315A (en) * 1987-06-08 1989-01-25 Philips Electronic Associated High voltage semiconductor with integrated low voltage circuitry
EP0337747A1 (en) * 1988-04-12 1989-10-18 Nec Corporation Circuit for producing a constant voltage
WO1995019046A1 (en) * 1994-01-10 1995-07-13 Carnegie Mellon University Four rail circuit architecture for ultra-low power and voltage cmos circuit design
US5814845A (en) * 1995-01-10 1998-09-29 Carnegie Mellon University Four rail circuit architecture for ultra-low power and voltage CMOS circuit design
US6366061B1 (en) 1999-01-13 2002-04-02 Carnegie Mellon University Multiple power supply circuit architecture

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2207315A (en) * 1987-06-08 1989-01-25 Philips Electronic Associated High voltage semiconductor with integrated low voltage circuitry
GB2207315B (en) * 1987-06-08 1991-08-07 Philips Electronic Associated High voltage semiconductor with integrated low voltage circuitry
EP0337747A1 (en) * 1988-04-12 1989-10-18 Nec Corporation Circuit for producing a constant voltage
WO1995019046A1 (en) * 1994-01-10 1995-07-13 Carnegie Mellon University Four rail circuit architecture for ultra-low power and voltage cmos circuit design
US5814845A (en) * 1995-01-10 1998-09-29 Carnegie Mellon University Four rail circuit architecture for ultra-low power and voltage CMOS circuit design
US6366061B1 (en) 1999-01-13 2002-04-02 Carnegie Mellon University Multiple power supply circuit architecture

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