GB2069756A - Arrangement of diodes integrated on an insulating substrate - Google Patents
Arrangement of diodes integrated on an insulating substrate Download PDFInfo
- Publication number
- GB2069756A GB2069756A GB8102334A GB8102334A GB2069756A GB 2069756 A GB2069756 A GB 2069756A GB 8102334 A GB8102334 A GB 8102334A GB 8102334 A GB8102334 A GB 8102334A GB 2069756 A GB2069756 A GB 2069756A
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- GB
- United Kingdom
- Prior art keywords
- semiconductor regions
- regions
- semiconductor
- ones
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/764—Air gaps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
- H01L21/76283—Lateral isolation by refilling of trenches with dielectric material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
- H01L21/76289—Lateral isolation by air gap
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
A semiconductor device comprises an insulating layer (10), a first p-type region (12-1) and a first n-type region (12-2) formed on the insulating layer to constitute a first diode, and a second p-type region (12-4) and a second n- type region (12-3) to constitute a second diode. The first p-type region (12-1) abuts on the second n-type region (12-3) and is isolated from the second p-type region (12-4), while the first n-type region (12-2) abuts on the second p-type region (12-4) and is isolated from the second n-type region (12-3). The isolation may be a gap 14 in the semiconductor layer or a solid portion of insulation material. Electrodes 18, 20 short these pin junctions in an array of such devices which are not required. <IMAGE>
Description
SPECIFICATION
Semiconductor device
This invention relates to a semiconductor device having a plurality of pn junctions in a polycrystalline silicon layer.
Diodes have hitherto been formed in a polycrystal line silicon layer on an insulating layer by doping the polycrystalline silicon layer with different impurities.
Since the diodes this type can be formed between or over semiconductor elements such as resistors, diodes, transistors formed in a monocrystalline silicon substrate, a semiconductor device having the diodes formed in its polycrystalline silicon layer can enjoy a higher integration degree than that of a semiconductor device in which the diodes are formed together with other semiconductor elements in a monocrystalline silicon substrate.
Conventionally, a bidirectional diode circuit including two diodes 1 and 2 of opposite polarities connected in parallel with each other as shown in
Figure 1 is constructed by a semiconductor device as shown in Figures 2 and 3, for example. As is clearly shown in Figure 3, the diode 1 is formed by electrically connecting both a collector region 3 and a base region 4 of a transistor structure with an electrode 5 and connecting an emitter region 6 with an electrode 7. The diode 2 is formed in like manner, and is spaced from the diode 1. The two diodes 1 and 2 are connected by means of conductive layers Band 9.
In the conventional semiconductor device of this type, however, the connection of the separately formed diodes requires relatively large space or area to be covered.
The object of this invention is to provide a semiconductor device having a plurality of pn junctions and relatively limited in area covered.
In an aspect of this invention, there is provided a semiconductor device comprising an insulating layer, a plurality of first semiconductor regions of one conductivity type formed on the insulating layer, #a plurality of second semiconductor regions of a conductivity type opposite to that of the first semiconductor regions formed on the insulating layer to constitute a plurality of pn junctions in cooperation with the first semiconductor regions, at least two of the first semiconductor regions and at least two of the second semiconductor regions alternately adjoining one another to be arranged in the form of a closed loop.
According to this invention, a specified diode circuit can be made out of a relatively compact semi-conductor device by arranging semiconductor regions of different conductivity types in the form of a closed loop and short-circuiting undesired pn junctions by means of conductive layers.
This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which:
Figure 1 is a circuit diagram of a well-known bidirectional diode circuit;
Figure 2 is a plan view of a prior art semiconductor device constituting the bidirectional diode circuit shown in Figure 1;
Figure 3 is a sectional view of the semiconductor device as taken along line Ill-Ill in Figure 2;
Figure 4 is a plan view of the semiconductor device according to an embodiment of this invention constituting a bidirectional diode circuit shown in
Figure 1,
Figure 5 is a sectional view of the semiconductor device as taken along line V-V in Figure 4;
Figure 6 is a sectional view of the semiconductor device as taken along line VI-VI in Figure 4;;
Figures 7 and 8 are modifications of the semiconductor device shown in Figures 4 to 6;
Figure 9 is a plan view of a semiconductor device according to another embodiment of the invention;
Figure 10 is a circuit diagram of a conventional muting control circuit provided with a bidirectional diode circuit;
Figure 11 is a plan view of a semiconductor device according to an embodiment of the invention constituting the bidirectional diode circuit used in the muting control circuit of Figure 10; and
Figure 12 is a plan view of a semiconductor device according to a further embodiment of the invention.
Figures 4 to 6 show a semiconductor device according to an embodiment of this invention. The semiconductor device is provided with an insulating substrate 10 and a semiconductor region 12 formed on the insulating substrate 10. The semiconductor region 12 is made up by forming a polycrystalline silicon layer on the insulating substrate 10 by e.g.
chemical vapor deposition (CVD) technique, selectively removing the central portion of the polycrystalline silicon layer by e.g. plasma etching method to form a space section 14, and then selectively doping regions 12-1 to 12-4 quartered by two lines intersecting at right angles at the space section 14 with p-and n-type impurities by e.g. ion implantation method. In this embodiment, the regions 12-1 and 12-4 are p-type regions, while the regions 12-2 and 12-3 are n-type regions. An insulating layer 16 is formed on the semiconductor region 12, and metal electrodes 18 and 20 electrically connecting the p- and n-type regions 12-1 and 12-2 respectively with the n- and p-type regions 12-3 and 12-4 are also formed on the semiconductor region 12 through contact holes defined in the insulating layer 16.
Here it is to be noted that the regions 12-1 to 12-4 are arranged in the form of a closed loop. Namely, the p-type region 12-1 abuts on the n-type region 12-2 to form a pn junction area, and abuts on and is electrically connected with the n-type region 12-3 by means of the metal electrode 18. On the other hand, the p-type region 12-4 abuts on the n-type region 12-3 to form a pn junction area, and abuts on and is electrically connected with the n-type region 12-2 by means of the metal electrode 20. Further, the p-type region 12-4 is isolated from the p-type region 12-1 by the space 14. The equivalent circuit of the semiconductor device shown in Figures 4 to 6 is identical with the one shown in Figure 1.The semiconductor device of Figures 4 to 6 can, however, be miniaturized by reducing the size of the space 14 for isolating the p- and n-type regions 12-1 and 12-2 respectively from the p- and n-type regions 12-4 and 12-3. For example, the space 14 can be given dimensions of 2y x 21l to 4Ft x 4u by plasma etching.
In this case, the area covered by the semiconductor device can be reduced to 10fit x 10#to to20fat x 20fit.
Figures 7 and 8 are sectional views of a semiconductor device according to another embodiment of the invention, and respectively correspond to the drawings of Figures 5 and 6. Like the semiconductor device shown in Figures 4 to 6, the semiconductor device of this embodiment has four semiconductor regions formed on an insulating layer 10. In the semiconductor device of Figures 4 to 6, the polycrystalline silicon layer is removed in the space 14 and dead regions. In this embodiment, however, portions of a polycrystalline silicon layer located in those regions are selectively oxidized to form oxide layers. Namely, a silicon oxide region 22 as an isolation region is formed in place of the space 14, and a silicon oxide layer 24 is formed on the periphery of the four regions including the regions 12-2 to 12-4.The semiconductor device of Figures 7 and 8 can also be miniaturized since the regions 12-1 and 12-2 can be isolated respectively from the regions 12-4 and 12-3 by means of the relatively small silicon oxide region 22.
Figure 9 is a plan view of a semiconductor device according to still another embodiment of the invention. This semiconductor device is provided with a semiconductor region 32 which is formed on an insulating layer in the same manner as the semiconductor region 12 of the semiconductor device shown in Figures 4to 6. The semiconductor region 32 includes a plurality of p- and n-type regions 32-11 to 32-44 alternately adjoining one another in both vertical and horizontal directions to be arranged in the form of a matrix. If the regions 32-22 is of the p-type, then the region 32-11, 32-13,32-31 and 32-33 are of the p-type, and the regions 32-12,32-21,32-23 and 32-32 are of the n-type. A desired diode matrix circuit can be made up by selectively forming electrodes on the p- and n-type regions formed in the aforesaid manner.
Figure 10 shows a well-known control circuit used in a muting circuit including a bidirectional diode circuit 40. In this control circuit, current sources 42 and 44 are each composed of a differential amplifier circuit which receives a reference voltage at one input terminal thereof and a control voltage atthe other input terminal. As the control voltage is changed, currents flowing through the current sources 42 and 44 take values (10 + Alto) and (10 hit), respectively. Here AlO varies with the variation of the control voltage. By thus changing the control voltage to vary the currents flowing through the current sources 42 and 44, currents flowing through diodes 40-1 to 40-4 of the diode circuit 40 are controlled.Output voltages at output terminals V1 and V2 are controlled in accordance with the currents flowing through these diodes 40-1 to 40-4. The output voltages from the output terminals V1 and
V2, together with an output voltage at an output terminal V3, are used to control a muting switch circuit (not shown).
Figure 11 a semiconductor device constituting the bidirectional diode circuit 40 used in the control circuit shown in Figure 10. This semiconductor device includes n-type regions 40-5 to 40-7, p-type regions 40-8 to 40-10, and conductive layers 40-11 to 40-13. The n-type region 40-5 abuts on the p-type region 40-9 to constitute the diode 40-1, the p-type region 40-8 abuts on the n-type region 40-6 to constitute the diode 40-2, the n-type region 40-7 abuts on the p-type region 40-9 to constitute the diode 40-3, and the p-type region 40-10 abuts on the n-type region 40-6 to constitute the diode 40-4.The conductive layer 40-11 electrically connects the regions 40-5 and 40-8 with the output terminal V1, the conductive layer 40-12 electrically connects the regions 40-6 and 40-9 with the output terminal V3, and the conductive layer 40-13 electrically connects the regions 40-7 and 40-10 with the output terminal
V2. Further, the regions 40-6 and 40-9 are electrically isolated from the regions 40-5 and 40-8, respectively, by an isolation region 40-14, and also isolated from the regions 40-7 and 40-10, respectively, by an isolation region 40-15.The semiconductor device shown in Figure 11 can be made far smaller than a device obtained by forming all the semiconductor elements of the circuit of Figure 10 in a monocrystalline silicon layer, since it can be formed on an insulating layer under which a semiconductor structure intended to constitute other semiconductor elements in the circuit of Figure 10 is formed.
Although illustrative embodiments of this invention have been described in detail herein, the invention is not limited to those precise embodiments. For example, the semiconductor region 12, which is divided into four sections in the embodiment of Figure 4, may be divided in some other number, e.g. six. Further, the isolation regions 14 and 22 may be of any other suitable shapes. Instead of using the conductive layer 40-12 in the embodiment of Figure 11, moreover, conductive layers may be provided separately for the p- and n-type regions to form a diode full-wave rectifier circuit. Such diode full-wave rectifier circuit can be obtained by dividing the semiconductor region 12 into six sections and selectively forming the conductive layers on the semiconductor region 12, as shown in Figure 12. In
Figure 12, regions 40-1 to 40-3 are of the p-type, while regions 40-4 to 40-6 are of the n-type. Further, a conductive layer 40-7 electrically connects the regions 40-1 and 40-4, and a conductive layer 40-8 electrically connects the regions 40-3 and 40-6. In this full-wave rectifier circuit, an AC input current is supplied to the conductive layers 40-7 and 40-8, and a DC output current is taken out from the conductive layers 40-2 and 40-5.
Claims (8)
1. A semiconductor device comprising:
an insulating layer;
a plurality of first semiconductor regions of one conductivity type formed on said insulating layer; and
a plurality of second semiconductor regions having a conductivity type opposite to that of said first semiconductor regions and formed on said insulat ing layer so as to constitute a plurality of pn junction areas in cooperation with said first semiconductor regions,
at least first and second ones of said first semiconductor regions which are separated from each other and at least first and second ones of said second semiconductor regions which are separated from each other being formed alternately in contact with one another to form a closed loop.
2. A semiconductor device according to claim 1, wherein a third one of said first semiconductor regions is formed in contact with the second one of said second semiconductor regions and is isolated from the first one of said first semiconductor regions, and a third one of said second semiconductor regions is formed in contact with the first and third ones of said first semiconductor regions and is isolated from the second one of said second semiconductor regions.
3. A semiconductor device according to claim 2, further comprising insulation regions formed in areas selectively defined by the first to third ones of said first semiconductor regions and the first to third ones of said second semiconductor regions.
4. A semiconductor device according to claim 2 or 3, further comprising conductive layers electrically connecting the first to third ones of said first semiconductor regions with the second, first and third ones of said semiconductor regions, respectively.
5. A semiconductor device according to claim 1, further comprising an insulation region formed in an area defined by the first and second ones of said first semiconductor regions and the first and second ones of said second semiconductor regions.
6. A semiconductor device according to claim 1 or 5, further comprising conductive layers electrically connecting the first and second ones of said first semiconductor regions with the second and first ones of said second semiconductor regions, respectively, to constitute a bidirectional diode circuit.
7. A semiconductor device comprising:
an insulating layer;
a plurality of first semiconductor regions of one conductivity type arranged on said insulating layer at spaces from one another along a plurality of lines; and
a plurality of second semiconductor regions having a conductivity type opposite to that of said first semiconductor regions and arranged on said lines at spaces from one another between said first semiconductor regions and adjoining said first semiconductor regions,
each of said first semiconductor regions and each of said second semiconductor regions respectively adjoining their corresponding ones of said second and first semiconductor regions on each two adjacent lines.
8. A semiconductor device, substantially as hereinbefore described with reference to Figures 4 to 9 and 11 and 12 of the accompanying drawings.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1752080A JPS56114381A (en) | 1980-02-15 | 1980-02-15 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| GB2069756A true GB2069756A (en) | 1981-08-26 |
| GB2069756B GB2069756B (en) | 1984-10-10 |
Family
ID=11946223
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB8102334A Expired GB2069756B (en) | 1980-02-15 | 1981-01-26 | Arrangement of diodes integrated on an insulating substrate |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JPS56114381A (en) |
| DE (1) | DE3104192A1 (en) |
| GB (1) | GB2069756B (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5879746A (en) * | 1981-11-05 | 1983-05-13 | Nec Corp | Semiconductor integrated circuit |
| JP2649359B2 (en) * | 1986-10-08 | 1997-09-03 | 日本電装株式会社 | Method for manufacturing semiconductor device |
| US5077595A (en) * | 1990-01-25 | 1991-12-31 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device |
| JP2803565B2 (en) * | 1994-04-15 | 1998-09-24 | 株式会社デンソー | Method for manufacturing semiconductor device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS51118378A (en) * | 1975-04-10 | 1976-10-18 | Matsushita Electric Ind Co Ltd | Semiconductor unit |
-
1980
- 1980-02-15 JP JP1752080A patent/JPS56114381A/en active Pending
-
1981
- 1981-01-26 GB GB8102334A patent/GB2069756B/en not_active Expired
- 1981-02-06 DE DE19813104192 patent/DE3104192A1/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS56114381A (en) | 1981-09-08 |
| DE3104192C2 (en) | 1987-01-29 |
| GB2069756B (en) | 1984-10-10 |
| DE3104192A1 (en) | 1981-12-10 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 746 | Register noted 'licences of right' (sect. 46/1977) | ||
| PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 19970126 |