JPH0734482B2 - Optically coupled semiconductor relay device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a semiconductor relay device, and more specifically,
The present invention relates to a semiconductor relay device including a light emitting unit that performs a blinking operation and a light receiving unit that performs a switching operation based on the blinking operation of the light emitting unit, the light emitting unit and the light receiving unit being electrically isolated and optically coupled.

2. Description of the Related Art In recent years, the operation of a machine having a drive device is often controlled by a computer. In general, a control circuit of a computer operates with a DC voltage of about 5V, whereas a machine having the driving device has, for example, 100V.
There are some that operate with commercial AC voltage. As described above, transmission and reception of signals between two circuits having different operating voltages must be performed in an electrically isolated state. Therefore, in such a case, for example, an electromagnetic relay device or an optically coupled semiconductor relay device is used.

In the electromagnetic relay device, the two circuits are magnetically coupled by a coil and perform a relay operation with a mechanical operation. Therefore, the electromagnetic relay device does not always operate in a good state due to mechanical fatigue and the like, and has a limited life, and the device itself is large. Further, in recent years, small-sized, lightweight, long-life solid-state relay elements are becoming popular in place of the electromagnetic relay device. For example, a solid state relay element called SSR (Solid State Relay) can obtain a large power gain, but it must be used separately for AC and DC, which is inconvenient.

On the other hand, a MOS type FET (metal-oxide film-semiconductor type field effect transistor, hereinafter referred to as transistor) is provided inside.
In the optical coupling type solid state relay element having the above, it has a high insulation separation property, a large power gain, is used for both AC and DC, and has a long life. Such an optical coupling type solid state relay element is roughly composed of a light emitting portion and a light receiving portion, a light emitting portion is provided with a light emitting diode (LED), and a light receiving portion is provided with a photodiode and the transistor. It In the optical coupling type solid-state relay element having such a configuration, the light generated by the light emitting diode is received by the photodiode of the light receiving section to perform photoelectric conversion, and the transistor is driven based on the output thereof.

FIG. 26 is a sectional view showing a structure of a light receiving portion 101 of a typical prior art optical coupling type solid state relay element. Receiver 1
01 is a light receiving element 104 having a plurality of photodiodes 103
And a transistor 105, and the light receiving element 104 and the transistor 105 are arranged on the support substrate 102. In the light receiving element 104, the plurality of photodiodes 103 are arranged on the silicon substrate 106, and the plurality of photodiodes 103 are arranged.
Are connected to each other via metal wiring 107.

One ends of the photodiodes 103 connected to each other are connected to a gate electrode 108 of the transistor 105 via a lead wire 109.
, And the other end is led to the outside through an external lead wire 110. On the other hand, the two drain regions 111 and 112 of the transistor 105 are output to the output terminal of the light receiving unit 101 via the two lead wires 113 and 114.

Problems to be Solved by the Invention In the light receiving unit 101, the chip forming the light receiving element 104 and the chip forming the diode 105 are separately disposed on the supporting substrate 102, and lead wires 109 are mutually provided.
Connected through. Therefore, the light receiving unit 101 becomes large. In addition, the light generated by the light emitting unit must be efficiently applied only to the photodiode 103. However, in this light receiving unit 101,
Since the transistor 105 is arranged in parallel with the photodiode 103, the transistor 105 is irradiated with the light, which adversely affects the transistor 105.

Furthermore, in order to set the current capacity of the solid-state relay element large, the input capacity of the transistor 105 must be set large, and for this purpose, the area occupied by the light receiving portion 101 of the transistor 105 must be large. I won't.

On the other hand, if the input capacitance of the transistor 105 is set to a large value, the output voltage of each photodiode 103 will be 0.5V.
Therefore, in order to drive the transistor 105 without lowering the responsiveness, a plurality of photodiodes 103 must be connected and the area occupied by the photodiodes 103 must be increased. Therefore, in the optical coupling type solid state relay element including the light receiving section 101 shown in FIG.
If an attempt is made to set a large current capacity, the original characteristic of being small is lost, and even if compared with an electromagnetic relay device that has become smaller in size in recent years, there is almost no difference.

An object of the present invention is to solve the above-mentioned problems, to provide an optical coupling type semiconductor relay device which is remarkably downsized and which can control conduction / cutoff of a relatively large current.

Means for Solving the Problems The present invention has a light emitting unit and a plurality of input / output electrodes,
An optical coupling type including a light receiving section optically coupled to the light emitting section, and performing a switching operation of electrically connecting / disconnecting between the plurality of input / output electrodes in the light receiving section in response to a blinking operation of the light emitting section. In the semiconductor relay device, the light receiving unit is configured by stacking semiconductor switching means and photodiodes in this order from bottom to top on a semiconductor substrate, and the semiconductor switching element is configured such that a carrier is in a direction perpendicular to a thickness of the semiconductor substrate. Is a lateral metal-oxide film-semiconductor field effect transistor that moves to a region where the photodiode is formed on a semiconductor substrate via an insulating film 19 and on a region between a channel 18 and a drain of the field effect transistor. A photodiode array consisting of a melt-recrystallized silicon film arranged in a plurality of photodiodes connected in series in the same direction Alternatively, a plurality of columns are formed, and as the uppermost layer, at least one of the common wirings that separately connects the electrodes on one side and the electrodes on the other side that are common to each photodiode row, and the common wiring and the channel 18 An upper gate electrode 20, a conductor connecting the one common wiring and the gate electrode to each other, and a source electrode and a drain electrode of the field effect transistor are formed, and based on a voltage from the one common wiring. The drain electrode of the field effect transistor is formed so as to perform a switching operation, which is an optical coupling type semiconductor relay device.

The present invention also includes a light emitting unit and a light receiving unit that has a plurality of input / output electrodes and is optically coupled to the light emitting unit,
An optical coupling type semiconductor relay device which performs a switching operation for conducting / interrupting between the plurality of input / output electrodes in the light receiving section in response to the blinking operation of the light emitting section, wherein the light receiving section is provided on a semiconductor substrate. The semiconductor switching means and the photodiode are laminated in this order from bottom to top, and the semiconductor switching element is a vertical metal-oxide film-semiconductor field effect transistor in which carriers move in the thickness direction of the semiconductor substrate. The photodiode is formed of a melt-recrystallized silicon film which is formed on a semiconductor substrate via an insulating film 19 and arranged on a region other than the opening 73 formed in the gate electrode of the field effect transistor. , One or more photodiode rows in which a plurality of photodiodes are connected in series in the same direction are formed, and each photodiode is used as the uppermost layer. At least one of the common wirings that separately connects the electrodes on the one direction side and the electrodes on the other side that are common to the ion row, the gate electrode 20 on the channel 18, and the one of these Forming a conductor for connecting the common wiring and the gate electrode of the field effect transistor and the source and drain electrodes of the field effect transistor, and the one of the common wiring and the gate electrode, and the one of the common wiring and the gate electrode. A conductor for connecting to and a source and drain electrode of the field effect transistor are formed, and a drain electrode of the field effect transistor is formed on the basis of a voltage from the one common wiring to perform a switching operation. Is an optically coupled semiconductor relay device.

Operation According to the present invention, the light receiving portion is configured by stacking the semiconductor switching means and the photodiode in this order on the semiconductor substrate. As a result, the area occupied by the semiconductor switching means and the photodiode in the light receiving section can be significantly reduced, and the optical coupling type semiconductor relay device can be downsized. The photodiode consists of a melt-recrystallized silicon film. Since the melt-recrystallized photodiode has a high carrier mobility, a sufficient photovoltaic power can be obtained. Further, in the above-mentioned photodiodes, the output voltage obtained from the entire photodiodes can be selected to a desired magnitude by setting the desired number of photodiodes forming each photodiode array. Further, by setting each of the photodiode rows to a desired number, the output current obtained from the entire photodiode can be selected to a desired magnitude.

Further, the current capacity of the semiconductor switching means can be increased corresponding to the large set output voltage of the photodiode, but since the semiconductor switching means and the photodiode are laminated as described above, The overall size is relatively small, and this can be achieved.

In particular according to the invention, the semiconductor switching means are metal-
In the case of an oxide film-semiconductor field effect transistor which is configured horizontally, a photodiode is arranged on a region between the channel and the drain of the field effect transistor, and the semiconductor switching means has a vertical metal-oxide structure. When it is a film-semiconductor type field effect transistor,
By arranging the photodiode on a region other than the area where the gate electrode opening of the field effect transistor is formed, even if the photodiode is melted and recrystallized, batch wiring can be performed at the end. Become.

Example FIG. 8 is a perspective view showing the overall configuration of an optically coupled semiconductor solid state relay element 1 according to an example of the present invention, and FIG. 9 is a sectional view showing the configuration of the solid state relay element 1. The solid-state relay element 1 is covered with a package 2 having a light-shielding property and made of, for example, black synthetic resin. A void 3 is formed in the package 2, a light emitting portion 4 including a light emitting diode (LED) or the like is disposed on one end face of the void 3, and a semiconductor described later on the other end face facing the one end face. A photodiode which is a photoelectric conversion means and a metal-oxide film-semiconductor field effect transistor (MOS FET, hereinafter referred to as a transistor) which is a semiconductor switching means.
A light receiving unit 5 including the above is disposed. The light emitting unit 4 and the light receiving unit 5 each have a one-chip configuration and are connected to one end of each of the plurality of lead pins 6, and the other end of each of the plurality of lead pins 6 is led out to the outside of the package 2. . The void 3 is filled with a transparent synthetic resin 120.

FIG. 10 is an equivalent circuit diagram of the solid state relay element 1. In the light emitting section 4, the light emitting diode 7 is connected to the DC power source 8 via the switch SW1. The light receiving section 5 includes a plurality of photodiodes 9 and a transistor 10. Each photodiode 9, which is a semiconductor photoelectric conversion element, constitutes a plurality of photodiode rows 11 connected in series with each other. The anode side of each photodiode row 11 is commonly connected to the gate electrode 20 of the transistor 10. The two drain electrodes 12 and 13 of the transistor 10 are led out to the outside of the package 2 via the lead pin 6 and used as output terminals of the solid-state relay element 1.

In the solid-state relay element 1 having such an electrical configuration, the light emitting diode 7 emits light when the switch SW1 of the light emitting section 4 is turned on. This light is received by the plurality of photodiodes 9 of the light receiving section 5 and photoelectrically converted.
The voltage generated by photoelectric conversion is applied to the transistor 10
Applied to the gate electrode 20 of the transistor 10 to control the impedance between the two drain electrodes 12 and 13 of the transistor 10.
In this manner, in the solid-state relay element 1, the impedance between the two drain electrodes 12 and 13 can be controlled by turning on / off the switch SW1 of the light emitting section 4.

FIG. 1 is a plan view showing a part of the configuration of a light receiving portion 5 used in a solid state relay element 1 which is an embodiment of the present invention, and FIG. 2 is seen from section line II-II in FIG. FIG. 3 is a cross-sectional view, FIG. 3 is a cross-sectional view taken along the section line III-III in FIG. 1,
FIG. 4 is a sectional view taken along section line IV-IV in FIG.
FIG. 5 is a sectional view taken along the section line V-V in FIG.
Hereinafter, the configuration of the light receiving unit 5 will be described with reference to FIGS. 1 to 5.

In the light receiving unit 5 according to the present embodiment, the transistor 10a
A plurality of photodiodes 9 may be formed in a matrix so as to cover the transistor 10a. The plurality of photodiodes 9 have a function as a light absorption layer that receives the light generated by the light emitting section 4 and shields the transistor 10a. The plurality of photodiodes 9 are connected in series through a metal thin film (metal wiring 34) attached on each photodiode 9 in order to obtain a desired output voltage, and a plurality of photodiode rows 11 are provided.
Is configured. This photodiode array 11 includes a plurality of rows of metal thin films (substrate electrode 27) in parallel to obtain a desired output current.
And a metal interconnection 36) for connecting a photodiode.

The source region and the drain region of the transistor 10a each have an elongated strip shape and are arranged alternately. Two metal thin films (drain electrodes 12, 1 having a substantially comb shape) are formed on each of the source region and the drain region.
3) is provided. The two metal films are nested inside each other, one metal film covering all the source regions,
Other metal thin films connect all drain regions individually.

All the metal thin films described above act as a light reflection layer that also shields the region on the transistor 10a where the light absorption layer (photodiode 9) does not exist. Further, the transistor 10a of this embodiment is a so-called lateral transistor in which carriers move in the direction perpendicular to the thickness of the substrate. The photodiode 9 uses a molten recrystallized silicon film and is arranged on the channel-source / drain region of the transistor 10a. Hereinafter, the configuration of the light receiving unit 5 will be described in detail.

A P ⁺ type semiconductor substrate 14 is formed on the lower side of the light receiving portion 5 in FIG. 2, and a P ⁻ type growth layer 15 is formed on the P ⁺ type semiconductor substrate 14. The P ⁻ type growth layer 15 is a strip-shaped N ⁺ type drain layer.
16 are surrounded by an N ⁻ type well layer 17 and are arranged in parallel in the vertical direction of FIG. 1 at regular intervals.

FIG. 6 is a sectional view taken along section line VI-VI in FIG.
As shown in the figure, between each N ⁻ type well layer 17, the P ⁻
The type growth layer 15 is filled, and in the P ⁻ type growth layer 15 between the N ⁻ type well layers 17, the channel region 18 of the transistor 10a is formed. A gate electrode 20 made of, for example, polysilicon is provided on the channel region 18 via a gate insulating film 19a. The gate electrodes 20 are connected to each other at both longitudinal end portions of the channel region 18, that is, at both longitudinal end portions of the N ⁻ type well layer 17.
As shown in FIG. 7, it has a substantially trapezoidal shape.

The two drain electrodes 12 and 13 are, respectively, trunk portions 23 and 24 extending parallel to each other in the vertical direction of FIG. 1 and mutually spaced from the two trunk portions 23 and 24 at equal intervals in the vertical direction of FIG. Drain connection parts 25, 26 extending in the direction close to
And has a substantially comb shape. The two drain electrodes 12 and 13 having such a structure are provided in the respective drain connecting portions 2
5, 26 are arranged on each of the drain regions 16 in a mutually nested state and connected to the drain regions 16 as shown in FIG.

In the portion of the insulating film 19 corresponding to each of the drain regions 16,
A plurality of strip-shaped contact holes 26A are formed, a metal thin film is vapor-deposited on the plurality of contact holes 26A, and then etching is performed to form the drain connection portions 26. The drain connecting portion 26 has a cross section parallel to the longitudinal direction of the two side portions 26a and 26b, a horizontal portion 26c interconnecting the lower end portions of the two side portions 26a and 26b, and the side portion 26b. And an extension portion 26d extending from the upper end portion in the opposite direction to the trunk portion 24.

The right side end portion of the trunk portion 24 in FIG. 4 is connected to the upper end portion of the side portion 26a. The drain connecting portion 25 also has the same structure as the drain connecting portion 26.

On the gate electrode 20, a substrate electrode 27 made of a metal thin film is provided on the insulating film 19. The substrate electrode 27 has a parallel portion 28 arranged in parallel with the drain connection portions 25, 26.
And a connecting portion 29 that connects them to each other, and has a substantially crank shape. This substrate electrode
27 is connected to one and is connected to the P ⁺ type semiconductor substrate 14 around the chip in which the light receiving section 5 is formed,
The chip surrounds the two drain electrodes 12 and 13 and makes one round around the chip.

Each photodiode 9 has an N ⁺ type region 31 formed on a P type region 30, and has a substantially rectangular flat plate shape. The plurality of photodiodes 9 are directionally connected in series so as to have the same polarity as each other to form a plurality of photodiode rows 11. That is, the P-type region 30 of each photodiode 9
And the N ⁺ type region 31 are electrically connected by the metal wiring 34 through the two contact holes 33, and a plurality of photodiode rows 11 are configured.

Each photodiode row 11 is arranged perpendicularly to the longitudinal direction of the photodiode row 11 so as to be spaced apart from each other. The substrate electrodes 27 are arranged between the photodiode rows 11 every two rows in a crank shape. Between the remaining photodiode rows 11, for example, the drain electrodes 12 are arranged every four rows of the photodiode rows 11.
Drain connection portions 25 are arranged, and the drain connection portions 26 of the drain electrode 13 are arranged between the remaining photodiode rows 11 at intervals of four rows so as to face the drain connection portions 25 of the drain electrode 12. .

One end of each of the photodiode rows 11 on the same side is connected to the connecting portion 29 of the substrate electrode 27 through a contact hole 32, and the other end of the photodiode row 11 is connected to the photodiode connecting metal wiring 36 through a contact hole 37. Are connected to each other. Further, the photodiode connecting metal wiring 36,
It is electrically connected to the gate electrode 20 through the contact hole 38. Therefore, each photodiode row 11 has one end connected to the substrate electrode 27 and the other end connected to the gate electrode 20. The plurality of photodiode rows 11 are arranged on the N ⁻ type well layer 17 between the gate electrode 20 and the drain region 16 with the insulating film 19 interposed therebetween.

FIG. 11 is a cross-sectional view for explaining a manufacturing process of the light-receiving unit 5 having a one-chip structure. Hereinafter, the manufacturing process of the light receiving unit 5 will be described with reference to FIG.

First, as shown in FIG. 1A, a P ⁻ type growth layer, which is a P type silicon layer containing a low concentration of acceptors, is formed on a P ⁺ type semiconductor substrate 14, which is a P type silicon substrate containing a high concentration of acceptors.
Epitaxially grow 15. Next, a gate insulating film 19a, which is a thermal oxide film, is formed on the growth layer 15 (see FIG. 2B), and a polysilicon layer 20a is deposited thereon. This polysilicon layer 20a is doped to have a low resistance N-type, and is then etched into a desired pattern (ladder type in this embodiment) using the photoresist as a mask to form the gate electrode 20 (see FIG. )reference).

Using the gate electrode 20 thus formed as a mask, a high resistance N ⁻ type well layer 17 is formed by ion implantation (see FIG. 5 (5)).

Next, as shown in FIG. 6 (6), an insulating film 19 is uniformly deposited on the entire surface, and then a polysilicon layer 9a is deposited (see FIG. 7 (7)). By irradiating the polysilicon layer 9a with an energy beam such as an argon laser, the polysilicon layer 9a is melted and recrystallized to obtain a silicon single crystal film. The irradiation of the energy beam is repeatedly performed at a predetermined interval, and a band-shaped silicon single crystal film 9b is formed over the entire surface (see (8) in the same figure).

The strip-shaped silicon single crystal film 9b is removed by etching using a photoresist as a mask except for the regions where the respective photodiodes 9 shown in FIG. 1 are arranged. The silicon single crystal film 9b thus removed by etching is subjected to a normal MOS (Metal Oxide Semiconductor) manufacturing process to manufacture the photodiode 9.

Next, a contact hole 26A is formed in the insulating film 19 (see FIG. 2).
Is formed, and the N ⁺ type drain region 16 is formed through the contact hole 26A (see (9) in the same figure). Finally, a contact hole 32 connecting the substrate electrode 27 and the photodiode 9, a contact hole 33 connecting the photodiodes 9 to each other, and a contact hole 37 connecting the photodiode 9 and the metal wiring 36 for connecting the photodiodes.
And a contact hole 38 for connecting the metal wiring 36 and the gate electrode 20 are formed in the insulating film 19, after which a metal thin film is laminated, and the metal thin film is etched into a desired pattern to form two Drain electrodes 21 and 22 are obtained. In this way, the 1 shown in FIGS.
The light receiving section 5 having a chip structure is manufactured.

FIG. 12 is a plan view showing the structure of the light receiving portion 40 which is the second embodiment of the present invention, FIG. 13 is a sectional view taken along the section line XIII-XIII in FIG. 12, and FIG. Fig. 12 Cross section line XIV-XIV
FIG. 15 is a cross-sectional view as seen from FIG.
FIG. 16 is a cross-sectional view as seen from FIG. 16, and FIG.

Hereinafter, the configuration of the light receiving unit 40 will be described with reference to FIGS. 12 to 16. The light receiving section 40 of the embodiment is housed in the package 2 shown in FIG. 8 and FIG. 9 similarly to the first embodiment, and includes a light emitting section having a light emitting diode 9, and is an optically coupled semiconductor relay. Configure the device. In addition, this embodiment is similar to the first embodiment, and corresponding components are designated by the same reference numerals.

In the light receiving unit 40 according to the present embodiment, the transistor 10b
However, the photodiode 9 having a horizontal configuration and using a melt-recrystallized silicon film is arranged on the channel-drain region. Further, the transistor 10b includes one source electrode (source region common electrode 42) and two drain electrodes 51 and 52, and the two drain electrodes 51 and 52 are substantially comb-shaped on both sides of the source region common electrode 42. It is arranged to exhibit. Each of the plurality of photodiode rows 11 has one end connected to the source region common electrode 42 and the other end connected to the gate electrode 20. The source region common electrode 42
Also, the metal thin film including the two drain electrodes 51 and 52 functions as a reflective layer that shields a region on the transistor 10b where the light absorption layer (photodiode 9) does not exist, similarly to the first embodiment. Hereinafter, the light receiving section 40 will be described in detail.

The light receiving section 40 of the present embodiment is constructed symmetrically with respect to the plane of symmetry 41 shown in FIG. In the light receiving section 40, a source region common electrode 42, which connects a plurality of source regions to be described later in common, is arranged in the central portion. This source region common electrode 42
As shown in FIG. 16, a trunk portion 43 having its axis on the plane of symmetry 41, and a plurality of gates arranged at equal intervals in the lateral direction of FIG. 16 and the trunk portion 43. Connection part 46
And a source connection part 47 connecting the basic part 43 and a plurality of gate connection parts 46.

Two drain electrodes 51 and 52 are disposed on both sides of the source region common electrode 42. These two drain electrodes 51,52
Are the cores 54 and 55, respectively, and
FIG. 16 is composed of a plurality of drain connecting portions 56 and 57 extending in a strip shape in the direction close to each other at equal intervals in the vertical direction. The plurality of drain connecting portions 56, 57 are arranged between the source connecting portions 47 of the source region common electrode 42.

A gate wiring 45 is disposed below the source region common electrode 42 in FIG. 14, and the gate wiring 45 has a trunk portion 48 having an axis line in the same direction as the axis line of the trunk portion 43 of the source region common electrode 42. And a pair of gate electrodes 49 each having its free end connected to the gate connecting portion 46 of the source region common electrode 42. Each of the gate electrodes 49 has an axis line that is perpendicular to the axis line of the trunk portion 48, and is disposed below each source connection portion 47 of the source region common electrode 42.

As described above, the light receiving section 40 of the present embodiment has a symmetric structure with respect to the symmetry plane 41, and therefore only the left side portion of FIG. 16 will be described below.

A plurality of strip-shaped N ⁺ -type drain regions 16 are provided on the lower side of each of the drain connection portions 56 (drain electrodes 51) in FIG.
It is formed on the P ⁻ type growth layer 15 while being surrounded by the N ⁻ type well layer 17. In addition, each source connection portion 47 (source region common electrode
42), two N ⁺ type source regions 60 are formed in a strip shape at intervals with respect to each other on the lower side of FIG. 13, and each N ⁻ type well layer 17 is surrounded by these two source regions 60. P filled between ^-
A channel region 18 is formed in the mold growth layer 15.

A band-shaped contact hole 47A is formed in the insulating film 19 on the two source regions 60, and the contact hole 47A is formed.
The source connection part 47 is formed by depositing a metal thin film on top and then etching. The source connecting portion 47 has a cross section perpendicular to the longitudinal direction of the two side portions 47.
a, 47b, a connecting portion 47c for connecting the lower side end portions of these two side portions 47a, 47b in FIG. 13 to each other, and the two side portions 47a, 47b.
FIG. 13 of FIG. 13 includes extension portions 47d and 47e extending in the directions away from each other from the upper end portion. The two extension parts 47d, 47e
Are provided to block the light emitted from the light emitting portion to the gate electrode 49, the N ⁻ type well layer 17, the channel region 18 and the two source regions 60 located thereunder.

Between the channel region 18 and the N ⁺ type drain region 60
On the N ⁻ type well layer 17, a plurality of photodiodes 9 are arranged in a matrix form in parallel to the strip-shaped N ⁺ type drain regions 16 via an insulating layer 19. The plurality of photodiodes 9 are directionally connected in series so as to have the same polarity as each other to form a plurality of photodiode rows 11, and each photodiode row 11 is arranged in parallel to the N ⁺ type drain region 16. . One end of each of the plurality of photodiode rows 11 has a main portion of the gate wiring 49 via a metal wiring 55 for gate connection.
The other end is connected to the gate connecting portion 46 of the source region common electrode 42.

In the light receiving section 40 having such a configuration, the source region common electrode 42 is used as an input terminal and the drain electrode
51 and 52 are used as two output terminals. The equivalent circuit of the light receiving unit 40 according to the present embodiment is the same as the first embodiment shown in FIG.
It has the same configuration as the equivalent circuit diagram of the light receiving unit 5 of the embodiment.

FIG. 17 is a plan view showing a part of the structure of the third embodiment of the present invention at the stage where the metal wiring pattern of the light receiving section 70 is formed, and FIG. 18 is a section line XVIII-XVIII in FIG. FIG. 19 is a cross-sectional view of the light receiving section 70 seen from above, and FIG.
FIG. 20 is a cross-sectional view of the light-receiving section 70 viewed from X, FIG. 20 is a cross-sectional view of the light-receiving section 70 viewed from section line XX-XX in FIG. 17, and FIG. 21 is a metal wiring pattern of the light-receiving section 70. FIG. 22 is a diagram showing a structure of a gate electrode 71 described later, and FIG.
The figure shows the arrangement of the photodiodes 9. The configuration of the light receiving unit 70 of this embodiment will be described below with reference to FIGS. 17 to 23. In addition, the light receiving unit 70 of the present embodiment,
It is similar to the light receiving portions 5 and 40 of the first and second embodiments, and corresponding components are designated by the same reference numerals.

In the present embodiment, the transistor 10c used in the light receiving section 70 has a vertical structure, and the gate electrode 71 has a flat plate shape in which square openings 73 are formed in a matrix, and melted The diode 9 using the crystallized silicon film is
The gate electrode 71 is provided on a region other than the region where the opening 73 is formed. In addition, the source region 74 has the openings 73.
The donut shape is formed on the lower side of the periphery of each of the source regions.
74 are connected to each other via the source wiring metal 81.

In addition, one end of each photodiode row 11 configured by connecting the plurality of photodiodes 9 in series is connected to the source wiring metal 81, and the other end is connected to the gate electrode 71. Therefore, in the light receiving unit 70 of this embodiment, the transistor 10c is used only for direct current. Therefore, by connecting one electrodes of the two transistors 10c to each other and connecting the photodiode rows 11 in anti-series, the solid-state relay element 91 for both DC / AC is formed. Less than,
The light receiving unit 70 will be described in detail.

The gate electrode 71 used in the light receiving section 70 of the present embodiment has a flat plate shape, and a plurality of openings 73 formed by etching away in a rectangular shape as shown in FIG. 22 are arranged in a matrix. To be done. An N ⁺ type source region 74 is formed in a donut shape on the lower side in FIG. 18 of the peripheral edge of each opening 73. A P ⁻ type well layer 75 surrounds the source region 74 and an N ⁻ type growth layer 76 is formed.
Formed on. The N ⁻ type growth layer 76 is an N ⁺ type drain region.
It is provided on 77.

The source wiring metal 81 has a substantially comb shape as shown in FIG. 21, and penetrates each opening 73 of the gate electrode 71 through each contact hole 82 provided in the insulating film 19 to form each N It is connected to the ⁺ type source region 74. A plurality of photodiodes 9 are formed on a region of the gate electrode 71 excluding the openings 73.
Are arranged in a matrix in parallel with the source wiring metal 81 through the insulating film 19 (see FIG. 23). The plurality of photodiodes 9 form a plurality of photodiode rows 11 connected in series in one direction via metal wirings 34. One end of each photodiode row 11 is connected to the source wiring metal 81 and the other end is , Connected to the gate electrode 71.

In the light receiving section 70 of the present embodiment, it should be noted that the N ⁺ type source region 74 surrounded by the P ⁻ type well layer 75 is connected to the gate electrode 71.
Is formed in a donut shape below the inside of the peripheral edge of each opening 73, and a channel region 84 is provided in a region located below the outside of the peripheral edge of the opening 73 of the P ⁻ type well layer 75, The N ⁺ type drain region 77 is provided below the N ⁻ type growth layer 76 in FIG.

By providing the N ⁺ type source region 74, the N ⁺ type drain region 77 and the channel region 84 as shown in FIG.
The light receiving section 70 constitutes a vertical transistor. That is,
The carriers emitted from the source region 74 move in the direction indicated by the arrow A in FIG. 18, that is, in the thickness direction of the N ⁻ type growth layer 76, through the channel region 84 provided in the peripheral portion thereof, It reaches the drain region 77.

FIG. 24 is an equivalent circuit diagram of a solid-state relay element 90 including the light receiving section 70 of this embodiment. As shown in the figure, the solid-state relay element 90 of this embodiment has a dedicated DC configuration in which the cathode side of the photodiode array 11 is connected to the source metal wiring 81 of the transistor 10c. Therefore, as shown in FIG. 25, the DC / AC shared relay element 91 can be constructed by connecting and using two light receiving portions 70 according to this embodiment in anti-series.

The light receiving parts 40 and 70 of the second and third embodiments are manufactured by substantially the same manufacturing process as the light receiving part 5 of the first embodiment.

As described above, in the light receiving portions 5, 40, 70 according to the first to third embodiments, each photodiode 9 and the transistors 10a, 10b,
Since 10c and 10c are laminated to form a one-chip structure as a whole, the light receiving parts 5, 40, 70 can be made compact. Further, since the photodiodes 9 are arranged in a matrix, the photodiodes 9 can be arranged extremely efficiently without enlarging the light receiving portions 5, 40, 70. That is, by connecting a desired number of photodiodes 9 in series in each photodiode array 11, the total output voltage of the photodiodes 9 can be set to a large value. Furthermore, by arranging the desired number of the photodiode rows 11 in parallel, the current capacity of all the photodiodes 9 can be set to be large.

As described above, in the light receiving portions 5, 40, 70 of the first to third embodiments, desired voltage and current capacity can be obtained without enlarging the overall configuration.

As described above, according to the present invention, in the light receiving portion, the semiconductor switching means and the photodiode are laminated in this order on the semiconductor substrate, so that the semiconductor switching means and the photodiode in the light receiving portion occupy. The area can be remarkably reduced, and the optical coupling type semiconductor relay device can be downsized. Further, since the melt-recrystallized photodiode is used, a sufficient photovoltaic force can be obtained and a large input capacitance to the semiconductor switching means can be secured. As a result, even if the size of the optically coupled semiconductor relay device is reduced, the input capacitance can be increased, and the performance does not deteriorate. Further, by setting the number of photodiodes forming the photodiode array to a desired number, the output voltage obtained from the entire photodiode can be selected to a desired value, and the number of photodiode arrays can be set to a desired number. Thus, the output current obtained from the entire photodiode can be selected to a desired magnitude. Thus, even a relatively small-sized optical coupling type semiconductor relay device can perform a switching operation of a relatively large current.

Particularly according to the invention, when the semiconductor switching means is a lateral metal-oxide-semiconductor field effect transistor, a photodiode is arranged on the region between the channel and the drain of the transistor, and the semiconductor switching means is a vertical type. In the case of a metal-oxide-semiconductor field effect transistor, the photodiode is arranged on a region other than the gate electrode opening of the transistor,
As a result, the excellent effect that the photodiode can be formed by using the molten recrystallized silicon and then the collective wiring can be performed is achieved.

[Brief description of drawings]

FIG. 1 is a plan view showing a part of the configuration of a light receiving portion 5 used in a solid state relay element 1 according to an embodiment of the present invention, and FIG. 2 is a sectional view taken along section line II-II in FIG. , Fig. 3 is Fig. 1
Sectional view seen from III-III, and FIG. 4 is a section line IV of FIG.
FIG. 5 is a sectional view taken along the line IV--IV of FIG. 1, FIG. 6 is a sectional view taken along the line VI--VI of FIG. 2, and FIG. The figure which shows the structure of the gate electrode 20, FIG. 8 is a perspective view which shows the whole structure of the solid-state relay element 1, FIG. 9 is sectional drawing which shows the structure of the solid-state relay element 1, FIG. FIG. 11 is an equivalent circuit diagram, FIG. 11 is a cross-sectional view for explaining the manufacturing process of the light receiving section 5, FIG. 12 is a plan view showing the configuration of the light receiving section 40 according to the second embodiment of the present invention, and FIG. FIG. 12 is a sectional view taken along section line XIII-XIII, FIG. 14 is a sectional view taken along section line XIV-XIV of FIG. 12, and FIG. 15 is a section taken along section line XV-XV of FIG. FIG. 16 and FIG. 16 are views showing the configuration of the metal wiring pattern of the light receiving portion 40, and FIG. 17 is a partial configuration of the light receiving portion 70 which is the third embodiment of the present invention at the stage where the metal wiring pattern is formed. The plan view shown in FIG. 18 and FIG. Section line XVIII
-Cross-sectional view seen from XVIII, Fig. 19 is Fig. 17 Sectional line XIX-
Sectional view seen from XIX, FIG. 20 is a sectional view taken along the section line XX-XX in FIG. 17, FIG. 21 is a view showing a metal wiring pattern of the light receiving section 70, and FIG. 22 is a configuration of the gate electrode 71. 23, FIG. 23 is a diagram showing an arrangement state of the photodiode 9, FIG. 24 is an equivalent circuit diagram of a solid state relay element 90 including the light receiving section 70 of the present embodiment,
FIG. 25 is an equivalent circuit diagram of a solid-state relay element 91 for both DC and AC, which is constructed by connecting two relay elements 90 in anti-series,
FIG. 26 is a cross-sectional view showing the configuration of the light receiving unit 101 of a typical prior art optical coupling type solid state relay element. 1,90 …… Solid state relay element, 4 …… Light emitting part, 5,40,70 ……
Light receiving part, 7 ... Light emitting diode, 9 ... Photodiode, 10 ... Transistor, 11 ... Photodiode array, 45
...... Gate wiring, 20,49,71 …… Gate electrode, 12,13,21,2
2,51,52 …… Drain electrode, 14 …… P ⁺ type semiconductor substrate, 15
...... P-type growth layer, 16 …… N ⁺ type drain region, 17 …… N ⁻ type well layer, 18,84 …… channel region, 27 …… substrate electrode, 3
5,64 ...... metal wiring, 60,74 ...... N ⁺ source region, 75 ...... P ^-
Type well layer, 76 …… N ⁻ type growth layer, 77 …… N ⁺ type drain region, 91 …… DC / AC common relay element

Claims (2)

[Claims] 1. A light emitting unit, and a light receiving unit having a plurality of input / output electrodes and optically coupled to the light emitting unit,
An optical coupling type semiconductor relay device which performs a switching operation for conducting / interrupting between the plurality of input / output electrodes in the light receiving section in response to the blinking operation of the light emitting section, wherein the light receiving section is provided on a semiconductor substrate. The semiconductor switching means and the photodiode are laminated in this order from bottom to top, and the semiconductor switching element is a lateral metal-oxide film-semiconductor field effect transistor in which carriers move in a direction perpendicular to the thickness of the semiconductor substrate. The photodiode is formed of a melt-recrystallized silicon film formed on a semiconductor substrate via an insulating film 19 and arranged on a region between a channel 18 and a drain of a field effect transistor. One or more photodiode rows in which the photodiodes of are connected in series in the same direction are formed, and each photodiode is used as the uppermost layer. At least one of the common wirings for separately connecting the respective electrodes on the one direction side and the electrodes on the other side, which are common to each other, and the gate electrode 20 on the channel 18, and the one of these And a source electrode and a drain electrode of the field-effect transistor are formed, and a drain electrode of the field-effect transistor is formed based on a voltage from one of the common lines. The optical coupling type semiconductor relay device is characterized in that the switching operation is performed. 2. A light emitting part, and a light receiving part having a plurality of input / output electrodes and optically coupled to the light emitting part,
An optical coupling type semiconductor relay device which performs a switching operation for conducting / interrupting between the plurality of input / output electrodes in the light receiving section in response to the blinking operation of the light emitting section, wherein the light receiving section is provided on a semiconductor substrate. The semiconductor switching means and the photodiode are laminated in this order from bottom to top, and the semiconductor switching element is a vertical metal-oxide film-semiconductor field effect transistor in which carriers move in the thickness direction of the semiconductor substrate. The photodiode is formed of a melt-recrystallized silicon film which is formed on a semiconductor substrate via an insulating film 19 and arranged on a region other than the opening 73 formed in the gate electrode of the field effect transistor. , One or more photodiode rows in which a plurality of photodiodes are connected in series in the same direction are formed, and each photodiode is used as the uppermost layer. At least one of the common wirings that separately connects the electrodes on the one direction side and the electrodes on the other side that are common to the ion row, the gate electrode 20 on the channel 18, and the one of these Forming a conductor for connecting the common wiring and the gate electrode of the field effect transistor and the source and drain electrodes of the field effect transistor, and the one of the common wiring and the gate electrode, and the one of the common wiring and the gate electrode. A conductor for connecting to and a source and drain electrode of the field effect transistor are formed, and a drain electrode of the field effect transistor is formed on the basis of a voltage from the one common wiring to perform a switching operation. Optically coupled semiconductor relay device characterized by: