GB2057743A

GB2057743A - Video display device

Info

Publication number: GB2057743A
Application number: GB8032430A
Authority: GB
Original assignee: Sharp Corp
Current assignee: Sharp Corp
Priority date: 1977-10-07
Filing date: 1978-10-06
Publication date: 1981-04-01
Also published as: GB2008303A; DE2843801A1; GB2057743B; FR2405604A1; GB2008303B; DE2843801C2; FR2405604B1

Abstract

A video display device comprises a thin-film electroluminescent matrix display panel having scanning horizontal electrodes Y and vertical data electrodes X, and a drive system 14 for scanning the panel by selecting a line at a time. Each video line is sampled and stored in capacitors Ch, the data signals applied to the data electrodes X being amplitude modulated in response to the stored voltages to display a video image. Each time the scanning of the panel is completed, a reverse refreshing pulse is applied to all elements to cause further emission by the cells which emitted light during scan, and to balance D.C. <IMAGE>

Description

1 GB2057743A 1

SPECIFICATION

Video display device This invention relates to a display device for displaying a video image using a thin-film electroluminescent (EL) display panel.

In accordance with the invention there is provided a video display device comprising a thinfilm electroluminescent (EL) display panel having a plurality of scanning electrodes and a plurality of data electrodes, and a drive system operable to apply signals to the scanning electrodes to scan the panel in a line-at-a-time manner while applying data signals to the data 10 electrodes to operate the display, the drive system including means for storing voltages corresponding to respective portions of a line of a video signal, said data signals being amplitude modulated in response to the stored voltages to provide a display of a video image, the drive system further being operable, after scanning said panel, to apply a refresh pulse to the panel.

The modulated data signals may be obtained by preliminarily applying fixed-amplitude data signals to the data electrodes and then modulating the voltage on each electrode in response to the respective stored voltages corresponding to the video signal portions. The modulation may be accomplished by discharging the electrode voltages at a constant current, and either the magnitude of the current or the period of discharge can be varied in response to the stored 20 voltages, thereby to control the resultant voltages on the data electrodes.

As a result, the brightnesses of the picture elements of the EL display panel correspond to the video signal.

In a television receiver embodying the present invention, a line of a video signal is stored during a single horizontal scanning period and data electrodes of the thin-film EL panel are preliminarily charged. During a horizontal synchronizing signal, the amplitudes of the charges on the data electrodes of the thin-film EL panel are modulated by the stored video signal using constant current discharge circuits. A write voltage is applied to the thin-film EL panel during a first part of the next succeeding horizontal scanning period to display the stored video signal, and the pre-charge operation described above is carried out during a second part of the 30 horizontal scanning period.

An arrangement embodying the invention will now be described by way of example with reference to the accompanying drawings, wherein:

Figure 1 is a fragmentary perspective view of a thin-film EL display panel; Figure 2 is a circuit diagram of an EL panel drive circuit for a device embodying the present 35 invention; Figure 3 is a time chart of signals appearing in the circuit of Fig. 2; Figure 4 is a time chart showing different steps carried out when displaying an image.

Figure 5 is a waveform diagram of voltages appearing on respective electrodes; and Figure 6 is a time chart for describing a refresh mode.

In order to give a better understanding of the present invention, a brief description will first be made, with reference to Fig. 1, of a construction of a double-isolated thin-film EL (electrolumi nescent) panel which can be used in a device of the present invention.

As shown in Fig. 1, a thin-film EL display panel has a three-layered structure. A predeter mined number of transparent electrode strips 2 are disposed on a glass support 1. A layer 3 of 45 dielectric material such as Y203, SiN,, Ti02, or A1203, a layer 4 of electroluminescent material, for example, ZnS doped with Mn (yellowish orange light) and a second layer 5 of dielectric material such as Y203, SiN,, Ti02, A1203 are disposed by a well known thin-film technique such as vacuum deposition and sputtering, each having a thickness ranging from 500 to 10000 A.

This results in the double-isolation three-layered structure of the EL display panel. A different 50 family of strip electrodes 6 is disposed in a direction normal to the direction of the transparent electrodes 2 to form an electrode matrix array together with the transparent electrodes. With such a three-layered thin-film EL display panel, if one of the first family 2 of electrodes and one of the second family 6 of electrodes are selected, the minute area where the selected electrodes cross will emit light. This area corresponds to a picture element of an image such as a character, 55 a symbol or a pattern being displayed. An EL panel with such a structure is much more attractive than the prior art dispersed powder type EL panel from the standpoint of light intensity, working life and performance stability.

A preferred form of the present invention is adapted to display a television image on the above described double-isolated matrix thin-film EL display panel. Figs. 2 and 3 are a circuit 60 diagram and a time chart of the preferred form and Fig. 5 shows the relationship between the waveform of a voltage applied to a specific electrode and a video signal.

In Fig. 2, the above described thin-film EL display panel is labelled 10, and has electrodes X,-X. extending in the X direction to serve as data electrodes and electrodes Y,-Y, extending in the Y direction to serve as scanning electrodes. Only some of the electrodes of the thin-film EL 65 2 GB 2 057 743A 2 display panel are depicted in the drawings. An enable circuit 11 supplies a pre-charge voltage VP to a common line A upon receipt of a pre-charge signal PRE. A diode array connected to the data electrodes is labelled 12, and has diodes connected to the common line A at the anodes thereof and to respective electrodes X,-X. at the cathodes thereof. The effects of the diode array 12 are to provide isolation for respective data lines and protect switching elements consisting of high voltage transistors from being reverse biased.

A modulator circuit 13 includes logic circuit elements and output circuit elements and may be implemented with an integrated circuit technique. This circuit receives a shift data signal DS which is derived from a signal synchronous with a horizontal synchronizing signal contained within a television composite signal and derived through a conventional modulator circuit, and 10 the circuit includes a digital shift register 13-1 to which the signal DS is delivered and which performs a shift operation in response to a shift clock signal SC, AND logic circuits AD,-AD.

which produce a logic product of shift pulses DS,-DS provided at the output of the digital shift register 13-1 and a sampling aperture signal AP determining a sampling period, analog gates AG,-AG, which gate video signals (analog signals) received and picked up through a conventional demodulator circuit according to the outputs of the AND logic gates AD,AD,, a family of capacitors Ch storing as a charge amplitude the video signal V after it has passed the analog gates AF1-AG, analog gates SG,-SG. which are opened by strobe signals SB synchronous with the horizontal synchronizing signal, ON/OFF switching elements CG1-CG,,, which are held in the ON state in response to a clear signal CL in order to ensure the OFF state 20 of constant current elements SI),-SI),,, to be described later when in the pre-charge mode, and the constant current type drive elements SI),-SI). themselves, for example, N channel DSAMOS (diffusion self alignment metal oxide semiconductor) transistors which vary the pre charge amplitude on the thin-film EL display panel according to the video signals and each form a constant current discharging circuit.

A scanning switch element circuit 14 is connected to the scanning electrodes Y1-Y,, and comprises a digital shift register 14-1 performing shift operations in response to a shift data signal SD produced from a signal synchronous with the horizontal synchronizing signal and a shift clock signal SS, AND logic circuits AW,-AW, which produce logic products of the outputs of the digital shift register 14-1 and a write signal WP, OR logic circuit SOW,-OW, which - 30 produce logic sums of the outputs of the AND logic circuits AW,-AW,, and a set signal SET, and N channel DSAMOS transistors enabled by the ouputs of the OR logic circuits OW1-OW,, This circuit arrangement can be implemented with an integrated circuit technique.

A diode array 16 is provided, with the cathodes of the diodes connected to odd scanning drive lines and the anodes connected in common, for the purpose of isolating the scanning drive 35 lines from one another and preventing switching elements from being reverse biased.

Another diode array 17 is provided, with the cathodes of the diodes connected to even scanning drive lines and the anodes connected in common, for the same purpose.

A drive circuit 18 supplies the odd scanning drive lines with a voltage V, , in response to a write signal WO. Another drive circuit 19 supplies the even scanning drive lines with the same 40 voltage V,, in response to a write signal WE. The supply voltage V,, from the write drive circuits 18, 19 is preferably equal to the threshold voltage level of electroluminescence of the thin-film EL display panel, but may instead be lower, in which case there should be a corresponding increase in the voltage of the other drive circuits. In the inventors' experiments the voltage VP was 70V and the voltage V,, was 140V.

A diode array 20 has a plurality of diodes with the anodes connected to respective data electrodes and the cathodes connected in common, and is used when supplying the panel with a refresh pulse.

A refresh drive circuit 15 supplies a refresh pulse voltage Vrto the common lines B, C of the diode arrays 16, 17 simultaneously upon receipt of a signal REF. A circuit 21 forms a sink 5P circuit upon receipt of a signal SI during the refresh mode.

The mode of operation when a specific scanning line j is driven will be now described, with reference to the waveform diagrams of Fig. 3.

At the beginning of the video signal period for the scanning electrode Y, the shift data pulse DS is applied to the digital shift register 13-1, the contents of which are then sequentially shifted in response to the shift clock signal SC to produce the shift data pulses DS1-DS,, The AND logic circuits AD,-AD produce logic products of the data pulses DS,-DS and the sampling period determining sample aperture signal AD and supply them in sequence to the analog gates AG,-AG.. Since the analog gates AG1-AG.. are supplied on the input lines thereof with the outputs of the AND logic circuits AD,-AD and on the common line thereof with the 60 video signal V, the video signal passes the analog gate AG,-AG,, only during the periods of the sampling aperture signal, (i.e. it passes a different gate during each of the periods). At those times, the hold capacitors Ch leading to the outputs of the analog gates AG,-AG are charged with respective amplitudes (voltages) of a line of the video signal. In this way, the capacitors Ch associated with the data electrodes X1-X hold respective video amplitudes.

1 A 3 GB2057743A 3 (PRE-CHARGE) Immediately before the video signal period is completed, in other words, while the video signal is being sampled, the pre-charge signal PRE is generated to urge the drive circuit 11 into the operative state. Under these circumstances the gates to all the scanning side switching elements SS,-SS,, are supplied with the set signal SET via the OR logic circuits OW,-OW, placing all the switching elements into the ON state. All the drive transistors SD1-SD within the data side switching element circuit 13, on the other hand, are in the OFF state. The setting of the transistors SD,-SD in the OFF state is guaranteed by placing all the clear gates CG1-CG into the ON state in response to the clear gate pulse CL. It will be noted that the clear gate pulse CL 10 is present throughout the pulse period of the pre-charge signal PRE and that of the set signal SET. Since the drive circuit 11 supplies, on the common line A, the voltage V,, all the picture elements on the thin-film EL display panel are charged with the voltage VP via the all the data lines X,-X,, The voltage VP is correlated as VP = V,;-Vh wherein V,, is the voltage required to produce maximum brightness of the thin-film EL display panel and V,, is the threshold voltage 15 thereof.

(DISCHARGE MODULATION) After the m th sampling of the video signal has been executed by the action of the digital shift register 13-1 and the precharge is completed in advance of the blanking period, the strobe 20 pulse signal SB is applied to all the analog gates SG1-SG,, and the supply of the clear pulse CL is discontinued. This leads to the instantaneous amplitudes (voltages) of the video signal stored on the respective hold capacitors Ch being transferred at once to the gates of the constant current drive elements SD1-SD The set pulse signal SET is discontinued as soon as the pre charge mode is completed. Thus all the transistors SS,-SS,, within the scanning side switching 25 circuit 14 are rendered nonoperative.

When the video signals stored on the capacitors are impressed upon the constant current type drive elements SD1-SD... the discharge modulation mode is carried out whereby the previously stored charges on the electrodes X,-X,, are discharged in a constant current fashion as long as the respective discharge period last.

Discharge current id flowing through a specific transistor SDi can be represented below:

dy id= - C- (1) dt wherein C is the sum of capacitances of a respective line viewed from the modulation side drive lines X,-X. and is equal to C = nCe (Ce: capacitance per picture element of the matrix panel and n: the number of all the picture elements in a data line).

Since the transistors SD1-SD discharge at a constant current, the discharged voltage V (i.e. 40 the voltage on each electrode after the discharge operation) can be written below:

t id id --dt=VP--t C C wherein t is the discharge period.

Assume now that an N channel MOS transistor having the relationship between the input gate voltage V. and the drain current iD as defined below is employed in the modulation side drive circuit 13:

iD = gmVg (3) wherein gm is the gate-to-drain mutual conductance of the transistor employed and a proportional constant.

Where Vg(i) is the input gate voltage of the constant current type drive element SD i driving a specific drive line Xi connected to the modulation side drive circuit 13 and gm(i) is the mutual conductance thereof, the voltage V(i) of the drive line Xifollowing application of the voltage Vg(i) to the gate of that transistor SDi can be obtained by rewriting the foregoing formulas (1) and (2):

id iD gm(l) V0 = VP_ -t= VP_ --t= VP_ C C --. V, (i) t (4) C 4 GB2057743A 4 wherein iD is the drain current and equal to the discharge current id.

In as much as the mutual conductance gm of the elements SI),-SI). in the circuit 13 is only slightly different from element to element, gm(i) -- gm (k: i) = gm is satisfied and gm c is deemed to be a constant K. The formula (4) can be rewritten as follows:

V(i) = Vp - K.VIO t The formula (5) reveals that the input gate voltage V,(i) of the drive element DSi and the period t of the applied input -gate voltage are two parameters for determining the voltage V(I).

Accordingly, a visual display of a half-tone image on a thin-film EL display panel can be provided either by applying a signal having a variable amplitude corresponding to the video signal for a specific period to the input of the constant current type drive elementor by applying a signal having a fixed voltage amplitude but a variable pulse width corresponding to the video signal to the input of the constant current type drive element, in both cases achieving amplitude modulation of the voltages across picture elements of the panel. The former technique will be 20 named the amplitude modulation drive method by the amplitude modulated input signal and the latter will be named the amplitude modulation drive method by the pulse width-modulated input signal.

The amplitude modulation drive method by the amplitude-modulated input signal is executed by applying a signal variable in voltage according to the video signal to the gate of the transistor 25 5Di. The amplitude modulation drive method by the pulse width-modulated input signal is executed through the utilization of a signal variable in pulse width according to the video signal, which pulse width variable signal is applied to the transistor SDi.

w 7 (WRITE MODE) After amplitude modulation of the voltages on the data electrodes, a scanning electrode is scanned so that all the picture elements associated with that scanning electrode are written-in to provide electroluminescence to a degree dependent on the amplitude modulated voltages on the data electrodes. The entire operation is successively repeated for different scanning electrodes, to provide lineat-a-time scanning of the panel.

In order to write the respective picture elements E(1, 1), E(2, 1).... E(i, j).... E(m, j) on the scanning side electrode Y,, all the transistors SS,-SS,, in the scanning side switch circuit 14 and all the transistors S1),-SI),, in the data side switch circuit 13 should assume the OFF state.

Under these circumstances the modulationside drive electrodes X,-X,, are held or clamped,,ith the voltages V(t), (i = 1,2,... m) corresponding to the inputs to the modulation side switching 40 elements SD1-SI), Only the transistor SS, enabling a selected one of the scanning electrodes Y. is turned ON in response to the output from the digital shift register 14-1, while all the remaining scanning drive elements SSkk-j remain in the OFF state. If the scan electrode Y, is an odd line, then the write drive circuit 19 upon application of the write command WP will being the common line C 45 of the diode array 17 connected to the even scan electrodes up to the electroluminescence threshold voltage V,. Since the drive elements SI),-SID.m and SS,-SS,, connected to the driven lines X,-X and Y, -Y, are -all in the OFF state at this moment, all the scanning side drive lines are raised up to the voltage V,, due to capacitive coupling between the modulation side drive lines X,-Xmand the scanning side drive lines Y,-Y, The voltages V,,(t), (i = 1,2_.. m) of the 5D modulation side electrodes X,-X. become as indicated below since the voltages of all the scanning side electrodes Y,k, except the selected scan electrode Y, are increased to the electroluminescence threshold voltage V,:

Vji) = V(i) + V, (6) The transistor associated with the selected scan electrode Y, is in the ON state so -that the picture element (i, j) on the selected scan electrode Y, causes electroluminescence in proportion to the write voltage V,,,,, upon supply of the voltage as defined by the formula (6). Meanwhile, the voltage V(i) is supplied to the picture elements E(i, k yj) on the non- selected scan electrodes Yk4P In order that selected picture elements on the selected scan electrode Y '. provide electrolurni nescence and non-selected picture elements on the non-selected scan electrodes Yk4 j do not -provide electroluminescence, the respective voltages of the common line drive circuits 11, 18, 6 5 19 should be correlated as follows. In the given example, V,= IVh.

1 i; 1 GB 2 057 743A 5 V(1)sVP:5V1h5V,Al) (7) The picture elements on the selected scan electrode Y, are written in this way.

When it is desired to write a picture element on the even scan line Yj,i during the write mode, the write drive circuit 18 drives the common line B of the diode array 16 connected to the odd scanning drive lines up to the electroluminescence threshold voltage Vh and only the drive element SS,,, in the scanning side drive circuit is placed into the ON state during the period of the write command M.

The pulse width of the write command WP is approximately one half as long as the horizontal 10 scanning period. During the write mode the write voltage is supplied for a long period so as not to suffer from the influence of variations in line resistance of the drive lines.

The clear pulse CL is also supplied to the clear gates CG,-CG,, during this period, which gates are held in the ON state to make sure that the constant current drive elements SI),-SD are in the OFF state. The clear gates CG1-CG,, are in the OFF state only when the strobe signal is 15 supplied during the blanking period and the constant current type elements SD1-SD effect the constant current discharge operation. The reason the clear pulse CL is applied during the whole period except for the blanking period is that the thin-film EL display panel is a relatively high voltage element and the gate inputs of the constant current type drive elements are grounded with low impedance by the clear gates CG1-CG to avoid the adverse effects of feedback upon 20 the input side thereof, whereby drive noise may ride on the instantaneous amplitude of the video signal held on the hold capacitor Ch during the sampling period or the operation of the drive elements may lack stability.

In this manner, the video signal is written on the scanning drive line Y, while the video signal of the next succeeding scanning drive line Y,,l is being sampled, i.e. during the write mode the 25 modulation side drive circuit 13 samples the video signal of the next scanning drive line Y,+ 1, The pre-charge mode is executed after completing the write mode but before the next succeeding blanking period.

Thus, the write mode is effected for the scanning side drive line Y,_, and the pre-charge mode is effected for the scanning side drive line Y, while the video signal for the s canning side drive 30 line Yi is being sampled. The discharge modulation mode is effected upon the scanning side drive line Y, during the blanking period after the signal for the scanning side drive line Yr The drive method, therefore, generally consists of the pre-charge mode, the discharge modulation mode and the write mode.

Fig. 4 shows the timing relationship among the pre-charge mode, the discharge modulation 35 mode and the write mode, with regard to the video signal V. Fig. 5 shows the video signal V, and the drive waveforms for the modulation side drive lines Xi,,, Xi and Xi-, and the scanning side drive lines Yj-2, Yj-1 and Yr The above mentioned operational modes are repeated to write sequentially the scanning side drive lines 1, 2, 3 n. After completing one scanning field, a refresh mode is effected during 40 the blanking period of the vertical synchronizing signal. The refresh mode is effected through a combination of the drive circuit 15, the diode arrays 16, 17, 20 and the drive circuit 2 1.

During that blanking period the transistors SS,-SS,, within the scanning side switching circuit 14 are all in the OFF state and the counterparts S1),-SD within the data side switching circuit 13 are all in the OFF state. The drive pulses REF and SI are supplied to the inputs of the circuits 45 15, 21 simultaneously and thus the refresh pulse is applied throughout the EL panel. The refresh pulse voltage Vr is equal in magnitude to that write voltage which is applied to the respective scan electrodes to cause the maximum brightness, but is of opposite polarity. Therefore, the thin-film EI display panel is driven by an a.c. voltage, by the alternate application of the write voltage and the refresh pulse voltage. If a write pulse is first applied to cause polarization of a picture element and then the refresh pulse is applied, the refresh pulse is superimposed upon a polarization electric field, allowing only those picture elements already written again to produce electroluminescence. Since the degree of polarization of the picture elements already written is proportional to the electroluminescence brightness, electroluminescence corresponding to the polarization degree is again produced upon application of the refresh 55 pulses, as is desired for a half-tone display. The effects of the refresh pulses are to prevent polarization from being biased in a certain direction and permit already-written picture elements again to produce electroluminescence upon the application of a write voltage during the next succeeding field period. 60 At the final stage of the refresh mode the set input signal SET is applied to the circuit 14 to 60 turn ON the transistors SS, -SS,, to unload the charge of the refresh voltage Vr accumulated on the whole of the panel. The vertical synchronizing signal and the various control signals REF, S] and SET used in the refresh mode are correlated in the timing relationship shown in Fig. 6. The write mode and the refresh mode described above will be repeated to complete a display of a television image. 65 6 GB2057743A 6

Claims

1. A video display device comprising a thin-film electroluminescent (EL) display panel having a plurality of scanning electrodes and a plurality of data electrodes, and a drive system operable to apply signals to the scanning electrodes to scan the panel in a line- at-a-time manner while 5 applying data signals to the data electrodes to operate the display, the drive system including means for storing voltages corresponding to respective portions of a line of a video signal, said data signals being amplitude modulated in response to the stored voltages to provide a display of a video image, the drive system further being operable, after scanning said panel, to apply a refresh pulse to the paneL

2. A display device as claimed in claim 1, wherein the drive system is operable to apply a fixed amplitude data signal to each data electrode, and then modulate the amplitude of the voltage on each data electrode in accordance with a respective stored voltage.

3. A display device as claimed in claim 1 or claim 2, arranged to sample a line of the video signal associated with a said scanning electrode to provide said stored voltages, and, while 15 sampling, to scan the preceding scanning electrode.

ii Printed for Her Majesty's Stationery Office by Burgess & Son (Abingdon) Ltd-11 98 1. Published at The Patent Office, 25 Southampton Buildings, London, WC2A lAY, from which copies may be- obtained.

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