DE2843801C2 - Circuit arrangement for controlling a thin-film electroluminescent video display panel with a matrix structure - Google Patents

Description

- A discharge modulation circuit (13) via which unselected data electrodes (Xi-Xm) fully precharge and selected data electrodes give their charge so far that the amplitude of the remaining charge corresponds to a video signal (V) to be mapped, and through

- A write circuit (18, 19) which, in the course of the line-by-line scanning , supplies a write voltage to all write electrodes (Y, -Y _n ) , which is superimposed on the remaining charging voltage of the individual picture elements (E) , which results in a voltage in the selected picture elements leads which is above the threshold value to be exceeded for a luminescence, but leads to a voltage below that in the unselected picture elements, so that the video image is displayed on the display panel (10).

2. Circuit arrangement according to claim 1, characterized in that the precharge voltage fVyso is selected. that result for the pixels (EJ electroluminescence values of a maximum permissible brightness.

3. Circuit arrangement according to claim 1 or 2, characterized in that the discharge modulation circuit (13) controllable current source «! (SD, - SD _m ) , to whose inputs a signal with an amplitude corresponding to the video signal can be applied.

4. Circuit arrangement according to claim t or 2, characterized in that the discharge modulation circuit has controllable current sources (SD \ to SDm) which are controllable by pulse-duration-modulated signals whose pulse widths correspond to the sampled video signal.

5. Circuit arrangement according to one of claims 1 to 4 for displaying a television picture, characterized in that

55

- The discharge modulation circuit (13) is assigned a device (13-1) for interrogating a video signal for a particular one of the writing electrodes (YJ during a video signal line period,

- the clock control is carried out in such a way that the write circuit (18, 19) then carries out the write operation in each case on the write electrode (Yj- \) previously operated on the specific write electrode (Yj),

- thereupon takes place on the specific writing electrode (Yj) a precharge with the sampled values of the video signal, and that

- Finally, the discharge modulation takes place by switching through charges temporarily stored in capacitors (ch) of the discharge modulation circuit (13) and corresponding to the sampled values of the video signal (V) with respect to the specific write electrode (YJ during a horizontal blanking interval

6. Circuit arrangement according to one of claims 1 to 5, characterized by a device (15, 20, 21) for performing a refresh operation during a vertical blanking interval.

The invention relates to a circuit arrangement for controlling a video image display, organized in a matrix-like manner and scanned in rows, in the form of a

Thin film EL (Electroluminescence) video display panel having a plurality of writing electrodes and one A plurality of data electrodes which define a number of picture elements on the display panel and which provide a precharge voltage for application to the picture elements.

In a known circuit arrangement of this type (DE-OS 20 29 053) the writing electrodes and data electrodes when selecting a picture element each controlled by a pulse generator, one of which is a pulse of negative polarity and the one supplies other pulses of positive polarity, however, each with a constant amplitude all picture elements at the same time a precharge voltage also always constant polarity created. On a video display board controlled with such a circuit arrangement is accordingly the Splitting of halftone images is not possible. The purpose of the aforementioned pre-charging voltage is in this case the induction of an after-leukiite or after-effect effect with good brightness of the displayed one Image.

Up to now, the was used to display a halftone image Use of an analog / digital converter is required, which converts the level of the video signal voltage into a divided by a predetermined number of corresponding tone signals. Such arrangements are necessarily complicated in terms of circuitry.

The invention is therefore based on the object of a Specify arrangement of the type mentioned above, with the help of which it is possible. without using a Analog / digital converter to display a halftone image on an electroluminescence display panel.

The solution principle consists in the application of a Amplitude modulation or pulse width modulation when displaying images on a thin film EL display panel. d. H. the pre-charge supplied to the panel becomes changed according to the video signals.

According to a preferred embodiment of the invention, all picture elements are precharged with constant charging voltage, whereupon the precharge amplitude in the individual picture elements is changed with the aid of a discharge modulation circuit. As a result, the EL display panel changes its brightness in accordance with the video signal.

In a television receiver that contains the display arrangement according to the invention, in the course of a single horizontal scanning slot of a television signal, the video signals for the individual horizontal

Scanning electrodes stored and the thin film EL display panel! charged in advance. If one is present Horizontal sync signal becomes the amplitude the precharge of the thin film EL display panel is controlled by the video signals thus stored within a constant current discharge circuit, formed by individually controllable constant current sources. In the course of the first half of the next following horizontal scan: a writing voltage is applied to the thin film EL display panel, and im During the second half of this horizontal scanning slot, the previously described pre-charging takes place.

An embodiment incorporating the features of the invention will now be described in conjunction with FIG Drawings explained in more detail. In it shows

Fig. 1 is a broken away perspective view a thin film EL display panel,

F i g. 2 is a schematic circuit diagram of an EL display panel driver circuit according to the invention;

3 shows a time-staggered pulse diagram for the circuit of FIG. 2,

F i g. 4 shows a pulse diagram for the temporal assignment of the precharge, the discharge modulation and the Writing to the video signal,

Fig. 5 shows a diagram of Piit voltage curves different activation lines, and

6 shows a timing diagram for an operating mode "Refresh".

The in F i g. 1, the thin-film EL (electroluminescence) indicator light, shown broken off, has a three-layer structure and has a number of transparent electrode strips 2 on for glass substrate 1. In addition, according to a known thin film technique (such as, for example, by vacuum deposition or vapor deposition), a layer 3 made of a dielectric material such as Y ₂ Oj, SiN ₄ . T1O2 and / or AI ₂ Oj. a layer made of an electroluminescent material such as, for example, ZnS (yellowish-orange light) doped with Mn, and a second layer 5 made of a dielectric material such as Y? Oj. SiN *. TiO ₂ . Al ₂ O ₁ applied, each of which has a thickness in the range / wischen 0.05 to 1 μπι (500 to 10,000 Å). This then results in a double-insulated three-day structure. A different group of electrode strips 5, which together form what is known as an electrode matrix, extends perpendicular to the transparent electrode strips 2. In this three-layer thin film EL display panel, when one electrode is selected from each of the first group 2 and the second group 5, the selected minute area where the electrodes cross each other is selected. Emits light. This area corresponds to an element of an image, a symbol, a character or any other pattern to be displayed. The EL panel with this structure is the powder dispersion type of the earlier EL panels in terms of light output. Service life and functional stability far superior.

The present invention is directed to displaying a television picture on the above-mentioned double-insulated matrix thin film EL display panel,

FIGS. 2 and 3 contain the circuit diagram and timing diagram of a preferred embodiment, and FIG. 5 shows the comparison between the waveform of a voltage applied to a certain electrode and a video signal. The thin-film EL display panel described above is shown schematically in FIG. The electrodes ΛΊ to X _n serve as data electrodes in the X direction and the electrodes Y \ to Y _n in the V direction as writing electrodes. A precharge voltage V _{p is} applied to a common line A by means of an activation circuit on the basis of a precharge signal PRE. The anodes of the various diodes of a diode arrangement 12 on the data side are all connected to the common line A, and their cathodes are each connected to one of the data electrodes X \ to X _m . In this way, the individual data electrodes are separated and, furthermore, switching elements designed as high-voltage transistors are protected from kickback voltages

A modulator circuit 13, preferably implemented using integrated circuit technology, contains logic Logic gates and output circuit elements. The circuit shows the following details:

- By means of a modulator circuit (not shown) a data shift signal DS is derived from a signal which occurs in synchronism with e em ^iri in a composite television signal horizontal sync signal contained

The content of a digital shift register 13-1 is switched on as a function of a shift clock signal S <".

Logical AND elements AD \ -AD _m generate a logical product from shift pulses DSi-DS _n occurring at the output of the digital shift register 13-1 and a sampling signal Λ Pein which determines a sampling period.

Analog gates AC \ -AG _m switch through recorded video signals V (analog signals) from a known demodulator circuit in accordance with the outputs of the logical AND elements ADy-ADm.

A group of capacitors Ch stores the video signal VaIs charge amplitude values passed through the analog gates AGi to AC _n

Analog gates SG to SG _n are opened synchronously with the horizontal synchronizing signal with the aid of Ti'.tsignalen Sß.

- ON / OFF-switchable switch elements Cd-CG _n are kept in the switched-on state as a function of a clear signal CL in order to ensure the switched-off state of constant currents SD \ - SDm in the precharge operating state.

- Driver elements acting as constant current sources, for example N-channel DSAMOS transistors (Diffusion Self Alignment Metal Oxide Semiconductor Trarsistors) SDx-SD _n . change the precharge amplitude for the thin film EL display panel in accordance with the video signals and would be collectively referred to as a constant current charging circuit.

A scanning circuit 14 connected to the writing electrodes Y \ - Y _n , which is referred to as "writing circuit" in the following, contains

A digital shift register 14-1, the content of which is shifted step-by-step as a function of a shift signal SD which is generated by a signal running synchronously with the horizontal synchronization signal and a shift clock signal SS;

- Logical AND elements AW \ - AW _n , each of which is the logical product of the outputs of the

Generate digital shift register 14 - 1 and a write signal WP:

- Logical OR elements OW ₁ -OW _n for switching through the outputs of the logical AND elements and a set signal SET, and

- DSAMOS transistors SSi - SS _{n which} can be activated with the outputs of the logical OR gates .

This circuit part can also be implemented using integrated circuit technology.

There is also a first diode circuit 16 in which all cathodes are connected to the odd-numbered writing electrodes and all anodes are connected together (line B) in order to separate the individual writing electrodes from one another and to protect the switching elements from counter voltages. In a further diode arrangement 17, the cathodes are connected to Hen even-numbered writing electrodes and the anodes are connected to one another for the same reasons (line C).

Depending on a write signal WO , a driver circuit 18 supplies the odd-numbered write electrodes with a voltage V _1n , and another driver circuit 19 supplies the even-numbered write electrodes with the same voltage V _{1n as} a function of a write signal WE. It is possible that the supply voltage provided by the write driver circuits 18, 19 turns out to be lower than an electroluminescence threshold voltage of the thin film EL display panel. In this case, it is necessary to increase the voltage of the driver circuits by a voltage difference. In tests, the voltage V "was 70 V and the voltage V, /, at HOV.

Another diode arrangement 20 comprises a plurality of diodes, the anodes of which are connected to the data electrodes Xi - X _n , and the cathodes of which are connected together - a refresh pulse can be supplied via this diode arrangement.

A refresh driver circuit 15 simultaneously supplies a refresh pulse voltage VR on the basis of a signal REF to the lines B and C of the diode arrays 16 and 17. A further circuit group 21 forms a diverting circuit which becomes effective on the basis of a signal SI during a refresh operating cycle.

The driving operation of a specific writing electrode Y _{1 will be} described below in conjunction with the timing chart of FIG.

At the beginning of the Vi-'eosignalperiode at the Schreibelek- so trode Y ₁ is the data shift pulse DS in the shift register 13-1, the content thereof is sequentially shifted in response to the shift clock signal SC to the write shift pulses DS _x DS _n to produce. The logical AND gates AD _{x -AD n} supply the logical products of the write pulses DSi-DS _n , and the gate signals AP determining the write period and feed them in sequential order to the analog _{gates AGx -AG n} . Since the latter receive the outputs of the logical AND gates ADx-AD _n at their inputs and the video signal V on their common lines, the video signal is only switched through by the analog gates AGx-AG _n in the time slots of the respective gate signal the capacitors Ch leading to the outputs of the Analoggattery4Gi -AG _{n are} charged with the amplitude (voltage) of the video signal in question. In this way get the question, with the data electrodes Xi - X _n connected individual capacitors Ch video signal amplitudes in question.

Pre-charge

Immediately before the end of the video signal period, that is to say while the video signal is still being scanned, the precharge signal PRE is generated in order to excite the activation circuit 11. Under these conditions, the gates of all writing electrode switching elements SS _{x -SS n} receive the set signal SET via the logical OR gates OW _{x -OW n} and are thereby switched on. At this point in time, all driver transistors SD _x -SDn within the modulator circuit 13 are still blocked. These switch-off states are ensured by the fact that all switch elements CCi - CG _{n are switched} on due to the erase pulse CL . It should be noted that the erase pulse C'L covers the entire pulse period of the precharge signal PRE and the set signal SET . Since the activation circuit 11 supplies the voltage V _p via the bus line A , this voltage is also applied to all the picture elements of the thin-film EL display panel via all the data electrodes Xi-Xm. The voltage V _p can be expressed as Vp = V "- V _1n , where V" denotes the electroluminescent voltage of the thin-film EL display panel and V, _n denotes its threshold voltage.

Discharge modulation

After the m-th sampling step of the video signal by the action of the digital shift register 13-1 and after performing the precharge with the beginning of a blanking interval, the clock pulse signal SB reaches all analog gates SCi -SG _m and the supply of the erase pulse CL is interrupted. As a result, the instantaneous amplitudes (voltages) of the video signal, which are stored in the corresponding holding capacitors ch , are delivered simultaneously to the gates of the constant current elements SD _x -SD, - . The setting signal SfT is interrupted as soon as the precharge process has ended. Thus, all of the transistors are now SSi - SS _n locked within the writing electrode switching elements fourteenth

As soon as the video signals stored in the capacitors are output to the constant current elements SD _{x -SD n} , the discharge modulation sequence follows, superimposed on precharge with constant current supply over the duration of each discharge period.

The discharge current id, which flows through a specific transistor SDi , results in

df

(D

Therein, C denotes the sum of the capacities of the individual electrodes, seen from the data electrodes Xi-Xm, and results in C = nCe (Ce = capacitance per picture element of the matrix plate; n = number of all picture elements).

Since the transistors SDx-SD _n act as constant current sources, the discharge voltage V per unit period can be expressed as follows:

-i-

id

German

id

(2)

whereir is the discharge period.

The ratio between the input gate voltage V _t and the drain current id of an N-channel MOS transistor within the modulator circuit 13 can be given as:

id = gmVg.

(3)

The gate / drain counteractive conductance (steepness) of the transistor (a proportional constant) is designated by gm.

If Vg (i) is the input gate voltage of a constant current driver element SDi , which drives a specific data electrode Xi , connected to the modulator circuit 13, and if gm (i) denotes its relative conductivity, the result is the Voltage V (i) of the data electrode Xi after applying the voltage Vgfi) to the gate of the Pulse width is used and fed to the transistors SDi.

Writing operation

In order to excite the respective picture elements E (\, j), E (2, j), ... E (Ij) ... E (m, j) on the side of the writing electrodes Yj during the next video signal period, assume that all transistors SS \ - SSn of write circuit 14 and all transistors SD of modulator circuit 13 are in the blocked state. Under these circumstances, the data electrodes X \ -X _m to which the modulated signal is applied are kept at the voltages V (i), (i- 1,2, ... m) , which are applied to the inputs of the modulation-side elements SD \ _{-SD n} , correspond.

Depending on the output of the digital shift register 14-1, only the one transistor SSj is turned on , which the specific write electro-

ΐαινιιτιι, η, nui

previous formulas (1) and (2):

V, - Ji-r-K-Jg-T

~! - υ .. ™haben. r

(4)

20th

25th

Therein / D denotes the drain current, which is equal to the Discharge current / dist.

The fewer differences there are between the relative capabilities gm of the individual elements SD \ -SD _m in the circuit 13, the more precisely applies gm (i) = * gm (K Φ i) = gm. Then - ^ - can be used as a constant

K and the above formula can be rewritten as follows:

V, (i) ■ τ.

(5)

It can be seen from equation (5) that the input gate voltage Vg (i) of the driver element SD and the period τ of the applied input gate voltage are two parameters for determining the voltage V (i) .

As a result, for the visual display of a halftone image on a thin-film EL display panel by means of amplitude modulation, there is on the one hand the possibility of either feeding a signal to the inputs of the constant current elements SDi which has the variable amplitude corresponding to the video signal for a certain period, or on the other hand the possibility of the To supply the inputs of the constant current elements with another signal that carries the specified voltage amplitude, but has a variable pulse width corresponding to the video signal.The first of the two possibilities could be described as an amplitude modulation control method using an amplitude-modulated input signal, and the latter as an amplitude modulation control with a pulse-width-modulated input signal.

The amplitude-modulated excitation in the case of an amplitude-modulated input signal is carried out in such a way that a voltage-variable signal corresponding to the video signal is applied to the gates of the transistors SDi . The amplitude-modulated excitation in the case of a pulse-width-modulated input signal, on the other hand, is carried out in such a way that a signal corresponding to the video signal is variable remain in the locked state.

If an odd-numbered writing electrode Y _{1 is} to be excited at this moment, the driver circuit 19 switches the bus line C of the diode arrangement 17 connected to the even-numbered writing electrodes to the electroluminescence threshold voltage V _1n . Because at this moment the transistors SD and SS connected to the excited electrodes X \ - X _m and Ki-V _{n are} all in the switched-off state, all electrodes on the write signal side are due to a capacitive coupling between the data electrodes X \ - X _n , and the writing electrodes Y \ - Y _{n are raised} to the voltage V _1n . The voltages V * (i), (i = \, 2, ... m) of the data electrodes X \ - X _n , become small because the "Write" mode is carried out and therefore all write electrodes Yy *, with the exception of the momentary selected writing electrode Yj can be raised to the electroluminescence threshold voltage V, a:

= V (I) + V _th .

(6)

The transistor assigned to the writing electrode Y ₁ is switched on, so that the picture element (I j) on the selected writing electrode Y _{1 is} excited to form electroluminescent radiation corresponding to the writing voltage V ₁ ^ according to formula (6). Meanwhile, the voltage V (i) is applied to the picture elements E (i, k # ^) on the non-selected writing electrodes Yk * 1 .

In order that the selected picture element on the selected writing electrode Y _{1 is} excited to electroluminescence, while the unselected pixels on the unselected writing electrodes Y _k * j are not to be excited, the corresponding voltages on the driver circuits 11, 18 and 19 should be as follows be coordinated:

V (i) <V _p <V _th <V _w {i) (T)

(In the example given, V _p = - V _1n A

If one wants to excite a picture element of an even-numbered writing electrode Y / + during the operating mode "write", the bus B of the diode arrangement 16, which is connected to the odd-numbered writing electrodes, is set to the electrode luminescence threshold voltage by the driver circuit 18

V _1n to switch, and only the transistor SS ₁₊ I is switched through during the period of the write command WP .

The pulse width of the write command WP is approximately half as long as the video signal duration. During the »Write« operating mode, the write voltage is applied for a relatively long time so that undesirable influences cWch changes in the line resistance of the electrodes do not occur.

During this period of time the erase pulse CL is also applied to the switch elements Cd-CG _n , and these are kept in the switched-on state in order to guarantee the switched-off state of the constant current driver elements SDi -SD _n. The switch elements CGt-CG _n are only blocked for the duration of the interruption of the clock signal CL, ie during the horizontal blanking interval. The constant current elements SD \ - SD _m effect the discharge modulation on the basis of a constant current. The reason why the erase pulse CL is applied during the entire period with the exception of the blanking interval is that the thin film EL display panel is a high voltage element (relatively speaking) and the gate inputs of the constant current driver elements via the switch elements CGt-CG _n , are connected to ground with a low impedance in order to avoid undesirable feedback effects on the input side, so that disturbances of the instantaneous amplitude of the video signal held on the capacitors Ch could occur or the operation of the drive elements could become unstable.

In this way, the video signal for the writing electrode Y _{1 is written} , while the video signal for the next writing electrode V, + 1 is interrogated. During the “write” operating mode, the driver circuit 13 queries the video signal of the next write _electrode V 1+ 1. The pre-charging takes place after the end of the write process but before the next blanking interval.

As mentioned, according to the invention, the pre-charging process for the writing electrodes Y _{1 is} effected at the time during which the writing electrode Y _{J +} \ is "interrogated". The discharge modulation process of the write line Y takes place during the blanking interval. The excitation according to the invention thus essentially includes the operating modes pre-charging, discharge modulation and writing.

The timing of the three operating modes mentioned is shown in FIG. 4 with reference to the course of the video signal. F i g. 5 shows the video signal V and the excitation pulses for the data electrodes X, + i. A ", and X, -i and the writing electrodes V, _ ₂ , V, _i and

The aforementioned operational sequences are sequential for the writing electrodes Y \, V ₂ , Vj ... V _n . After the one-time image scanning has been completed, a refresh operation is effected during the blanking interval of the vertical synchronous signal. The refreshing process is brought about by the driver circuit 15, the diode arrangements 16, 17, 20 and the diverter circuit 21 together.

During this period, all transistors SS] - SS _{n of} the write circuit 14 are switched off, as are the counterparts SDt - SD _{m of} the modulator circuit 13. The drive pulses REF and S / are fed to the inputs of the circuits 15 and 21 at the same time, so that the refresh pulse the affects the entire EL panel. The refresh pulse voltage VR is the same as the writing voltage which is applied to the respective writing electrodes for maximum brightness. The refresh pulse VH is applied to the thin-film EL display panel in reverse polarity, so that the writing voltage and the refresh pulse voltage are alternately applied to it. If, to achieve polarization, the picture element is first supplied with the write pulse and then the refresh pulse, the latter is superimposed on an existing electrical polarization field and only those picture elements which have already been described are excited to electroluminescence. Since the degree of polarization of the picture elements already described is proportional to the respective electroluminescence brightness, a luminescence corresponding to the degree of polarization will be present when the refresh pulse is applied, and this enables a halftone display. The fresh impulses have the effect of preventing the polarization from being biased in a certain direction and ensuring that the picture elements already written show electroluminescence during the next picture period when the write voltage is applied.

At the end of the refresh period of the circuit is supplied to the set input SET 14 in order by switching on of transistors SSi - _n SS to derive the refresh voltage VR corresponding charge that has accumulated on the entire panel.

The vertical sync signal and the various control signals REF, SI and SET. which occur during the refreshing process are timed according to FIG. 6 coordinated For the complete display of a television picture, the writing process and the refreshing process are repeated periodically.

For this purpose 4 sheets of drawings

Claims (1)

Patent claims: 1. Circuit arrangement for controlling a matrix-like organized and line-by-line to be scanned video display in the form of a thin-film EL (EIektroIumineszenz) video display panel with a plurality of writing electrodes and a A plurality of data electrodes defining a number of picture elements on the display panel, by means of which a precharge voltage is applied to all picture elements by