GB2055519A

GB2055519A - Digital Frequency Synthesiser

Info

Publication number: GB2055519A
Application number: GB7924877A
Authority: GB
Original assignee: Standard Telephone and Cables PLC
Current assignee: STC PLC
Priority date: 1979-07-17
Filing date: 1979-07-17
Publication date: 1981-03-04
Also published as: GB2055519B

Abstract

An indirect digital frequency synthesiser has an offset frequency synthesiser with a programmable frequency divider 11, which is repeatedly stepped through a predetermined sequence of division factors. The output of the offset synthesiser is fed to two sample and hold circuits 31, 35. One of the sample and hold circuits, 31, is operated after each step in the division sequence, and its output is fed via a fixed frequency divider, 33, to provide, as the offset frequency, the output frequency at the preceding step in the sequence divided by ten. The other sample and hold circuit, 35, is operated at the end of each sequence to hold the output of the offset frequency synthesiser until the end of the next sequence. <IMAGE>

Description

SPECIFICATION Digital Frequency Synthesiser This invention relates to digital frequency synthesisers, in particular for indirect synthesis.

Frequency synthesis is the means by which a range of frequencies may be generated that are related mathematically to a reference frequency and hence exhibit all or some of the stability and spectral purity characteristics of the reference frequency.

Various techniques or systems are known for performing the function of frequency synthesis. In a simple form of indirect frequency synthesiser, Fig. 1, the output of a voltage controlled oscillator 1 is divided by a digital frequency divider 2 the division factor n of which can be set as required.

The output of the divider 2 is applied to a phase detector 3 together with the output of a reference oscillator 4. The phase detector output is applied, via a loop filter 5, to the voltage control connection of the voltage controlled oscillator 1.

By way of example, if the value of n is set to 90 and the reference frequency is 100 KHz then when the frequency of the voltage controlled oscillator is 9 MHz the divided v.c.o. output and the reference frequency will be equal. The output of the phase detector will be proportional to the phase difference and can be arranged to correct for any tendency of the v.c.o. frequency to drift- thus locking the oscillator to 9 MHz. If the division ratio n is changed to 91 then the local oscillator will lock to 9.1 MHz.

In a modified arrangement of the basic synthesiser outlined above additional circuitry is provided to include an offset to the synthesised frequency, proportional to an input frequency f2, as shown in Fig. 2. In the arrangement of Fig. 2 the output f, of v.c.o. 10 is divided down by divider 11 and the resultant is compared with the reference frequency fr from oscillator 12 in phase detector 1 3. The difference signal is fed via loop filter 14 to a second v.c.o. 15, running at frequency f3. The output of v.c.o. 1 5 is applied as one input to a second phase detector 1 6. The output f, of v.c.o. 10 is also applied to a mixer where it is mixed with an offset frequency f2.The resultant from mixer 1 7 is fed to the other input of phase detector 1 6 the output of which is used as a control signal for v.c.o. 10. In this arrangment f=nxfr and f3=(nxf)+f2. For example, if fr=1 00 KHz and n=91 then f,=9.1 MHz. Assume f2=1 .1 MHz then f3=1 0.2 MHz.

If the output f3 of the synthesiser in Fig. 2 is divided by 10 and fed to a further similar synthesiser as the offset frequency f2 for that further synthesiser then a decade of resolution can be achieved. For example, consider the arrangement of Fig. 3 in which six synthesiser blocks are cascaded, each block being the equivalent of that part of Fig. 2 shown within the dotted line. In each case except the extreme left block the offset frequency f2 is the f3 output of the previous block divided by 1 0. All the blocks share the same reference frequency oscillator 20. In block 21 n=9 so the output f3=0.9 MHz. When divided by 10 this provides an offset frequency f2=0.09 MHz for block 22, in which n=6.The output f3 from block 22 is thus 0.69 MHz, which gives an offset frequency f2=0.069 MHz for block 23 and so on. Thus if n in the six blocks is 9, 6, 5, 1,3 and 7 respectively the final output frequency f3 from block 26 will be 0.731569 MHz. The synthesiser block shown within the dotted line in Fig. 2 is hereinafter defined as an "offset synthesiser circuit".

According to the present invention there is provided an indirect digital frequency synthesiser including an offset synthesiser circuit, as hereinbefore defined, and a reference frequency oscillator therefor, first and second sample and hold circuits to both of which the output of the offset synthesiser circuit is applied, a fixed digital frequency divider to which the output of the first sample and hold circuit is applied to form the offset frequency input for the offset synthesiser circuit, and control means arranged to cyclically step the division factor of the frequency division means in the offset synthesiser circuit in a predetermined sequence, the control means also being arranged to operate the first sample and hold means to hold the output of the offset synthesiser circuit after each step in the cycle and to operate the second sample and hold circuit at the end of the cycle to hold the output of the offset synthesiser until the end of the succeeding cycle.

An embodiment of the invention will now be described with reference to Figs. 4 and 5 of the accompanying drawings which illustrate a block diagram of a synthesiser arrangement and the control sequence therefor respectively.

The arrangement shown in Fig. 4 is based on the offset synthesiser circuit of Fig. 2 and in that respect the same reference numerals are used.

The only difference between the offset synthesiser circuit in Fig. 4 and that in Fig. 2 is in the divider 11 which in Fig. 4 is shown as being programmable from a control circuit (not shown).

The output f3 from v.c.o. is fed to a frequency increment store A, comprising a phase 30, sample and hold circuit 31 and voltage controlled oscillator 32. The output of v.c.o. 32 is fed back to the phase detector 30 and also to a divide-by-ten circuit 33, the output of which becomes the offset frequency f2 for the mixer 1 7. Output f3 is also fed to an output frequency store B which consists of a phase detector 34, sample and hold circuit 35 and v.c.o. 36, the output of which is fed back to the phase detector 34. The sample and hold circuits 31 and 35 are operated under the control of the same control circuit that sets the division factors n in divider 11.

Fig. 5 illustrates the operation of the arrangement in Fig. 4. The control circuit sets, in the first step, the factor n=9 in divider 11. At this time it is assumed that the operation is from startup so initially there are no values for f1-f4. Once the division factor n has been set the offset synthesiser circuit will proceed to synthesise an output frequency f3=0.9 MHz (assuming that fr=1 00 KHz), f, being also 0.9 MHz and f2 being at this time zero. Once the offset synthesiser loop has stablished under these conditions the control circuit commands sample and hold circuit 31 to operate and the frequency increment store A stores f3=0.9 MHz. In step 2 the control circuit sets n again (to 9 in this example).Since there is now an output of 0.9 MHz from v.c.o. 32 to divider 33 there is an f2=0.09 MHz input to mixer 17 at the beginning of step 2. Consequently the offset synthesiser circuit will stabilise at f3=f1+f2=0.9+0.09=0.99 MHz. This newt3 is then stored in store A. In step 3 n is set to 10,f2 is now 0.099 MHz and f3 becomes 1.099 MHz. This procedure continues until the last step (e.g. step 5) in the cycle is completed, when not only is f3 stored in store A but also in store B, which then produces the desired output f4. At the end of step 5 the control circuit returns to step 1 and repeats the cycle. f4 is held in store B until the end of step 5 in each cycle when store B is updated.

Thus the complete synthesiser arrangement utilises only one offset synthesiser circuit and reference frequency oscillator circuit to produce as many decades of resolution as are required.

Claims

1. An indirect digital frequency synthesiser including an offset synthesiser circuit, as hereinbefore defined, and a reference frequency oscillator therefor, first and second sample and hold circuits to both of which the output of the offset synthesiser circuit is applied, a fixed digital frequency divider to which the output of the first sample and hold circuit is applied to form the offset frequency input for the offset synthesiser circuit, and control means arranged to cyclically step the division factor of the frequency division means in the offset synthesiser circuit in a predetermined sequence, the control means also being arranged to operate the first sample and hold means to hold the output of the offset synthesiser circuit after each step in the cycle and to operate the second sample and hold circuit at the end of the cycle to hold the output of the offset synthesiser until the end of the succeeding cycle.

2. A synthesiser according to claim 1 wherein each sample and hold circuit includes a phase detector to one input of which the output of the offset synthesiser circuit is applied, the output of the phase detector being applied to the sample and hold circuit the output of which is applied to a voltage controlled oscillator as the control signal therefor, and a feedback connection from the output of the v.c.o. to the other input of the phase detector.

3. A synthesiser according to claim 1 or 2 wherein the fixed digital frequency divider has a division factor of 10.

4. An indirect digital frequency synthesiser substantially as describes with reference to Fig. 4 of the accompanying drawings.