GB2053701A - Electronic chess game - Google Patents

Abstract

An electronic apparatus, for simulating the playing of chess, includes its own liquid crystal display. The display can include a region for displaying any chess piece together with alpha numeric information regarding the coordinates of a piece being moved. The display for the chess piece is built up by a hollow basic outline 10 which represents a white pawn, a solid interior 12 for the outline to convert the piece to a black piece and a number of additive shapes positioned adjacent the upper end of the outline for representing the capital pieces. Alternatively, a complete chess board is formed by a liquid crystal display where at each square a chess piece can be represented as above. A separate micro-processor and multiplexing are provided for the display. The game is stated to be applicable to draughts. <IMAGE>

Description

SPECIFICATION Improvements in electronic game apparatus This invention relates to electronic game apparatus.

In particular the invention relates to electronic game apparatus which is capable of simulating the playing of board games such as chess, draughts, checkers, Shogi and the like.

Such electronic games are known and have been achieved in the past by means of a suitably programmed micro-processor and a display provided on the cathode ray tube of, for example, a television set, or by means of a light emitting diode display. Suitable miniature programmed micro-processors are available. Disadvantages of the present game apparatus are the necessity to use a television set which makes the apparatus non-portable. Alternatively if a light emitting diode display is used this is complicated and expensive, requires a large number of electrical connections, and has a relatively large power requirement so that again the apparatus cannot be conveniently portable with its own power supply.

The invention has therefore been made with these points in mind.

According to the invention there is provided an electronic game apparatus capable of simulating the playing of at least a game of chess, the apparatus including an inputfora playerto inform the apparatus of moves made by the player, a programmed micro-processor to which the move input information is supplied in a form for assimilation, the game micro-processor providing a response move output to inform the player of the apparatus of the response of the processor, and a liquid crystal display for displaying the moves of the game, the display being capable of providing at least the display of any chess piece and alpha numeric information for specifying the coordinates of a particular piece being or to be moved, the liquid crystal displayforthe chess piece being capable of representing any chess piece by means of a building block system including a basic piece outline for a pawn, a solid interior within the outline for differentiating between black and white pieces and a number of additive shapes positioned adjacent the upper end of the outline for representing capital pieces.

Such apparatus can be relatively compact and of relatively low power consumption and so can be portable. Also because each chess piece is represented by building up on a basic piece outline and each piece does not require an individual connection for it to be displayed, the chess piece display can be relatively simple electrically, particularly as regards the number of electrical connections to the liquid crystal display. Preferably there are fewer additive shapes than different capital pieces so that some of the capital pieces are formed by a combination of additive shapes.Thus the display in apparatus of the invention need require, for example, only sb electrical connections plus a common backplane connection to display all 12 possible different chess pieces, namely a white and a black set of pawn, bishop, knight, king, queen and rook, whereas if each piece has its own liquid crystal outline, 14 connections or 12 plus the backplane, would be required.

Each of the various additive shapes can be a single continuous area or a combination of two or more discontinuous areas. The particular outline of the various additive shapes is chosen so that they can be combined to give distinct yet attractive overall shapes to the capital pieces. In this connection the theoretical minimum number of additives shapes required to give the five different capital pieces for each colour is three. In practice, however, it is often desirable to choose four additive shapes to give more attractive and distinct appearances to the capital pieces.

The alpha numeric display which gives move indication information can be a conventional 7segment display which must be capable of displaying one of the letters A to H or a number from 1 to 8 so as to be able to identify the coordinates of each square on a chess board. The alpha numeric display must contain at least two such 7-segment displays so as to give both a letter from A to H and a number from 1 to 8 which can display the initial square of the piece and thereafter the final square of a piece during a move. Preferably, however, there are four 7-segment displays so that initial and final squares for a move can be shown simultaneously. In this latter case, the display will require 28 electrical connections for the alpha numeric display and the common backplane connection.

Finally the display desirably contains a number of annunciator indicators, e.g. 6, for indicating various steps in the game, e.g. check, check-mate, stalemate/ draw, piece-capture, which colour is being played by the computer and the fact that computer is computer ing and so the player must wait before making the next move. For 6 such indicators therefore 6 electrical connections plus the common backplane connection are required.

Therefore such a display including the display of any chess piece, four 7-segment alpha numeric displays and six annunciator indicators will require only a total of forty electrical connections plus the common barttplane connection to indicate the total progress of the game.

The display can be driven by a parallel direct drive from, for example, the game micro-processor but preferably the data from the game micro-processor to be displayed is placed in a static serial shift register having sufficient, parallel complementary outputs, e.g. 40 outputs for the case noted above, these outputs driving the segments of the display directly. Suitable miniature static serial shift register circuits are available commercially and in the event that a particular circuit has insufficient bits, it can be extended to the required 40 bits by combining with one or more additional shift registers.

in addition or alternatively the electronic game apparatus can provide full analog representation of a chess board by means of a liquid crystal display of the whole board. Clearly an impractically large number of electrical connections would be required if at each of the 64 squares on the board 12 electrical connections were required, one for each of 12 pieces possible at each position. Accordingly, the invention aims according to a further aspect to reduce the number of connections to a reasonable figure.

Therefore according to another aspect of the invention there is provided an electronic game apparatus capable of simulating the playing of at least a game of chess, the apparatus including an input for a player to inform the apparatus of moves made by the player, a programmed game microprocessor to which the input information is supplied in a form for assimulation and the micro-processor providing an output response, a liquid crystal output display which at each of the 64 squares of the board is capable of providing a display of any chess piece, the liquid crystal display for the chess piece at each square of the board being capable of being represented by means of a building block system including a basic chess piece outline for a pawn, a solid interior within that outline for differentiating between black and white pieces and a number of additive shapes positioned adjacent the upper end of the outline for representing capital pieces, and liquid crystal display driving means for receiving the output response from the micro-processor and driving the liquid crystal display so as to show the up-to-date square of each piece on the board, the driving means including at least 3-fold multiplexing.

Such an apparatus can additionally be provided with a separate display for an individual chess piece to show which piece is being moved in a particular move and an alpha numeric display specifying the coordinates of the piece being moved. Such a display should desirably be as previously described.

By providing a display which uses both the building blocksystem or representing pieces and multiplexing it is possible to reduce the number of electrical connections to be made to a reasonable number. Thus each square need require only 6 connections plus the common backplane and multiplexing can reduce the total to the order of 100 for 4-fold backplane multiplexing and 135 for 3sold backplane multiplexing connections.

This is still a large number of connections and to handle the multiplexing we have found according to one embodiment that there should be on-line microprocessor control of wave4orms of the signals applied to the liquid crystal display at all time and phases. There are a number of ways in which this can be achieved.

According to one preferred embodiment of the invention the liquid crystal display driving means is a master micro-processor which is arranged to receive position data for each piece in the game from the game micro-processor through an exterior connection, the master micro-processor controlling the board display. The multiplexing is AC and static shift registers driven by the master micro-processor must be updated every 1/2n periods where n is the degree of multiplexing and the period is the time required for each cycle of the liquid crystal display drive clock.

In such an embodiment a relatively simple master micro-processor can be used with a limited number of input'output lines connected with relatively large static shift registers having parallel complementary outputs which drive the output display directly.

According to another preferred embodiment of the invention two or more simple 1-chip microprocessors with a sufficiently large number of outputs are provided to drive the multiplexed display directly. Each ofthese micro-processors will have an identical program and they are interconnected so that one is the master and the other or others is a slave. Then the master defines the clock for the multiplexing and is linked to the game micro-processor for inpuVoutput whilst the slave or slaves only receive information from the master and drives its portion of the display according to the commands received from the master.

In order to provide the highest quality of chess game from the game micro-processor, this microprocessor should be allowed to devote its whole capacity to the game program whilst it is computing its move. Therefore, according to a preferred embo dimentofthe invention, the game micro-processor does not drive the display except when the contents of the display are to be changed. Instead the display is driven by fbted-logic units which maintain the existing appearance of the display but which can be updated when there is a change made in the positions of the pieces after the entry of a move in the game. This can be achieved by providing means which repeatedly deliver to a driver for the display a stream of data which cause the display to show repeatedly the present board positions.Thus, the game micro-processor, having once instructed the fixed-logic units to display a particular board position, need not take any further part in what is displayed since the logic units repeatedly display this position until the game micro-processor undates and changes the display and then the fixed logic units repeatedly cause the display to show the changed position.

According to one approach within this preferred embodiment, the data for the display circulates continuously around a closed loop formed by a segment driver shift register for the liquid crystal display (LCD) underthe control of a clock, controller and counter. The storage shift register is controlled in such a way that the game micro-processor can feed in a new chessboard position when required.

An advantage of this arrangement is that the counter can provide the signal required to drive the LCD backplanes.

According to another approach within this preferred embodiment, a random access memory (RAM) and LCD segment driver shift register are provided together with a counter driven by a clock. The RAM provides the LCD segment driver with a constant flow of data but the segment driver does not need to feed the data back into the RAM since this stores the data and repeatedly delivers to the LCD segment driver shift register. The RAM is arranged to provide the data for driving the display under the control of the clock and when the game micro-processor wishes to update board position, it must take over from the clock and the RAM switched into its "write" mode for insertion of new data corresponding to the new board position. Once this is complete the game micro-processor can then release the RAM and allow it to become under the control of clock again so that it again repeatedly delivers board information to the LCD segment driver shift register, this time of the new board position.

The invention will now be described, by way of example, with reference to the accompanying drawings, in which: Figure 1 is a diagram showing how the various chess pieces are built up by the liquid crystal display; Figure2 is a diagram of game apparatus including a liquid crystal display according to one form ofthe the invention showing the white queen as an example of a chess piece to be displayed; Figure 3 is a diagram illustrating one form of drive for the liquid crystal display forming part of the apparatus of Figure 2; Figure 4 is a view of a chess board formed by a liquid crystal display showing the initial positions of the chess pieces; Figure 5 is a block diagram of one form of control circuitry for the display shown in Figure 4; Figure 6 is a block diagram of another form of control circuitry for the display shown in Figure 4;; Figure 7 is a block diagram of another form of control circuitry for the display shown in Figure 4; Figure 8 is a block diagram of a further form of control circuitry for the display shown in Figure 4; Figure 9 is a logic diagram for one embodiment for the circuitry as shown in Figure 8; and Figure 10 is a logic diagram for another embodiment for the circuitry as shown in Figure 8.

Referring first to Figure 1, this shows how the various chess pieces can be formed in a liquid crystal display by following the teachings of the invention.

Thus, a basic chess piece outline 10 is given to all pieces and as seen in the key forming part of the Figure that outline appears in each type of piece. The outline 10 has an open centre 12 and to differentiate between black and white pieces that centre is made to appear dark or not, respectively.

The basic outline 10 with or without the centre 12 represents a black or white pawn. To display capital pieces regions 12 at or near the top of the basic outline 10 are made to appear and the key forming part of Figure 1 shows which regions are used to represent which capital pieces. A separate region 12 is not provided for each capital piece. Instead, as shown in the key, the capital pieces are built up by combination of only four regions 12 some of which are continuous areas and some of which are discontinuous areas.

There are many possible different shapes which can be given to the various chess pieces. According to the invention, however, one needs some form of basic outline such as the outline 10, a centre which can differentiate between black and white pieces and regions 12 at or near the top of the outline 10 to represent the various capital pieces.

Figure 3 shows a liquid crystal display of a complete chess board 20 with the various pieces shown in their initial starting positions. Each square, whether black or white, of the board has an identical capability of representing any piece at that square.

Figure 2 is a diagrammatic representation of one form of game apparatus 30 according to the present invention. The game apparatus has a liquid crystal display 32 positioned in a housing 34 forthe apparatus.

The display 32 includes a section 36 for displaying a chess piece in accordance with the building block system as described above. It includes four further sections 38 to 41 which are capable of providing alpha numeric material. Each of these sections 38 to 41 is in the form of a conventional 7-segment display capable of providing one of the letters A to H or the numbers from 1 to 8 for identifying the coordinates of a position on the chess board. In addition to this, six further annunciator segments 42 are provided.

These segments are in the form of small squares which can be caused to appear or not depending upon various functions of the chess game. For example, six functions which these segments 42 can display are check, checkmate, stalemate/draw, piece capture, the colour played by the computer and the fact that the computer is computing so that the player must wait before his next move.

The display 32 is controlled by a static serial shift register 44 which receives information from the programmed game micro-processor 46. Input information is provided for the processor 46 from a keyboard 48 by means of which the player selects the coordinates of a piece to be moved and the coordinates of the square to which the piece is to be moved. The apparatus shows the piece to be moved in the region 36, the initial square of that piece in the sections 38 and 39 and the final square in the sections 40 and 41. As soon as the first two coordinates have to be entered on the keyboard 48 and displayed in the sections 38 and 39, the display 36 is arranged to show the piece on that square and when the keyboard 48 has been operated to input the move, then if this results, for example, in a piece capture this will be announced by one of the annunciator segments 42.Then the processor 46 will compute the situation on the chess board and another of the segments 42 will show this and in due course when the game micro-processor has decided on its move, this will be displayed in the same way by giving the initial co-ordinates of the piece to be moved in the sections 38 and 39, the final coordinates with sections 40 and 41, and the piece in question in the region 36.

The apparatus is provided with an on/off switch 49 and a power source 50, which can be a rechargeable battery or mains transformer, to power the various parts of the apparatus.

Since each chess piece is built up on a building block system by causing, in conventional fashion with a liquid crystal display, various segments to appear within the region 36, it will be appreciated that rather than having to have one or two electrical connections for each chess piece in the region 36 it is possible to reduce this number very significantly.

Thus, it is only necessary to provide six electrical connections plus the common backplane to display any chess piece in the region 36. Each conventional 7-segment display in the sections 38 to 41 require seven electrical connections, one for each segment making a total of twenty-eight connections to the display 32 plus the common backplane, and finally each annunciator segment requires an electrical connection plus the common backplane making a further six connections. This means that only a total of forty electrical connections to the display 36 are required plus the common backplane and this is a practicable proposition and does not involve any excess costs as would be necessary if each chess piece were to be displayed at an individual position.

In addition, a liquid crystal display, as opposed to, say, a light emitting diode display, has only very low power consumption and so the apparatus 30 can be relatively compact and be provided with its own electrical power source 50 such as a rechargeable battery.

The forty connections for the display 32 still represent quite a large number and so instead of driving the display with a conventional parallel direct drive from the game processor, the display is driven by the static serial shift register 44 which has forty parallel complementary outputs. Suitable miniature static-serial shift register circuits are readily available integrated circuits. In some cases, however, available registers may not have a sufficiently large number of parallel complementary outputs. Therefore, according to a preferred embodiment this can be overcome by extending smaller shift registers by adding on additional shift registers in the manner shown in Figure 3. Thus, a suitable static serial shift register44a is that marketed by Mitei Corp. under part No. Mitel MD4332 and is a 32 bit register.Added to this are two further small shift registers such as can be found on a chip marketed commercially by RCA under the part No. 4015B. As can be seen these shift registers are tied in to the clock frequency for the display 32 and they merely extend the register 44 to 40 bits. Both they and the register MD4332 drive the various segments of the display 32 directly. The shift register 44 receives information regarding the piece to be displayed, coordinates and so on directly from the game micro-processor 46 which is not itself used to drive the display directly. This has the advantage that the game micro-processor can be programmed to deal exclusively with the game and so a more sophisticated programme can be used than would be the case if part of it had to be used to control the liquid crystal display 32.Additionally, a greater proportion of the processing power of the micro-processor can be devoted to strategy so giving a higher quality game.

A more sophisticated output display can be provided by a liquid crystal display which shows a full chess board with the up-to-date position of each piece. Such a display 20 is shown in Figure 3 and can be used as an ancillary to the game apparatus30 shown in Figure 2. Thus the display 20 can be provided in addition to the apparatus 32 as, for example, an optional extra which can be attached by suitable electrical connections not shown in Figure 2.

Alternatively the display 20 can form part of a separate chess game apparatus having its own game micro-processor.

The display 20 is driven by its own microprocessor which controls the display 20 upon receipt of information from the game micro-processor 46 regarding the positions of the chess pieces.

By the use of the building block system, to simulate a chess piece one can reduce the number of electrical connections required at each position on the chess board of the display 20 but with six connections plus a common backplane, the sixtyfour positions of the display of the board would still require over 380 connections which would be prohibitively expensive and complicated. Therefore, multiplexing of that display which is at ieast 3-fold and preferably at least 4fold is used. Most preferably, the multi-plexing is 8-fold. Higher degrees of multiplexing, e.g. up to 16 are also possible and reduce the number of the connections required.

Thus, by adopting 4-fold multiplexing the number of connections to the display 20 which are required are of the order of 100 connections and by adapting 8-fold multi-plexing there can be .384 segments for 56 connections. As noted above, the game microprocessor 46 is not used to drive the display 20.

Instead, the display 20 has its own micro-processor which receives information from the separate game micro-procesor so that the display micro-processor is on line at all times and controls the wave forms of the signal sent to the display at all times and at all phases.

According to one embodiment as shown in Figure 4, this is achieved by using a liquid crystal display micro-processor 51 and a large static shift register 52 which receives information from the microprocessor 51 to drive the display 20. The microprocessor 51 receives information about the position of each chess piece from the game micro-processor 46. In addition, it has four output backplane signals which feed directly to the display 20 for 4-fold multiplexing. Further, it has an output 5 giving a data strobe signal and an output 6 which gives the serial data to the shift register 52 regarding the various segments to be displayed.Since A/C multiplexing is used, the static shift register must be up-dated every 1/(2x4) periods for 4-fold multiplexing, the period being the time required for one cycle of the liquid crystal display drive clock provided by the data/ strobe output 5. In this way, the micro-processor 51 can be relatively simple but it is used with a large static shift register 52.

Ninety-six outputs are required from the shift register 52 and normally simple and compact large shift registers will not be available. According to the invention this can be overcome by linking a number of smaller shift registers in series. A shift register is available from Mitel Corp. under reference No.

MD4332 having 32 outputs and by linking 3 of these in series one can provide the effect of the large shift register having ninety-six output lines which feed directly to the connections on the display 20.

An alternative embodiment for controlling the liquid crystal display 20 is shown in Figure 6. This uses two micro-processors 60 and 62 which are linked so that the processor 60 is the master and processor 62 is the slave. As a result, the combined micro-processor has a much higher number of outputs than the processor 51 described in Figure 5 and so the combined processor can drive the display directly. Each micro-processor 60 and 62 has an identical programme and, if required, more than one slave 62 may be provided. The master processor 60 defines the clock and provides synchronising pulses through a line 64 to its slave. It receives input information from the game micro-procesor 46 and supplies to the latter information regarding the liquid crystal display 20. The slave micro-processor 62 does not interact directly with the game microprocessor.In addition, a memory 66 is provided to keep track ofn the display required on the liquid crystal display 20. The micro-processors-60 and 62 drive the liquid crystal.dispiay directly and because they can be identical micro-processors this simplifies the stock for the manufacturers and enables them to be obtained more cheaply in larger numbers.

In various embodiments described above, the game micro-processor 46 has not been described in detail since suitable programmed micro-processors for playing a game of chess are commercially available and form no part on their own, of the present invention.

It is desirable to allow the game micro-processor to concentrate all its capacity on the game programme whilst it is computing a move. Therefore, it may be undesirable if some of the capacity of the game micro-processor has to be used in controlling the LCD display whilst the game micro-processor is computing. In this way, one can provide the highest quality of a chess game from a particular microprocessor.Therefore, according to preferred embodiments of the invention, the display is driven by fixed-logic units whose function is basically to maintain the existing appearance of the display but which can be updated from time to time when a change is made in the positions of the pieces after the entry of a move and thereafter these fixed logic units will maintain the updated appearance until a further move is made when a further updated appearance will be maintained and soon. In this way, it is only necessary for the game microprocessor to update the fixed logic units from time to time after entry of a move with the result that it can concentrate its computing ability on a move to be made when it is computing a possible move.

In practice, the use of a number of dedicated inflexible fixed-logic units in place of a microprocessor to drive the LCD may give a cheaper solution than the use of further micro-processor to drive the display although much does depend upon other factors including the current capacity available and the space available.

Referring to Figure 7, this shows in block diagram one form of control circuitry for driving the LCD display 20. The display is driven by an LCD segment driver 70 in the form of a shift register which receives information from a storage shift register 72. The LCD segment driver 70 has sufficient parallel outputs to drive the display. The storage shift register 72 must have a capacity at least equal to the degree of multiplexing less one times the number of outputs from the LCD segment driver. The storage shift register 72 also has a recirculation line 74.

A clock 75 which includes a control gate 76 and a counter 78 are also provided. These cause the shift register loop of data in the register 72 to advance as many bits as are required to drive the display segments. This logic also controls the storage shift register 72 in such a way as to allow the game micro-processor 46 to feed in a new data pattern corresponding to a new chessboard position.

Also, it will be noted that the counter 78 provides an output signal to drive an LCD back plane driver 80 to provide the required multiplexed output from the display 20. This back plane driver 80 is separate from the storage shift register 72 and receives a separate output from the counter.

Turning next to Figure 8, this shows an alternative embodiment to that shown in Figure 7. In this embodiment, a RAM 82 is provided which drives the LCD segment driver 70 which in turn drives the display 20. The RAM 82 provides the driver 70 with a constant flow of data but unlike the embodiment shown in Figure 7, the data from the segment driver does not need to be fed back into the RAM 82 since the memory of the RAM contains data corresponding to the update position of the LCD display.

The stream of data from the RAM 82 is generated by sequentially scanning the RAM by valid addresses from a counter 84 to the RAM address inputs in the "read" mode. The counter is driven by an external clock 86 through a multiplexer 88. This clockcan be a separate oscillator or can, for example, be a stream of pulses generated by the microprocessor 46.

In order to enter a new position on the display 20, the micro-processor 46 takes control of the RAM 82 by switching the multiplexer 88 from the external clock 86 to its own update clock and switches the RAM into the "write" mode. It also resets the counter to zero and steps through to the addresses it wishes to change and at that point writes data into the corresponding RAM locations. Once the writing process is over, the micro-processor releases the counter 84 which then comes back under the control of the external clock 86 so that the RAM can then repeatedly feed to the driver 70 a stream of data corresponding now to the updated board position.

The LCD display has a back plane driver 90 which is driven by the output from the counter.

The embodiment shown in Figure 8 can be put into practice using well-known components and Figures 9 and 10 show alternative ways of putting the embodiment of Figure 8 into practice.

Referring to Figure 9, the clock 86 pulses into the circuit via the multiplexer 88. The counter 84 takes its input from the multiplexer 88 and generates addresses to a single RAM 82. This is conveniently of the type sold under the No. 2102 as a static random access memory by Synertek. The output data from the RAM 82 is fed to the drivers 70 and 90 which are respectively formed by serial input LCD drivers of the type sold under the Nos. 0538 and 0539 by Hughes Aircraft Company. The RAM 82 outputs its data in a normal way to the drivers 70 and 90 but output Q5 from the counter also passes through a multiplexer circuit 92 which switches on the driver 70 for the first part of the data stream on the RAM 82 and then switches over to the driver 90 for the second part.

In all units, a iock back function 94 is provided under user control and the game micro-processor 46 control to allow the user to see on the display 20 an alternative board position, e.g. the previous board position which can be stored in the upper address space half of the RAM 82.

Via an update line 96 the micro-processor can, through the multiplexer 88, seize control of the RAM 82 when its memory is to be updated as the result of a move being entered into the game microprocessor.

The logic circuit shown in Figure 10 has been simplified in comparison with that shown in Figure 9 by the use of drivers 98 of the type sold under the NO. HLCD 0438 sold by Hughes Aircraft Company.

These work on the Serial In, Serial and Parailel Out (SISPO) basis. These two drivers 98 are then treated as equivalent to a single long shift register and so it is possible to eliminate the switch over circuitry of the multiplexer 92. Since the drivers 98 do not provide signals for multiplexed back plane drive, a row driver 100 is provided which takes its data from the counter 84. Additionally, a monostable multivibrator 102 is provided to form a trivial servicing function required by the drivers 98. The provision of the row driver 100 enables one to have different peak to peak voltages for the back plane drive and the individual segment drive in the display.

Claims (17)

1. An electronic game apparatus capable of simulating the playing of at least a game of chess, the apparatus including an input for a player to inform the apparatus of moves made by the player, a programmed game micro-processorto which the move input information is supplied in a form for assimilation, the game micro-processor providing a response to inform the player of the apparatus of the response of the processor, and a liquid crystal output display for displaying the moves of the game, the display being capable of providing at least the display of any chess piece and alpha numeric information for specifying the coordinates of a particular piece being or to be moved, the liquid crystal display for the chess piece being capable of representing any chess piece by means of a building block system including a basic piece outline for a pawn, a solid interior within the outline for differentiating between black and white pieces and a number of additive shapes positioned adjacent the upper end of the outline for representing capital pieces.

2. Apparatus as claimed in Claim 1 in which the capital pieces are constituted by combining the additive shapes and that there are fewer additive shapes than capital pieces.

3. Apparatus as claimed in Claim 1 or Claim 2 in which the display includes a region for displaying any chess piece and at least 2 sections for providing alpha numeric information to give coordinates on a chess board.

4. Apparatus as claimed in Claim 3 in which the display includes 4 sections providing alpha numeric information to give initial and final coordinates for the movement of a chess piece.

5. Apparatus as claimed in Claim 3 or Claim 4 in which the display additionally includes annunciator segments for further information on the progress of a chess game.

6. Apparatus as claimed in any preceding claim in which data from the game micro-processor to be displayed in the display is placed in a static serial shift register having a parallel complementary output for each segment of the display, these parallel complementary outputs driving the display directly.

7. An electronic game apparatus capable of simulating the playing of at least a game of chess, the apparatus including an input for a player to inform the apparatus of moves made by the player, a programmed game micro-processor to which the input information is supplied in a form for assimulation and the micro-processor providing an output response, a liquid crystal output display which at each of the squares of the board is capable of providing a display of any chess piece, the liquid crystal displayforthe chess piece at each square of the board being capable of being represented by means of a building block system including a basic chess piece outline for a pawn, any solid interior within that outline for differentiating between black and white pieces and a number of additive shapes positioned adjacent the upper end of the outline for representing capital pieces and liquid crystal display driving means for receiving the output response from the micro-processor and driving the liquid crystal display so as to show the up-to-date square of each piece on the board, the driving means including at least 3-fold multiplexing.

8. Apparatus as claimed in Claim 7.in which the driving means includes 4-fold multiplexing.

9. Apparatus as claimed in Claim 7 or Claim 8 in which the capital pieces are constituted by combining the additive shapes so that there are fewer additive shapes than capital pieces.

10. Apparatus as claimed in any of claims 7 to 9 in which the driving means for the liquid crystal display include a master micro-processor and a static shift register driven by the master microprocessor, the static shift register having parallel complementary outputs which drive the output display directly.

11. Apparatus as claimed in Claim 10 in which the static shift register is formed from two or more registers linked in series.

12. Apparatus as claimed in any of claims 7 to 9 in which the driving means for the liquid crystal display include at least two micro-processorchips which have identical programs, which have a total number of outputs sufficient for driving the display directly, and which are linked so that one is the master and the other or others are slaves, the master micro-processor defining the clock for the multiplexing and being linked with the game micro-processor whilst the slave or slaves are arranged to receive infdrmation solely from the master.

13. Apparatus as claimed in any of claims 7 to 9 in which the display is driven by fixed-logic units which repeatedly delivers to a driver for the display a stream of data which cause the display to show repeatedly the present board position, the game micro-processor changing the stream of data when a move is entered.

14. Apparatus as claimed in Claim 13 in which the data for the display circulates continuously around a closed loop formed by a segment driver shift register for the display under the control of a clock, a controller and a counter.

15. Apparatus as claimed in Claim 13 further comprising a random access memory and a display segment driver shift register receiving data from the memory, a clock and a counter controlling the repeated supply of data from the memory to the drive shift register, the random access memory being switched to its "write" mode by the game micro-processor when new data corresponding to a new board position is inserted.

16. Apparatus as claimed in any of claims 7 to 12 combined with apparatus as claimed in any of claims 1 to 6.

17. An electronic game apparatus substantially as herein described with reference to Figures 1 to 3, Figure 4, Figures 4 and 5 or Figures 4 and 6, of the accompanying drawings.