GB2052810A

GB2052810A - Display device for an electronic timepiece

Info

Publication number: GB2052810A
Application number: GB8018139A
Authority: GB
Original assignee: Seikosha KK
Current assignee: Seikosha KK
Priority date: 1979-06-07
Filing date: 1980-06-03
Publication date: 1981-01-28
Also published as: FR2458833A1; JPS55163487A; HK56585A; FR2458833B1; CH650124GA3; JPH0115838B2; GB2052810B; DE3021257A1; SG33585G

Abstract

A display device for an electronic timepiece has 60 radially arranged segment electrodes (27a) Fig. 2 and three rings of common electrodes (28a, 28b, 28d) Fig. 3. A liquid crystal material is disposed between the segment electrodes and the common electrodes and the arrangement produces a time display simulating that given by a timepiece with mechanical hands. The outermost common electrode ring (28d) constitutes an electro- optical graduated time scale which is either permanently energised or can be used to indicate seconds. <IMAGE>

Description

SPECIFICATION Display device for an electronic timepiece This invention relates to display devices for electronic timepieces.

Electronic wrist watches are known in which a liquid crystal display device produces an analog time display simulating that produced by the hands of a mechanical watch. In such wrist watches, a graduated time scale is formed by printing separately from the liquid crystal display device, so that the position of the "hands" in relation to the time scale appears to differ depending upon the direction of angle of observation due to the influence of the thickness of the display device and parallax effects. In addition, a considerable amount of labour is necessary to adjust the position of printing of the time scale in relation to the positions of the "hands".

According to the present invention there is provided a display device for an electronic timepiece comprising: an electro-optical time display device for producing a time indication in analog form and an electro-optical graduated time scale.

In one embodiment of the present invention the display device includes means for successively de-energising graduations of the time scale to indicate the passage of time.

Preferably the display device optically produces a time display simulating that given by a timepiece with mechanical house and minutes hands and in which a segment electrode arrangement consists of 60 radial electrodes equally spaced apart around a circle, and a common electrode arrangement arranged in three rings, the outermost ring constituting the said time scale.

According to another aspect of the present invention there is provided an electronic timepiece having a display device as recited above.

The invention is illustrated, merely by way of example, in the accompanying drawings, in which: Figures 1A and 1B are circuit diagrams of an electronic timepiece having a display device according to the present invention; Figure 2 is a plan view of a segment electrode arrangement of the display device of Figs. 1 A and 1 B; Figure 3 is a plan view of a common electrode arrangement of the display device of Figs. hand 1B; Figures 4 to 6 are circuit diagrams of parts of the electronic timepiece of Figs. 1A and 1 B; Figure 7 is a timing chart of voltage pulses to explain the operation of the electronic timepiece shown in Figs. 1A and 1B; Figure 8 is an illustration of a display produced by the display device of Figs. 1A and 1 B; and Figures 9 to 12 illustrate another embodiment of an electronic timepiece having a display device according to the present invention.

Referring to Figs. 1 A and 1 B, there is illustrated an electronic timepiece having a display device according to the present invention. The output signal from a quartz crystal oscillator 1 is frequency divided by a frequency divider 2 and is supplied to a decimal counter 3 to count units of seconds. A carry output from the counter 3 is supplied to a seconds counter 4. Decimal counters 5, 6 count units of minutes and counters 7, 8 count units of hours from carry outputs of the preceding counter stage. These counters are adapted to produce binary coded decimal outputs. A duodecimal counter 9 is adapted to count time upon receipt of the output from the counter 4 and produces a carry output which is supplied to the counter 7.

A timing pulse generating circuit 10 produces timing pulses successively at terminals P, to P3 upon receipt of an output pulse of, for example, 1 28 Hz from the frequency divider 2. Opening and closing of gate circuits 11 to 1 6 having AND logical function is controlled by these timing pulses, thereby to control the supply of outputs from the counters 3 to 8 to OR gate circuits 17, 18.

Decoders 19, 20 convert the codes of outputs from the gate circuits 17, 1 8. An output conversion circuit 21 is adapted to alter the order of generation of signals in accordance with the odd number value and even number value of the output date from the gate circuit 1 8. These outputs are applied to a segment voltage supplying circuit 22 adapted to select the voltage to be applied to segment electrodes which will be described in greater detail hereinafter. A common electrode, which will also be described in greater detail later, is adapted to be supplied with a voltage selectively by a common voltage supplying circuit 23. A pulse cyclically generated at the output terminal P1 of the timing pulse generator 10 is divided by 2 by means of a flip-flop circuit 24, and is applied to a voltage selector 25.

Voltages 0, vO, 2vo and 3vo are periodically generated at terminals SO, S1, CO, C1 respectively in synchronism with the signal applied to the voltage selector 25. A reference numeral 26 denotes an inverter.

Figs. 2 and 3 illustrate the electrode arrangement of a liquid crystal display of the electronic timepiece of Figs. 1A and 1 B.

A segment electrode arrangement 27 shown in Fig. 2 consists of 60 segment electrodes 27a radially arranged, 10 of which are connected as illustrated to terminals e1-e10 of the segment voltage supply circuit 22. Other segment electrodes are connected as follows. In the following description the segment electrodes are counted in the clockwise direction from the segment elec trode 27a connected to the terminal e1. The tenth segment electrode is connected to the eleventh segment electrode. Similarly the ninth segment electrode is connected to the twelfth segment electrode.The first segment electrode and the twentieth segment electrode, the twentieth segment electrode and the twenty-first segment electrode, the nineteenth segment electrode and the twenty-second segment electrode, and the eleventh segment electrode and the thirtieth segment electrode are connected to each other, respectively. Similar connections are made up to the sixtieth segment electrode.

Fig. 3 shows a common electrode arrangement 28. There will be seen that there is an outer common electrode 28d, an intermediate common electrode 28b and an inner common electrode 28a each of which is divided in the circumferential direction into six sections.

The outer common electrode 28dcarries indicia or marks M1 to M12 formed thereon corresponding to positions of 1 o'clock to 1 2 o'clock.

Grooves 26cseparating the adjacent sections of the common electrodes 28a, 28b are positioned between the tenth and eleventh segment electrodes 27a, twentieth and twenty-first segment electrodes, thirtieth and thirty-first segment electrodes, fortieth and fourty-first segment electrodes, fiftieth and fifty-first segment electrodes and sixtieth and first segment electrodes, respectively, counted in the clockwise direction.

The liquid crystal display device according to the present invention is constituted by an assembly of display sections including a liquid crystal material interposed between the segment electrode arrangement of Fig. 2 and the common electrode arrangement of Fig. 3.

Detailed description of the liquid crystal display device is omitted.

Fig. 4 shows, in detail, the output conversion circuit 21 and the segment voltage supplying circuit 22 which are constituted by analog switching circuits 44-53, AND gate circuits 29-38, OR gate circuits 39-43 and inverters 54-58.

Fig. 5 shows, in detail, the voltage selecting circuit 25 which is constituted by switching circuits 59 to 74 and inverters 75, 76.

Fig. 6 shows in detail the common voltage supplying circuit 23 which is constituted by AND gate circuits 77-82, switching circuits 83-92 and inverters 93-97.

Operation of the electronic timepiece shown in Figs. 1A and 1 B will now be described.

Referring to Fig. 5, voltages vO, 1vo and 3vo are applied to terminals 13, 14; 12, 15; 10, 17 respectively. Further, a voltage 0 is applied to the terminals 11, 16. For ease of explanation it is assumed that the liquid crystal display device produces no display when the voltage is lower than |vO| and and produces a display when the voltage is higher than 12viol.

A pulse train shown by waveform A in Fig.

7 is applied to the terminal P0 of Fig. 5 so that the switching circuits 67, 69, 71, 73 and 68, 70, 72, 74 are opened and closed alternately. On the other hand pulses shown by waveform A are generated at the terminal Q of the flip-flop circuit 24 triggered by the pulses generated at the terminal P,.In consequence, the switching circuits 59, 61, 63, 65 and the switching circuits 60, 62, 64, 66 shown in Fig. 5 are opened and closed alternately to produce two voltages out of the four voltages 0, vO, 2vo, 3vo. Therefore pulse b1 of the waveform B in Fig. 7 is produced and the potential 0 is maintained at the terminal SO, while voltages 2vo and 0, 3vo and 0, v0 and 0 and v0 and 2vo are generated alternately at the terminals S" CO, C1 and C2 respectively.

On the other hand if pulse b2 is produced a voltage 3v, is generated at the terminal So and voltages v0 and 3vo, 0 and 3vo, 2vo and 3v, and 2vo and v0 are alternately generated at terminals S1, CO, C1 and C2 respectively.

The operation of the electronic timepiece will be explained assuming a time of 10 o'clock, 5 minutes and zero seconds (exactly 5 past 10). In this state, the counters 3 to 9 are counting, respectively, 0, 0, 5, 0, 0, 5, 5.

As pulses are cyclically generated from the terminal P1 of the timing pulse generating circuit 10 shown in Fig. 1A, the gate circuits 11, 14 for units of seconds are opened, so that data in the counters 3, 4 concerning seconds is delivered to gate circuits 17, 18.

Therefore, logic 0 is generated at terminals 2 -22 of the gate circuit 18 so that logic 1 and logic 0 are produced at terminals fi and h respectively while logic 1 is produced at the terminal x0 of the decoder 1 9.

Referring now to Fig. 4, since the outputs from the gate circuits 29, 39 are logic 1, the potential generated at the terminal So appears at the terminal e1. The potential generated at the terminal S, appears at other terminals e2-210, because the switching circuits 47, 49, 51, 53 are OFF. With regard to the decoder 20 shown in Fig. 6, the voltage generated at the terminal CO appears at the terminal k, because logic 1 appears at the terminal yO. In this state, since the terminal P3 of the timing pulse generating circuit 10 is logic 0 the terminal P3 is logic 1 so that the AND gate circuits 77-82 are open. Therefore, the switching circuit 83 is turned ON so that the voltage present at the terminal CO appears at terminal g1. The voltage present at the terminal C, appears at terminal k2-k6, 92-98- Therefore, a voltage differential |3viol between the voltages applied to the terminals e1 and g1 is applied to the liquid crystal material periodically so that the display corresponds to the electrode S shown in Fig. 2 which is turned ON. The voltage v0 is periodically applied between other electrodes so that the display corresponding to those other elec trodes is not produced.

Referring now to the terminal P2 of the timing pulse generating circuit 10, a pulse periodically generated at terminal P2 opens the gate circuits 12, 1 5 so that the output data "5', and "0" from the counters 5, 6 passes therethrough. In consequence logic 1 appears at terminal x5 of the decoder 1 9 and at terminal y0 of the decoder 20. Moreover logic 1 and logic 0 are maintained at terminals h and h respectively.

In consequence, the output from the OR gate circuit 41 shown in Fig. 4 is logic 1 so that the switching circuit 48 is turned ON to permit the voltage present at the terminal SO to appear at the terminal e6. The voltage present at the terminal S1 appears at the terminals e1-e5 and e7-e10.

As will be seen from Fig. 6 the voltage present at the terminal CO appears at the terminals g1, k1 while the voltage present at the terminal C1 appears at the terminals 9,-g, and k2-k6. Therefore the display corresponding to the electrode M shown in Fig. 2 and connected to terminal e6 and common electrodes opposed to the terminals g1, k1 produces a display.

Referring now to the terminal P3 of the timing pulse generating circuit 10, the pulses periodically derived from this terminal open the gate circuits 13, 1 6 to permit the output from the counters 7, 8 to pass therethrough.

In consequence, the voltage generated at the terminal So appears at the terminal e10 of the segment voltage supplying circuit 22. Meanwhile, the voltage present at the terminal CO appears at the terminal k6 of the common electrode supplying circuit 23, while the voltage present at the terminal C1 appears at the terminals k1-k5 thereof. When a pulse is generated at the terminal P3, the output from the AND gate circuits 77-82 shown in Fig. 6 is logic 0 so that the voltage present at the terminal C, appears at the terminals g1-g6.

Therefore, the display corresponding to the electrode H connected to the terminal e10 and the common electrode connected to the terminal k6 produces a display. Thus a display corresponding to the electrodes H, M, S are produced i.e. a display of 10 hours 5 minutes and 0 seconds.

Hereinafter a description will be made as to the display of a graduated time scale. Terminals m, to m6 of the common electrode 28d shown in Fig. 3 are connected in common to the terminal C3 shown in Fig. 5. As stated already, the voltages v0 and 2vo are generated at the terminal C2 at the half period of the pulse output from the terminal Q of the flipflop circuit 24, and voltages 2vo and v0 are formed in the next half period of output pulse from the terminal Q. On the other hand, at the terminal SO the voltage 0 and 3vo are formed in the earlier half and later half periods of the output pulse from the terminal Q.

Further, voltages 2vo, 0 and voltages vO, 3vo are formed at the terminal S1, in the earlier and later half periods of the output pulse. In consequence, a voltage 12viol is supplied between the segment electrode and the common electrode 28d irrespective of whether this segment electrode is selected to produce a display or not so that the display between the common electrode 28dand the segment electrodes is continuously produced to indicate time graduations of a graduated time scale.

Fig. 8 illustrates the time display of the electronic timepiece of Fig. 1. The numerals around the graduations may be provided by printing or by means of a liquid crystal display device.

Figs. 9 to 1 2 illustrate another embodiment of an electronic timepiece having a display device according to the present invention.

Fig. 9 shows a circuit interposed between the output conversion circuit 21 shown in Fig.

1 and the segment voltage supplying circuit 22. An inverter 98 inverts the output level derived from the output conversion circuit 21.

The gate circuits 99, 100 have AND functions, while the gate circuit 101 has an OR function.

Fig. 10 shows a modification of the common electrode voltage supplying circuit 23.

Gate circuits 102, 103 have AND functions.

A reference numeral 104 denotes a circuit constituted by switching circuits 83-88 and inverters 93-95 as shown in Fig. 6, while reference numeral 105 denotes a circuit constituted by switching circuits 89-92 and inverters 95-97. Reference numeral 106 denotes a common voltage supplying circuit for the common electrode 28dwhich is constituted by switching circuits 107-114 and inverters 115-118 as shown in Fig. 11.

Fig. 1 2 is a detailed circuit diagram of the voltage selecting circuit. This voltage selecting circuit is constituted by switching circuits 119-134 and inverters 135, 136.

In this embodiment the hours and minutes indications are produced in the same manner as previously described and a seconds indication is produced as follows.

The units of seconds is selected when a pulse is generated at a terminal P of the timing pulse generating circuit 10 shown in Fig. 1A. As this pulse is generated the gate circuit 99 (Fig. 9) is opened so that the inverted logical level of seconds data is delivered to the segment voltage supplying circuit 22 through the gate circuit 101. Therefore, a voltage corresponding to non-display, i.e. the voltage generated at the terminal S1, is applied to the terminal of the segment electrode which should produce a display according to the data. On the other hand the voltage corresponding to the display, i.e. the voltage generated at the terminal So, is applied to the terminals of the segment electrodes which should not produce a display according to the data.Meanwhile, the switching circuits 111, 11 3 shown in Fig. 11 are opened by the pulse from the terminal P1. Also the voltage present at the terminal CO appears at the output of the switching circuit connected to terminal y, at which the displaying output from the decoder 20 is derived, while the voltage present at the terminal C2 is generated at the outputs of other switching circuits.

Therefore, as far as the output to be displayed is concerned, the voltage present at the terminal CO is generated at the terminal mk, while, in the case of the outputs which should not be displayed, the voltage present at the terminal C3 appears at terminals mn (n = 1 to 6). In consequence, the voltage present at the terminal CO shown in Fig. 1 2 and the voltage present at the terminal S, are applied to the common electrode 28dfor display of seconds (Fig. 3) and to the segment electrode (Fig. 2), so that voltages 1v01 and 0 are periodically applied.Therefore, the graduated time scale to which these voltages are applied do not produce a display while other display sections receives voltages 3level and |vO| to to produce a display. Consequently, the graduations of the graduated time scale are so energised to indicate the elapse of seconds.

As described above a graduated time scale is formed as an electro-optical display device which represents the shape of the pointer or hands so that the necessity for adjustment of graduations is completely eliminated. In addition, since the variation of apparent position of the pointer or hands in relation to the graduations due to variation of angle or direction of observation is avoided, erroneous reading of the time indication does not take place.

Further, the present invention offers an additional advantage that the graduated time scale can be used for displaying seconds information.

Claims

1. A display device for an electronic timepiece comprising: an electro-optical time display device for producing a time indication in analog form and an electro-optical graduated time scale.

2. A display device as claimed in claim 1 including means for successively de-energising graduations of the time scale to indicate the passage of time.

3. A display device as claimed in claim 1 or 2 which optically produces a time display simulating that given by a timepiece with mechanical hours and minutes hands and in which a segment electrode arrangement consists of 60 radial electrodes equally spaced apart around a circle, and a common electrode arrangement arranged in three rings, the outermost ring constituting the said time scale.

4. A display device for an electronic timepiece substantially as herein described with reference to and as shown in the accompanying drawings.

5. An electronic timepiece having a display device as claimed in any preceding claim.

6. An electronic timepiece as claimed in claim 5 and substantially as herein described with reference to and as shown in the accompanying drawings.

7. A display device for electronic timepiece comprising: display means having a plurality of unit display sections and adapted to shift a predetermined state of discrimination successively from one to another unit display sections, in accordance with the lapse of time; and graduation display sections disposed to correspond to respective unit display sections and electrically connected to said unit display sections.

8. A display device for electronic timepiece comprising: display means having a plurality of unit display sections and adapted to shift a predetermined state of discrimination successively from one to another unit display section in accordance with the lapse of time; graduation display sections disposed to correspond to respective unit display sections and electrically connected to said unit display sections; and driving means for shifting a predetermined state of discrimination from one to another graduation display sections in accordance with the lapse of time.