GB2050728A - Phase Comparators - Google Patents

Abstract

Method of, and circuit for, measuring the value of a physical variable such as the degree of fullness of a storage tank represented by the phase shift between two signals applied to a phase comparator. The physical variable is interrogated for a relatively short period (T3-T1) in an overall longer period. The charge on a storage capacitor C1 is increased by connecting it to a source of high voltage (VH) for a period (T2-T1) and is decreased by connecting it to a source of low voltage (VL) for a period (T3-T2), the instant T2 being a variable time determined by the phase displacement between the two input signals 14 and V applied to the comparator. Thereafter the capacitor is disconnected from both sources and the mean value voltage (Vm) remaining is representative of the value of the physical parameter being measured. Vm=VH[(T2-T1)/(T3-T1)]+VL[(T3-T2)/(T3-T1) =VL+(VH-VL)[T2-T1)/(T3-T1)] <IMAGE>

Description

SPECIFICATION Method of, and Circuit for, Determining the Value of a Physical Variable The present invention relates to a method of, and circuit for, determining a value of a physical variable, for example an indication of the phase shift between two signals or the degree of fullness of a storage tank.

In a phase comparator such as that disclosed in British Patent Specification 1,477,584, the leading edge of a first binary signal waveform, which may comprise a reference waveform, is used to trigger a trapezoidal waveform generator which produces a rising edge slope or ramp. The leading edge of a second binary signal waveform, which is being compared with the first waveform, triggers a pulse generator which produces pulses of a shorter duration (20 (IS) than the duration (100 MS) of the rising edge of the trapezoidal waveform.At the occurrence of each pulse generator pulse, a sampling switch is operated for the duration of the pulse, which duration represents a sampling instant, and the portion of the ramp voltage occurring during the sampling instant is applied to a storage capacitor which has one electrode connected to an input of a buffer amplifier. As the buffer amplifier has a finite input impedance, and the storage capacitor has some leakage, the voltage on the capacitor decays between samples. Additionally the sampling switch has a parasitic series resistance and the trapezoidal waveform generator has finite output impedance; hence the storage capacitor will take a certain time to charge up. Consequently the voltage across the storage capacitor appears as a ripple which can be regarded as noise.

If the sampling instants are separated by relatively long spaces then because of the decay in the voltage across the storage capacitor due to leakage in the buffer amplifier, the value of the voltage will change so that in the event of connecting an analogue to digital converter to the output of the buffer amplifier, the digital value of the voltage will change and make this value unsuitable for use as an indication of the voltage across the capacitor during the sampling instant.

An object of the present invention is to provide a method of, and circuit for, determining the value of a physical variable the measurement of the value being maintained substantially constant between sampling instants.

According to one aspect of the present invention there is provided a method of determining the value of a physical variable, which value is to be represented as a mean value voltage across a capacitor, comprising interrogating the physical variable for a relatively short period in an overall longer period and during the interrogation period providing first and second signals representative of the beginning and end of the interrogation period and a third signal indicative of the physical variable, the third signal occurring at a variable time between the first and second signals, charging and discharging the capacitor for periods related to the differences in time between the first and third signals and the third and second signals, thereafter maintaining the charge on the capacitor substantially constant until the occurrence, of the next interrogation period.

The capacitor may be charged by connecting it to a source of relatively high voltage and is discharged by connecting it to a source of relatively low voltage, the charge being maintained constant by disconnecting the capacitor from both the relatively high voltage and relatively low voltage sources.

If desired the capacitor may share its charge with another capacitor which is connected to an output, and the another capacitor is disconnected from the first-mentioned capacitor when the latter is being charged/discharged during the interrogation period. Advantages of using the another capacitor as a buffer capacitor are that the voltage at the output is substantially free from ripples produced during the charge/discharge sequence and that the values of the capacitors can be reduced compared with when only one capacitor is used.

According to a second aspect of the present invention there is provided a method of determining the value of a physical variable, substantially as hereinbefore described with reference to the accompanying drawings.

The circuit may further comprise another capacitor connectable to the integrating circuit by further switching means controlled by the control means so that during the predetermined period the another capacitor is disconnected from the integrating circuit and is connected to the integrating circuit at other times.

United States Reissue Patent No. 28706 which corresponds to British Patent Specification No.

1,220,091 discloses a triple slope analog-to-digital converter. In one embodiment described with reference to Figures 1 and 2 of that patent, a start signal derived from the mains is used to operate switches which connect an RC integrating circuit to a source of voltage which is being measured and connect a clock source to a counter. A ramp voltage is produced across the capacitor of the integrating circuit as it changes up from zero. Once the counter overflows (that is after a fixed duration). the switches are rendered non-conductive. Further switches are closed and the capacitor of the integrating circuit is connected to a source of negative reference voltage and the capacitor begins to discharge rapidly towards an internally set level which is above zero. At the same time the counter has been connected to the clock source and has been counting.When-the internally set level has been reached, the circuit assumes a third dated in which the capacitor of the integrating circuit discharges slowly to zero which the counter continues to count but on a lower decade than before. The number shown on the counter is an indication of the voltage being measured. Because the capacitor has been discharged completely, the number on the counter will remain steady. Such a circuit cannot hold a mean value, above zero, because of the problems of leakage. Also because it does not have a state in which the input to the integrating capacitor is open circuited so that the mean value voltage can be held thereacross, such a circuit is unsuitable for use in interrogating the value of a changing physical variable at regular but relatively widely spaced apart time intervals.

The present invention will be explained and described, by way of example, with reference to the accompanying drawings, wherein: Figure 1 shows a number of waveform diagrams, A to D, which serve to explain the principle of the present invention, and Figure 2 shows schematically a circuit by which three states can be applied to a storage capacitor of an integrating circuit.

The present invention will be described in the practical application of a phase comparator and the physical variable being measured is the phase shift between two signals. In this application a binary signal 20, diagram C is compared with a binary reference signal 10, diagram A. The reference signal 10 is applied to a strobe pulse generating means (not shown) which produces at predetermined and relatively widely spaced apart intervals a strobe pulse 14 which is arranged to be 50% in front of the leading edge 12 and 50% behind. Each pulse 14 has a leading edge 1 6 and a trailing edge 1 8. The binary signal 20 has a leading edge 22 which occurs in the illustrated example during the period of the strobe pulse 14.The exact position of the edge 22 relative to the edge 12, provided it is during the period of the strobe pulse 14, i.e. during the period determined by the edges 1 6 and 1 8, is a measure of the phase shift. In the case of the edges 12 and 22 occurring contemporaneously, the two signal will be in phase.

A capacitor C1 of an RC integrating circuit 30 (Figure 2) is charged for a period corresponding to the time difference between the occurrence (T1,T2) of the leading edges 1 2 and 22 whereas the capacitor C1 is discharged during the time difference between the occurrence (T2) of the leading edge 22 and the occurrence (T3) of the trailing edge 8 of the associated reference pulse 14. As the phase difference between the binary signals 12, 20 is variable, then the periods (T2-T1) and (T3-T2) are variable within an overall fixed period (T3-T1), i.e. the period of the strobe pulse 1 4.

It should be noted that the circuit may be operated so that the capacitor C1 is discharged between T1 and T2 and charged between T2 and T3.

During the period between the trailing edge 1 8 of one strobe pulse 14 and the occurrence of the leading edge 16'of the next following strobe pulse 14, the voltage across the capacitor Cl is held at a mean value, Vm, which is substantially constant because the input to the integrating network is open circuited. This represents a first state of the integrating circuit 30. At the occurrence of each strobe pulse 14 a new mean value Vm is determined as will be explained with reference to waveform diagram ID.In the described embodiment, the leading edge 1 6 which occurs at T1 causes the integrating circuit 30 to be connected to a source of relatively high voltage VH SO that the capacitor C1 is charged for a period (T2-T1), which period represents the time difference between the occurrence of the leading edges 1 6 and 22. This is the second state of the integrating circuit 30. At time T2, the integrating circuit 30 is switched from a relatively high voltage source VH to a relatively low voltage source VL and the charge on the capacitor C1 falls. This continues until T3 when the connection of the source VL to the integrating circuit 30 is open-circuited so that a new mean value Vm prevails.The period (T2-T3) represents a third stage of the integrating circuit.

The value of Vm is determined as follows: Vm=V[(T2T1 )/(T3-Tl )]+VL[(T3-T2)/(T3- T1 )] =VL+(VH-VL)[(T2- )/(T3-T1)] Thus the mark/space ratio of the charge/discharge signal determines the new Vm.

Referring to Figure 2, the integrating circuit 30 is connected by switches S1. S2, shown schematically in broken lines, to voltage rails 32 and 34 at VH and VL, respectively. With both switches S1,S2 non-conductive, the voltage across the capacitor C1 is a value Vm. By rendering the switch S1 conductive for the period (T2--T1) and leaving the switch S2 non-conductive, the capacitor C1 is charged towards the rail 32 voltage by VH. Conversely by rendering the switch S2 conductive and switch S1 non-conductive, the capacitor C1 discharges towards V, via the resistor R for the period (T3-T2).If there has been'a change in the durations of the periods (T2-T1) and (T3-T2) the net charge will be different and consequently Vm will be different.

One practical embodiment of the switches S1 and S2 and control circuirtherefor is shown in Figure 2. The switches S1 and S2 comprise enhancement n-channel MOS field effect transistors 36, 38 which have their source-drain paths connected in series between the rails 32, 34. The value of VH is five volts whilst that of V; is zero volts. The gates of the transistors 36, 38 are connected to outputs of respective 2-input AND gates 40, 42. One input 44,46 of each AND gate 40, 42 receives the strobe pulses 14 whilst the second input 48 of the AND gate 40 receives the inverted form of the signal 20 and the second input 50 of the AND-gate 42 receives the signal 20.

In operation, during the period (T2-T1) when there is coincidence of the inputs 44, 48, the output of the AND gate is high and the transistor 36 is rendered conductive. Although not shown it is necessary to provide means to overdrive the gate of the transistor 36 in order to render it conductive, such means may comprise a bootstrapping arrangement or a connection to a voltage source of say twelve volts. During the period (T3-T2) when there is coincidence of the inputs 46, 50, the output of the AND gate 42 is high and the transistor 38 is rendered conductive.

Although the circuit of Figure 2 has been described with reference to AND gates and N-channel enhancement transistors, this is only illustrative because any suitable logic and switching elements may be used.

The integrating circuit 30 may be connected to a buffer amplifier 52 (shown in broken lines), such as an MOS amplifier, which does not provide a leakage path for the charge on the capacitor C1.

However although such an arrangement operates sa2isfactorily, the charge/discharge sequence during the period of the strobe pulse 14 will produce a ripple at the input to the amplifier 52. In a typical practical application where R=100 KQ and Ci=i MF,the RCtime constant lOOmS and the duration of the strobe pulse 14 is 6 ,uS, a 75 ,uV ripple may be produced on a Vm of 2.5 V assuming that the reference signal 10 and binary signal 20 are in phase. The undesirable effect of this ripple can be avoided by disconnecting the output of the tri-state driven integrator during the period of the stobe pulse 14.One way of doing this is shown in full lines in Figure 2 and comprises an enhancement nchannel MOS field effect transistor 54 whose source-drain path is connected between the input of the integrating circuit 30 and the input of the buffer amplifier 52'. A capacitor C2 is connected between the input of the amplifier 52' and the source V,. The gate of the transistor 54 receives the signal 14, that is the transistor 54 is non-conductive during each strobe pulse 14 but is conductive at all other times. Thus during the period of the strobe pulse 14, the capacitor C2 is disconnected from the integrating circuit 30 and the capacitor C1 is charged/discharged depending on the phase shift of the binary signal 20 relative to the reference signal 10 without producing a ripple at the input of the amplifier 52'.At the end of this period, the transistor 54 is rendered conductive and the capacitors C2 and C1 are re-connected so that any variation in voltage on the capacitor C1 will be charge shared with the capacitor C2. The value of the capacitor C2 need only be large enough to return data, that is Vrn, during the strobe period and to avoid ripple on the output of the integrating circuit 30 due to capacitive feedthrough of the strobe signal. Consequently it is possible to reduce the RC time constant without having a high output ripple voltage, typically the value of R is 50 KS2, C1 is 3000 pF, C2 is 1000 pF and the RC time constant is of the order of 200 MS.

The three-state integrating circuit is particularly useful in those practical applications where the overall system will not react to rapid changes in Vm. In the case of a phase comparator included in a phase locked loop, a relatively long reaction time will avoid hunting by the phase locked loop (PLL). In one embodiment of a phase comparator including the three state integrating circuit, the duration of the strobe pulse 14, waveform diagram 1 B, is 500 nS and the signal 20 is interrogated once every 100 yS (the reference signal 10 having a frequency of 10 KHz). Hence although a comparison takes places at regular intervals in time, these intervals are long compared to the period of the strobe pulse 14, the ratio being 5000 to 1. Accordingly this points to the necessity of Vm being maintained constant for a relatively long time.Further with VHVL equal to 5 V, the output voltage will vary by 5 V for a phase change of ts for .f,. 3600where tsis 500 nS, f, is 10 KHz and the rate of change in output voltage is 1000 V/cycle.

Although the circuit has been described in the environment of a phase comparator which may be incorporated in the PLL of a digital timing circuit, many other practical applications are possible where the charge on a capacitor is used to indicate a different physical variable, such as the fullness of a storage tank in which the dielectric constant of the substance being stored is different from that of air or air and vapour. Another requirement being that it is necessary to be able to provide signals corresponding to the instants T1, T2 and T3 so that the required charge/discharge cycle of the capacitor can be achieved. In the case of the storage tank T1 could be represented by a tank full signal, T3 by a tank empty signal and T2 by a level signal.

Claims (2)

Claims

1. A method of determining the value of a physical variable, which value is to be represented as a mean value voltage across a capacitor, comprising interrogating the physical variable for a relatively short period in an overall longer longer period and during the interrogation period providing first and second signals representative of the beginning and end of the interrogation period and a third signal indicative of the physical variable, the third signal occurring at a variable time between the first second signals, charging and discharging the capacitor for periods related to the differences in time between the first and third signals, thereafter maintaining the charge on the capacitor substantially constant until the occurrence of the next interrogation period.

2. A method as claimed in Claim 1, wherein the capacitor is charged by connecting it to a source of relatively high voltage and is discharged by connecting it to a source of relatively low voltage, and wherein the charge is maintained constant by disconnecting the capacitor from both the relatively high voltage and relatively low voltage sources.

2. A method as claimed in Claim 1, wherein the capacitor is charged by connecting it to a source of relatively high voltage and is discharged by connecting it to a source of relatively low voltage, and wherein the charge is maintained constant by disconnecting the capacitor from both the relatively high voltage and relatively low voltage sources.

3. A method as claimed in Claim 1 or 2, wherein the capacitor shares its charge with another capacitor which is connected to an output and the another capacitor is disconnected from the firstmentioned capacitor when the latter is being charged/discharged during the interrogation period.

4. A method of determining the value of a physical variable, substantially as hereinbefore described with reference to the accdmpanying drawings.

5. A circuit for determining a value of a physical variable, comprising an integrating circuit including a capacitor, first means providing a relatively high voltage, second means providing a relatively low voltabe, control means operable for a predetermined period during a longer, repetitive period to provide a first switching signal representative of a time period between the beginning of the predetermined period and the occurrence of a signal representative of the physical variable and a second switching signal representative of a time period between the occurrence of the physical variable signal and the end of the predetermined signal, switching means actuable by the first and second switching signals to connect the integrating circuit to the first means for a period determined by the first or the second switching signal and to the second means for a period determined by the second or the first switching signal and thereafter disconnecting both the first and second means from the integrating circuit, the mean voltage across the capacitor being indicative of the value of the physical variable.

6. A circuit as claimed in Claim 5, further comprising another capacitor connectable to the integrating circuit by further switching means controlled by the control means so that during the predetermined period the another capacitor is disconnected from the integrating circuit and is connected to the integrating circuit at other times.

7. A circuit for determining a value of a physical variable, substantially as hereinbefore described with reference to the accompanying drawings.

8. A phase locked loop circuit having a phase comparator including the circuit as claimed in Claim 5,6Or7.

New Claims or Amendments to Claims filed on 24th Jan 1980.

Superseded Claims 1,2.

New or Amended Claims:

1. A method of determining the value of a physical variable, which value is to be represented as a mean value voltage across a capacitor, comprising interrogating the physical variable for a relatively short period in an overall longer period and during the interrogation period providing first and second signals representative of the beginning and end of the interrogation period and a third signal indicative of the physical variable, the third signal occurring at a variable time between the first and second signals, charging and discharging the capacitor for period related to the differences in time between the first and third signals, thereafter maintaining the charge on the capacitor substantially constant until the occurrence of the next interrogation period.