GB1601907A

GB1601907A - Analogue-to-digital converter

Info

Publication number: GB1601907A
Application number: GB11184/78A
Authority: GB
Original assignee: Hitachi Ltd
Current assignee: Hitachi Ltd
Priority date: 1977-03-22
Filing date: 1978-03-21
Publication date: 1981-11-04
Also published as: FR2385264B1; FR2385264A1; DE2812375A1; DE2812375C2

Description

(54) ANALOG-TO-DIGITAL CONVERTER (71) We, HITACHI, LTD., a Corporation organized under the laws of Japan, of 5-1, 1-chome, Marunouchi, Chiyoda-ku, Tokyo, Japan, do hereby declare the invention for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement: This invention relates to an analog-to-digital Converter (hereinafter referred to as an ADC) which is important for an interface between the analog and the digital circuits, and more particularly to an integrating type ADC as used in the field of welfare equipments, home electric apparatus and instrumentation, etc.

In a prior art ADC, A-D conversion is done by discharging the charge corresponding to an input signal by a discharging circuit after it is charged in a storage means, and counting the number of clock pulses by a counter during the discharging time T which is equal to a period that a level of the charge reaches a constant detection level VT. An example is described in an article entitled "An All-MOS Analog to Digital Converter Using a Constant Slope Approach". IEEE Journal of Solid State Circuits, June 1976 by G. Smarandoin et al.

However, in such a circuit construction of the prior art, if an input signal voltage is less than the detection level VTH, the discharge time T cannot be detected, and thus A-D conversion is impossible. In another word, in the prior art circuit, the A-D conversion is possible in a limited range of the input signal.

An object of this invention is to extend the range of the input signal by which the A-D conversion is attained in an ADC wherein charges corresponding to an analog input signal is stored in a storage means and then discharged in the discharging circuit to count the discharge time by a counter until a voltage in the storage means reaches a certain detection level.

Another object of this invention is to provide a circuit construction suited to the formation of the ADC in an IC.

According to the present invention there is provided an analog-to-digital converter comprising a storage means connected to an input terminal to store a signal corresponding to the analog input signal, a discharging means connected to the output terminal of said storage means for discharging said stored signal, a counter means for counting clock pulses during discharge of the storage means until the time at which the voltage at the output terminal of the storage means reaches a certain non-zero detection level during discharging; and a bias voltage supply means connected to said storage means and operable to apply a predetermined voltage greater than said detection level voltage to said storage means to ensure that the voltage at said output terminal of said storage means is above said detection level at the commencement of discharge.

A further aspect of the invention provides an analog-to-digital converter comprising a storage means for storing an analog input signal voltage applied at an input terminal, a discharging means connected to the output terminal of said storage means for discharging said analog input signal voltage stored in said storage means, a level detection means for detecting the time at which the voltage at the output terminal of said storage means reaches a certain non-zero detection level voltage, a counter for counting the number of clock pulses from the beginning of discharging to the detection time of said level detection means; and a bias voltage supply means connected to said storage means and operable to apply a predetermined voltage greater than said detection level voltage to said storage means to ensure that the voltage at said output terminal of said storage means is above said detection level at the commencement of discharge.

A preferred aspect of the invention provides an analog-to-digital converter comprising an input terminal to which an analog input signal is applied, a capacitive element connected to said input terminal through a first switch and storing said analog input signal voltage, a constant current discharging circuit connected to the output terminal of said capacitive element and having a second switch, a level detection means connected to the output terminal of said capacitive element and detecting the time at which said voltage at the output terminal of said capacitive element becomes equal to a certain non-zero detection level, a counter means for counting the number of clock pulses from the beginning of the operation of said constant current discharging circuit to said time; and a bias voltage supply means connected in series with said capacitive element and operable to apply a predetermined voltage greater than said detection level to said capacitive element to ensure that the voltage at said output terminal of said capacitive element is above said detection level voltage at the commencement of discharge.

Although the object of this invention can be attained by connecting a bias voltage to the storage means at the discharge time only when the input signal voltage is smaller than the detection level, the bias voltage may be always connected to the storage means at the discharge time regardless of whether the input signal voltage is smaller than the detection level or not.

Preferably, the circuit construction is such that not only the bias voltage is connected to the storage means at the discharge time but also a short-circuiting circuit is provided in parallel with a capacitive element of the storage means so that at the end of the A-D conversion the both terminals of the capacitive element is short-circuited to perform switching from the bias to the earth voltage. Therefore, regardless of the magnitude of the bias voltage, no negative (or positive) voltage is generated in any part of the circuit, thereby preventing the destruction of IC.

The present invention will be more readily apparent from the following detailed exemplary description taken in conjunction with the accompanying drawings, in which: Figure I is a drawing showing the schematic circuit construction of the prior art ADC of exponential slope type.

Figure 2 is a waveform diagram for explanation of the operation of the circuit construction of Figure 1.

Figure 3 is a drawing showing the schematic circuit construction of an ADC of exponential slope type according to one embodiment of this invention.

Figures 4a and 4b are waveform diagrams for explanation of the operation of the circuit construction of Figure 3.

Figures 5a and 5b are concrete circuit diagrams showing a bias voltage supply means in the circuit construction of Figure 3.

Figure 6 is a drawing showing the schematic circuit construction according to another embodiment of this invention.

Figure 7 is a waveform diagram for explanation of the operation of the circuit diagram of Figure 6.

Figures 8a and 8b are drawings showing the essential portion of a circuit construction improving the embodiment of Figure 6.

Figure 9 is a drawing showing the schematic circuit construction of an ADC of constant slope type according to another embodiment of this invention.

Figure 10 is a drawing showing the concrete circuit construction of a constant current discharge circuit in the circuit construction of Figure 9.

Figure 11 is a waveform diagram for explanation of the operation of the circuit construction of Figure 9.

Figure 12 is a drawing showing the essential portion of a circuit construction improving the embodiment of Figure 9.

Figure 13 is a waveform diagram for explanation of the operation of the circuit construction of Figure 12.

Figure 14 is a drawing showing the schematic circuit construction of an example of modifying the connection point of the bias voltage supply means used in this invention.

Prior to a detailed description of this invention with reference to the drawings, an explanation of an example of the prior art ADC of exponential slope type will be made with Figure 1. The literature already indicated demonstrating an ADC of constant slope type should be referred to also.

In Figure 1, (1) denotes an input terminal to which an input signal is supplied, and (2) denotes a storage means comprising a switch (21) (SW1) and a capacitive element (22). (3) denotes a cischarging circuit comprising a resistance element (31) and a switch (32) (SW2).

(4) is a level detecting circuit and (5) is a counter whose terminals (51), (52) and (54) receive clock pulses to be counted, set and clear pulses respectively.

Figure 2 is a waveform diagram for explanation of the operation of the circuit construction of Figure 1. When an input signal voltage VI is supplied to the input terminal (1) and the switch (21) (SW1) is turned on at a time shown in Figure 2(b), the output terminal voltage V or the voltage at one terminal of the capacitive element (22) of the storage means (2) becomes equal to the input signal voltage VI. That is, the analog input signal voltage Vl is stored in the storage means. After a time to, when the switch (21) (SW1) is turned off and the switch (32) (SW2) of the discharging circuit (3) is turned on as shown in Figure 2(c), an electric charge is discharged with an exponential slope through the resistive element (31), as shown in Figure 2(a).When the voltage V drops to a constant detection level TTH, the level detection circuit (4) is turned off, as shown in Figure 2(d), giving a reset pulse for the counter (5). Since the set pulse for the counter (5) was applied at the terminal (52) at the discharge starting time or when the switch (32) (SW2) was turned on, the counter (5) counts the number of clock pulses supplied to the terminal (51) during the period Tr as shown in Figure 2(e). After the end of counting, the count value is sent out to a processing circuit as shown by an arrow (53).

Following equations hold for the count value Nl , the frequency f of clock pulses, the capacitance C of the capacitive element (22), and the resistance R of the resistance element.

Vl = VTH exp(T1/CR) (1) N10 = fTl = f.CR.n (VI/VTH) (2) As apparent from these equations, if Vl S VTH, the value of N10 becomes zero. That is, in the circuit construction shown in Figure 1, when the input signal voltage Vl is less than the detection level VTH, the output of counter (5) is zero, which mean that the A-D conversion is not possible. It is seen therefore that the A-D conversion of the prior art circuit is limited.

This is also the same with an ADC of constant slope type using a constant current circuit in the discharging circuit. Putting the count value N lc, the period Tloc and the current value of the constant current circuit Io, we have the following equations corresponding to eqs. (1) and (2).

VI = Io TIC + VTH (3) C Nix = I (V1 - VTH) (4) Io It is clear that unless Vl > VTH the count value Nloc is not obtained.

Figure 3 shows the first embodiment of this invention, in which this invention is applied to an ADC of exponential slope type. In the figure, the same reference numeral designates the same element. (6) denotes a bias voltage supply means having a function of connecting a bias voltage Vn to the capacitive element (22). (61) and (62) are switches (SW3) and (SW4) respectively. (63) is a bias voltage source. A parallel circuit comprising the switch (61) or (SW3), the switch (62) or (SW4) and the bias voltage source (63) is connected in series with the capacitive element (22).

Explanation will be made of the operation of the embodiment with reference to Figures 4a and 4b, showing the waveforms at the output of the storage means (2) of Figure 3. Figure 4a shows the waveform when the input signal voltage Vl is less than the detection level voltage VTH while Figure 4b shows the waveform when Vl is larger than VTH. In Figure 4a, under the condition of switch (21) (SW1) on; switch 32 (SW2) off; switch (61) (SW3) on; and switch (62) (SW4) off, an input signal voltage Vl less then VTH is applied at the input terminal (1).Corresponding charge is stored in the capacitive element (22) and the voltage V at the output of the storage means becomes Vl. Next, when the switches (21) (SW1) and (32) (SW2) are turned off and on respectively and at the same time the switches (61) (SW3) and (62) (SW4) are turned off and on respectively to connect a bias voltage Vn to the capacitive element (22) to cause discharging, the voltage V at the output of the storage means (2) is shifted to (Vl + Vn). In this case, the bias voltage Vn should of course satisfy the condition VI + Vn > VTH. The period T1 in which the voltage V at the output of the storage means (2) drops to VTH is counted by a counter (5) to obtain a count value N.Here, the following equations corresponding to eqs. (1) and (2) hold.

Vl = VTH exp(T1/CR) - Vn (5) N = FCR4n (Vl + VB ) (6) Thus, even if the input signal voltage Vl is smaller than Vm, the A-D conversion is effected only by adding a bias voltage source with a suitable value and an additional switch. Figure 4b shows the waveform when the condition of switch (61) (SW3) on; switch (62) (SW4) off is kept at the discharging time since the input signal voltage Vl is larger than VTH. It is noted that the waveform of Figure 4b is entirely the same as that of Figure 2a.

Although in the above description the bias voltage VB was connected to the capacitive element (22) prior to the discharging and the voltage V at the output of the storage means (2) was made (Vl + VB)r a bias voltage Vn with Vn > VTH may be connected to the capacitive element (22) before the discharging regardless of whether Vl is less than VTH or not. By this method, the circuit can be easily constructed, because no circuit for discriminating whether Vl is larger or smaller than VTH is necessary.

Next, explanation will be made of effective elements for constructing the embodiment of Figure 3 in an IC. As the switches (SW1) to (SW4), single channel (n or p channel) MOSFET or C-MOS analog switches may be used. The level detection circuit (4) can be formed by MOSFET, since it works satisfactorily by multistage connection of conventional logic gates such as inverters.

A concrete example of Vn, VTH, and Vl will be briefly described here. When the level detection circuit (4) is constituted by multistage connections of inverters, VTH may be set at 0.5 V to 1.5 V. If VTH is set around 1.3 V and the bias voltage Vn is set around 2.0 V, all the input signal voltage Vl above 0 V can be A-D converted.

Figures Sa and Sb show concrete examples of the bias voltage supply means (6) in Figure 3. In Figure Sa, the switches (61) (SW3) and (62) (SW4) of Figure 3 are constituted by MOSFET's, with (64) and (65) being control terminals for them. Figure Sb shows a bias voltage supply means (6') realized by a conventional inverter of MOSFET's, with (66) and (67) being VnD supply and control terminals respectively. The voltage difference between the low and high levels of the inverter corresponds to the bias voltage Vn. Namely, the inverter is at the low level at the charging time while at the high level at the discharging time. Usually, the low level is grounded. Figure 6 shows a modification of the embodiment of Figure 3.In this embodiment, a reference voltage terminal (7) is connected in parallel with the input terminal (1) to which the input signal voltage Vl is supplied, and furthermore switches (23) (SW5) and (24) (SW6) are added to the switch (21) (SW1). Influence of irregularity and age variation of the circuit elements are thus eliminated by the introduction of the reference voltage VR as one of the input voltages of ADC. In Figure 6, the level detection circuit (4) is drawn by a multiple connection of inverters (4). The inverters (4) may be those, as shown in Figure Sb.

Explanation of the operation of the circuit construction of Figure 6 will be made next with reference to Figure 7. Figure 7(a) shows the output voltage V of the storage means (2).

Figures 7(b). (c) (d), (e) show ON-OFF operations of the switches (SW6), (SW1), (SW5) and (SW2) respectively. Figure 7(f) shows the output of the level detection means (4) while Figure 7(g) shows the operation timing of the counter (S). Although the application time of bias voltage Va is not shown, VB is applied simultaneously with the ON of the switch (32) (SW2) while its application is stopped simultaneously with the ON of the switch (24) (SW6).

Initially. when the switch 24 (SW6) is turned on and the zero voltage is A-D converted, the counter (S) gives a count value No. Next, when the switch (21) (SW1) is turned on and the input voltage Vl is A-D converted, the counter (S) gives a count value Nl. Lastly, when the switch (23) (SWS) is turned on and the reference voltage VR is A-D converted, the counter (S) gives a count value NR In this case, the following equations hold.

0 = VTH exp ( fCR) - VB (7) V1 = VTH exp(Nr - N1 (8) exp() - VB VR = VTH exp( NR - Vn (9) fCR From eqs. (7), (8) and (9), we have

Thus, VI is free from the influence of C, R, and VTH.

However, since the bias voltage Vg is obtained from the high level of the inverter, variation of Vg and age variation become serious. Figure 8 shows the essential portion of a circuit construction solving these problems. Figure 8a shows a construction which counts a count value Ng corresponding to the bias voltage VB. In comparison with Figure 5, an inverter (8) with the same characteristic as that of the inverter (6') for the bias voltage supply means, an input terminal (9) to which the high level voltage VB' is applied, and a switch (25) (SW7) for supplying this voltage to the storage means (2) are added.In this circuit, assuming the count value for Vgl with V111 = VB as NB, we have

= f.CR fCR = log2 e (Ns - No) (13) Thus, the influence of VB is eliminated. If the variaton of VB and VB' can not be neglected, the embodiment as shown in Figure 8b may be useful, in which two kinds of reference voltage are used. Let reference voltage VR and VR' be applied to the inputs (7) and (7') respectively and count values NR and NR' be obtained by the counter (5). Assuming the count values for the input voltage VI and the zero voltage as N1 and No respectively, we obtain

where 1'' may be obtained from

In Figure 8b, the switch 23' (SW5') serves to select the reference voltage VRr.

The above description referring to Figures 3 to 8 has been made on the embodiments of ADC of exponential slope type. Next, explanation will be made of an embodiment of ADC of constant slope type with reference to Figure 9. A difference from the exponential slope type is that the discharge circuit (3) is replaced by a constant current discharge circuit (3').

Switches (21) (SW1), (23) (SW5), and (24) (SW6) are shown by MOSFET. Although various kinds of constant current discharge circuits (3') suitable for IC are publicly known, a construction as shown in Figure 10 may be useful. In Figure 10, (33) denotes a VDD supply terminal, (34) a control terminal for applying a control pulse to the switch (32) (SW2). for the ON-OFF operation of the constant current circuit, (35) a constant current output circuit, and (36) a bias circuit for the output circuit. The constant current circuit (35) comprises two enhancement type MOSFET's (351) and (352) connected in series between the output terminal and the earth.The bias circuit (36) serves to operate the enhancement type MOSFET's (351) and (352) in the saturation region, and is formed by a first voltage divider circuit comprising a depletion type MOSFET (361) and an enhancement type MOSFET (362) and a second voltage divider circuit comprising a depletion type MOSFET (363) and an enhancement type MOSFET (364). The constant voltage of the first voltage divider circuit is applied to the gate FET (352), while that of the second voltage divider circuit is applied to the gate (351) of FET (351). This constant current circuit utilizes basically the fact that the drain currents in the saturation region of the enhancement type MOSFET's (351) and (352) are substantially constant independently of the drain voltage.

Furthermore, the fact that the drain currents of the MOSFET's (351) and (352) varies in opposite direction to that of the voltage variation at the connection point of these MOSFET's to stabilize the drain voltage of FET (352) always at a constant value, is also appreciated.

Figure 11 shows the waveform diagrams of the circuit construction of Figure 9. Figure ll(a) shows the voltage V at the output of the storage means (2); Figure 11(b) shows the ON states of (SW1), (SW5), and (SW6); Figures 11(c), (d) and (e) show the ON and OFF states of (SW2), (SW3) and (SW4) respectively; Figure 11(f) shows the output of the level detection circuit (4): and Figure 11(g) shows the counting period of the counter (5).

Although the times of ON-OFF of switches (SW1) to (SW6) are shown to coincide with each other, the switch (61) (SW3) is turned off a little later than the OFF time of switches (21) (SW1) (23) (SW5) and (24) (SW6). The switch (62) (SW4) is then turned on at a later time, and the switch (32) (SW2) is turned on at a further delayed time. Moreover, it is necessary to provide a certain time gap between the OFF time of switch (62) (SW4) and the ON time of switch (61) (SW3). The control of the switch group is done by a signal from a control circuit (not shown).

For the count values NRC, N1c, and Noc for the reference voltage VR, the input signal voltage Vl and the zero voltage VO respectively, the following equation holds.

V1 = VO + (VR - VO) N1c - Noc NRC - Noc (16) It is seen that the capacitance C of the capacitive element (22) and the bias voltage Vn do not appear in the above equation.

However, a problem occurs when the operation of Figure 11 is effected for the circuit of Figure 9. As apparent from Figure 11(a), since Vg > VTH is selected, the voltage V at the output terminal of the storage means (2) becomes minus, or - (V11 - VTH), when the switch (62) (SW4) is turned off. Assume that the circuit is formed by N-channel MOS-IC. Then the p-n junction between the drain regions of the OFF state switches (21) (SW1), (23) (SW5), and (24) (SW6) and the substrate has a forward bias, when the output voltage V is minus.

This causes an excessive current, leading to destruction of IC. In order to avoid this, after the switch (62) (SW4) is turned off, the switch (61) (SW3) and the switch (24) (SW6) may be simultaneously turned on to put the both terminals of the capacitive element (22) at the zero potential. However, since it is difficult to obtain such a coincidence, the possibility of IC breakdown is still high.

Figure 12 shows the essential portion of an embodiment which solves this problem. In this figure, a switch (28) (SW8) is added in parallel with the capacitive element (22). Moreover, the construction of the constant current discharge circuit (3') is different from that of Figure 10. The gate voltage of an enhancement type FET (352) is maintained at constant by a bias circuit (36'). Another enhancement type FET (351) has an ON-OFF switch function for the constant discharge circuit (3'), (34') denotes a terminal for supplying the control pulse. It is needless to say that both enhancement type FET's (351)and352) may be operated in the saturation range during the ON period. Next, the operation of the switch (28) (SW8) of this embodiment will be described.Just as the terminal voltage of the capacitive element (22) of the storage means (2) drops to the detection level voltage VTH and the counter (5) finishes counting the switch (28) (SW8) is turned on to recover the terminal voltage to VB.

Thereafter, if the switch (62) (SW4) and the switch (61) (SW3) are turned off and on respectively, the terminal voltage of the capacitive element (22) does not drop below 0 V.

This operation can be clarified with reference to Figure 13. Figure 13(a) shows the output voltage of the storage means (2), or the terminal voltage of the capacitive element (22); Figure 13(b), (c), (d), (e) and (f) show the ON and OFF states of the switches (SW1), (SW2), (SW3), (SW4) and (SW8) respectively.

Since through the use of this embodiment the terminal voltage of the capacitive element (22) does not fall below zero, no breakdown of IC occurs even if the circuit of this invention is formed by N-channel MOSFET's. The circumstance is the same with the case when the circuit is formed by P-channel MOSFET's, only if the inversion of polarity is taken into account. Although the embodiment was explained for the case of constant slope type, it is needless to say that the principle can be applied to the exponential slope type as shown in Figure 3.

In the circuit elements described above, the level detection circuit (4) is suitably built in an IC by a multiconnection of inverters, but analog comparators and operational amplifiers are also suitable. Furthermore, as the connection position of the bias voltage supply means (6), such a position as shown in Figure 14 is also allowed, as is evident from its function.

Although not described in the above explanation, according to this invention, it is possible to control the operation of the bias voltage supply means depending on the characters of plural analog input signals to be A-D converted in such a way that the bias voltage supply means operates always for certain kinds of analog input signal while it does not operate for other kinds of analog input signal.

WHAT WE CLAIM IS: 1. An analog-to-digital converter comprising a storage means connected to an input terminal to store a signal corresponding to the analog input signal, a discharging means connected to the output terminal of said storage means for discharging said stored signal, a counter means for counting clock pulses during discharge of the storage means until the time at which the voltage at the output terminal of the storage means reaches a certain non-zero detection level during discharging; and a bias voltage supply means connected to said storage means and operable to apply a predetermined voltage greater than said detection level voltage to said storage means to ensure that the voltage at said output terminal of said storage means is above said detection level at the commencement of discharge.

2. An analog-to-digital converter according to Claim 1; wherein said storage means comprises a first switch one end of which is connected to said input terminal and a capacitive element one end of which is connected to the other end of said first switch and said discharge means; said bias voltage supply means being connected to the other end of said capacitive element.

3. An analog-to-digital converter according to Claim 1, wherein said discharging means comprises a series connection of a resistance element and a second switch.

4. An analog-to-digital converter according to Claim 2, wherein said bias voltage supply

**WARNING** end of DESC field may overlap start of CLMS **.

Claims

**WARNING** start of CLMS field may overlap end of DESC **. It is seen that the capacitance C of the capacitive element (22) and the bias voltage Vn do not appear in the above equation. However, a problem occurs when the operation of Figure 11 is effected for the circuit of Figure 9. As apparent from Figure 11(a), since Vg > VTH is selected, the voltage V at the output terminal of the storage means (2) becomes minus, or - (V11 - VTH), when the switch (62) (SW4) is turned off. Assume that the circuit is formed by N-channel MOS-IC. Then the p-n junction between the drain regions of the OFF state switches (21) (SW1), (23) (SW5), and (24) (SW6) and the substrate has a forward bias, when the output voltage V is minus. This causes an excessive current, leading to destruction of IC. In order to avoid this, after the switch (62) (SW4) is turned off, the switch (61) (SW3) and the switch (24) (SW6) may be simultaneously turned on to put the both terminals of the capacitive element (22) at the zero potential. However, since it is difficult to obtain such a coincidence, the possibility of IC breakdown is still high. Figure 12 shows the essential portion of an embodiment which solves this problem. In this figure, a switch (28) (SW8) is added in parallel with the capacitive element (22). Moreover, the construction of the constant current discharge circuit (3') is different from that of Figure 10. The gate voltage of an enhancement type FET (352) is maintained at constant by a bias circuit (36'). Another enhancement type FET (351) has an ON-OFF switch function for the constant discharge circuit (3'), (34') denotes a terminal for supplying the control pulse. It is needless to say that both enhancement type FET's (351)and352) may be operated in the saturation range during the ON period. Next, the operation of the switch (28) (SW8) of this embodiment will be described.Just as the terminal voltage of the capacitive element (22) of the storage means (2) drops to the detection level voltage VTH and the counter (5) finishes counting the switch (28) (SW8) is turned on to recover the terminal voltage to VB. Thereafter, if the switch (62) (SW4) and the switch (61) (SW3) are turned off and on respectively, the terminal voltage of the capacitive element (22) does not drop below 0 V. This operation can be clarified with reference to Figure 13. Figure 13(a) shows the output voltage of the storage means (2), or the terminal voltage of the capacitive element (22); Figure 13(b), (c), (d), (e) and (f) show the ON and OFF states of the switches (SW1), (SW2), (SW3), (SW4) and (SW8) respectively. Since through the use of this embodiment the terminal voltage of the capacitive element (22) does not fall below zero, no breakdown of IC occurs even if the circuit of this invention is formed by N-channel MOSFET's. The circumstance is the same with the case when the circuit is formed by P-channel MOSFET's, only if the inversion of polarity is taken into account. Although the embodiment was explained for the case of constant slope type, it is needless to say that the principle can be applied to the exponential slope type as shown in Figure 3. In the circuit elements described above, the level detection circuit (4) is suitably built in an IC by a multiconnection of inverters, but analog comparators and operational amplifiers are also suitable. Furthermore, as the connection position of the bias voltage supply means (6), such a position as shown in Figure 14 is also allowed, as is evident from its function. Although not described in the above explanation, according to this invention, it is possible to control the operation of the bias voltage supply means depending on the characters of plural analog input signals to be A-D converted in such a way that the bias voltage supply means operates always for certain kinds of analog input signal while it does not operate for other kinds of analog input signal. WHAT WE CLAIM IS:

1. An analog-to-digital converter comprising a storage means connected to an input terminal to store a signal corresponding to the analog input signal, a discharging means connected to the output terminal of said storage means for discharging said stored signal, a counter means for counting clock pulses during discharge of the storage means until the time at which the voltage at the output terminal of the storage means reaches a certain non-zero detection level during discharging; and a bias voltage supply means connected to said storage means and operable to apply a predetermined voltage greater than said detection level voltage to said storage means to ensure that the voltage at said output terminal of said storage means is above said detection level at the commencement of discharge.

means comprises an inverter.

5. An analog-to-digital converter according to Claim 2, wherein said bias voltage supply means comprises a parallel circuit of a third switch and a series connection of a fourth switch and a bias voltage source.

6. An analog-to-digital converter comprising a storage means for storing an analog input signal voltage applied at an input terminal, a discharging means connected to the output terminal of said storage means for discharging said analog input signal voltage stored in said storage means, a level detection means for detecting the time at which the voltage at the output terminal of said storage means reaches a certain non-zero detection level voltage, a counter for counting the number of clock pulses from the beginning of discharging to the detection time of said level detection means; and a bias voltage supply means connected to said storage means and operable to apply a predetermined voltage greater than said detection level voltage to said storage means to ensure that the voltage at said output terminal of said storage means is above said detection level at the commencement of discharge.

7. An analog-to-digital converter according to Claim 6, wherein said level detection means comprises a multistage connection of inverters.

8. An analog-to-digital converter according to Claim 7, wherein said storage means comprises a first switch one end of which is connected to said input terminal and a capacitive element the one end of which is connected to the other end of said first switch and the other end of which is connected to the earth; said discharging means comprising a series circuit of a discharging circuit and a second switch inserted between the connection point of said first switch and said capacitive element and the earth.

9. An analog-to-digital converter according to Claim 8, wherein said bias voltage supply means comprises a parallel circuit of a third switch and a series connection of a fourth switch and a voltage source, and connected in series with said capacitive element.

10. An analog-to-digital converter according to Claim 9, wherein an eighth switch is connected in parallel with said capacitive element.

11. An analog-to-digital converter according to Claim 10, wherein said first, second, fourth, and eighth switches comprise MOSFET's.

12. An analog-to-digital converter according to Claim 7, wherein said inverters comprise MOSFET's.

13. An analog-to-digital converter comprising an input terminal to which an analog input signal is applied, a capacitive element connected to said input terminal through a first switch and storing said analog input signal voltage, a constant current discharging circuit connected to the output terminal of said capacitive element and having a second switch, a level detection means connected to the output terminal of said capacitive element and detecting the time at which said voltage at the output terminal of said capacitive element becomes equal to a certain non-zero detection level, a counter means for counting the number of clock pulses from the beginning of the operation of said constant current discharging circuit to said time; and a bias voltage supply means connected in series with said capacitive element and operable to apply a predetermined voltage greater than said detection level to said capacitive element to ensure that the voltage at said output terminal of said capacitive element is above said detection level voltage at the commencement of discharge.

14. An analog-to-digital converter according to Claim 13, comprising an eighth switch connected in parallel with said capacitive element.

15. An analog-to-digital converter according to Claim 13, wherein said constant current discharging circuit comprises a series connection of two enhancement type MOSFET operating in the saturation region.

16. An analog-to-digital converter according to Claim 15, wherein one of said enhancement type MOSFET's is said second switch.

17. An analog-to-digital converter substantially as hereinbefore described with refer ence to and as shown by Figures 3 to 14 of the accompanying drawings.