GB2045580A - Compensated input circuit for use with bipolar return to zero line signals - Google Patents

Abstract

An input circuit for use with bipolar RT2 signals is transformer coupled for d.c. isolation and line impedance matching. Part of the input signal BL1 is tapped off, rectified and smoothed to provide a d.c. voltage which follows the amplitude changes of the input line signal. The d.c. voltage is used to vary the threshold of a level detector circuit which comprises a long tail triplet (TR1, TR2, TR3). Transistors TR1 and TR2 provide the signal output conditions whereas TR3 provides the variable threshold. The signals amplified by TR1 and TR2 are further amplified by transistors TR4 and TR5 which provide, at their collectors, the respective positive and negative mark binary output signals. <IMAGE>

Description

SPECIFICATION Compensated input circuit for use with bipolar return to zero line signals The present invention relates to a circuit which is suitable for use in receiving line signals using bipolar return to zero coding such as HDB3.

According to the invention there is provided an input circuit for use in receiving line signals of the bipolar return to zero type, the circuit including means for tapping off, rectifying and smoothing part of the received input signal to generate a d.c. voltage which follows the amplitude changes of the input signal which d.c. voltage is used to vary the threshold of a level detector circuit associated with a long-tail pair amplifier handling the input signals.

The invention will be more readily understood from the following description which should be read in conjunction with the accompanying drawing.

The operation of the circuit according to one embodiment of the invention is as follows (refer to circuit diagram Fig. 1). The bipolar line BLI signal enters the circuit via a transformer T1 which matches the input circuit to the line impedance and provides d.c. isolation.

Part of the signal is tapped off, rectified by diodes D1 and D2 and smoothed by C4 to provide a d.c. voltage which follows the amplitude changes of the input line signal. The d.c. signal on C4 is used to vary the threshold of a level detector circuit formed by transistors TRi, TR2, T3 and associated components.

Thus the detection threshold follows the amplitude of the input line signal.

The signals amplified by TR1 and TR2 are further amplified by TR4 and TR5. The output from the collectors of TR4 and TR4 consist of positive and negative mark binary signals.

These can be readily used by normal TTL logic circuits. TR1, TR2 and TR3 and PNP transistors. These have a low transistion frequency so are operated in a non saturating mode to obtain the necessary speed for operating the circuit at 2Mb/s. TR1 and TR2 are prevented from saturating by the clamping of their collectors by the base emitter diodes of TR4 and TR5. The latter transistors are NPN and having a high transition frequency which allows them to be used in a saturating mode.

Capacitors C2 and C3 provide frequency compensation necessary if the circuit is being driven from a long length coaxial cable.

The transistors TR1-TR5 can be replaced by integrated circuits which cut down the number of components required for this circuit. The circuit is ideally suited for implementation in intregrated form when costs become more attractive.

The circuit was designed orginally to work at 2048 kbit/sec with a standard n883 coded input signal. With minor adjustments to the compensation capacitors the circuit should operate up to 8 Mbit/sec.

At higher frequencies the transistors TR4 and TR5 would have to be operated in the non saturating mode.

1. An input circuit for use in receiving line signals of the bipolar return to zero type, the circuit including means for tapping off, rectifying and smoothing part of the received input signal to generate a d.c. voltage which follows the amplitude changes of the input signal which d.c. voltage is used to vary the threshold of a level detector circuit associated with a line signal amplifier.

2. An input circuit according to claim 1 in which the line signal amplifier comprises a long-tail triplet and the d.c. voltage is used to control the current in one of the transistors of the triplet.

3. An input circuit substantially as shown and described with reference to the accompanying drawing.

**WARNING** end of DESC field may overlap start of CLMS **.

Claims (3)

**WARNING** start of CLMS field may overlap end of DESC **. SPECIFICATION Compensated input circuit for use with bipolar return to zero line signals The present invention relates to a circuit which is suitable for use in receiving line signals using bipolar return to zero coding such as HDB3. According to the invention there is provided an input circuit for use in receiving line signals of the bipolar return to zero type, the circuit including means for tapping off, rectifying and smoothing part of the received input signal to generate a d.c. voltage which follows the amplitude changes of the input signal which d.c. voltage is used to vary the threshold of a level detector circuit associated with a long-tail pair amplifier handling the input signals. The invention will be more readily understood from the following description which should be read in conjunction with the accompanying drawing. The operation of the circuit according to one embodiment of the invention is as follows (refer to circuit diagram Fig. 1). The bipolar line BLI signal enters the circuit via a transformer T1 which matches the input circuit to the line impedance and provides d.c. isolation. Part of the signal is tapped off, rectified by diodes D1 and D2 and smoothed by C4 to provide a d.c. voltage which follows the amplitude changes of the input line signal. The d.c. signal on C4 is used to vary the threshold of a level detector circuit formed by transistors TRi, TR2, T3 and associated components. Thus the detection threshold follows the amplitude of the input line signal. The signals amplified by TR1 and TR2 are further amplified by TR4 and TR5. The output from the collectors of TR4 and TR4 consist of positive and negative mark binary signals. These can be readily used by normal TTL logic circuits. TR1, TR2 and TR3 and PNP transistors. These have a low transistion frequency so are operated in a non saturating mode to obtain the necessary speed for operating the circuit at 2Mb/s. TR1 and TR2 are prevented from saturating by the clamping of their collectors by the base emitter diodes of TR4 and TR5. The latter transistors are NPN and having a high transition frequency which allows them to be used in a saturating mode. Capacitors C2 and C3 provide frequency compensation necessary if the circuit is being driven from a long length coaxial cable. The transistors TR1-TR5 can be replaced by integrated circuits which cut down the number of components required for this circuit. The circuit is ideally suited for implementation in intregrated form when costs become more attractive. The circuit was designed orginally to work at 2048 kbit/sec with a standard n883 coded input signal. With minor adjustments to the compensation capacitors the circuit should operate up to 8 Mbit/sec. At higher frequencies the transistors TR4 and TR5 would have to be operated in the non saturating mode. CLAIMS

1. An input circuit for use in receiving line signals of the bipolar return to zero type, the circuit including means for tapping off, rectifying and smoothing part of the received input signal to generate a d.c. voltage which follows the amplitude changes of the input signal which d.c. voltage is used to vary the threshold of a level detector circuit associated with a line signal amplifier.

2. An input circuit according to claim 1 in which the line signal amplifier comprises a long-tail triplet and the d.c. voltage is used to control the current in one of the transistors of the triplet.

3. An input circuit substantially as shown and described with reference to the accompanying drawing.