GB2029053A

GB2029053A - Improvements in or Relating to Methods of Detecting and Preventing the Retransmission of Subsequently Altered Store Contents

Info

Publication number: GB2029053A
Application number: GB7928861A
Authority: GB
Original assignee: Felten and Guilleaume AG
Current assignee: Felten and Guilleaume AG
Priority date: 1978-08-19
Filing date: 1979-08-20
Publication date: 1980-03-12
Also published as: BE878276A; LU81603A1; ES483471A1; YU202579A; NL7906180A; DE2836420A1; FR2433806A1

Abstract

In diode matrices 1 serving as stores, by a reprogramming of intact coupling points the store content can be subsequently falsified or even after prolonged operation individual coupling points can revert into the unprogrammed state, which also falsifies the store content. To guard against this each word is stored in complementary forms in a pair of locations and on readout of the store contents the opposite state of each store location pair associated with each data bit is checked 6 and, according to the result of this verification, the stored data is retransmitted or not by means of a switch 7. <IMAGE>

Description

SPECIFICATION Improvements In or Relating to Methods of Detecting and Preventing the Retransmission of Subsequently Altered Store Contents The invention relates to methods of detecting and preventing the retransmission of subsequently altered store contents, for instance in diode matrices constructed as identification keyers in communication technology.

Diode matrix assemblies are increasingly employed e.g. in signal networks as name or identification keyers for identifying a given associate station.

Such assemblies are formed according to the cross-bar principle. The coupling points are formed by diodes. The coupling diodes simultaneously decouple the inputs and outputs of the assembly relative to each other. With each coupling diode there is connected in series a fuse in the form of a low-load (low power rating), low value resistor. In the unprogrammed state all fuses are intact and all coupling points are unmarked. This condition is illustrated in Figure 1 of the accompanying drawings. One of these intact fuses is shown at 11.

The programming or marking of a coupling point is effected in a manner whereby, through the access paths leading to the coupling point concerned, i.e. address wire 13 and readout wire 14, a current JP is passed, the intensity of which is sufficient to break the associated fuse by meltdown. This process, illustrated in Figure 2 of tha accompanying drawings, is generally final, and the coupling point is permanently marked by the programming. Such a marked coupling point bears the reference 12.

However, this in itself reliable and low-cost method of information storage has two serious disadvantages: 1. The store content can be subsequently falsified by the reprogramming of intact coupling points.

2. As shown by operational experience so far gained with these diode matrices, under certain programming conditions programmed coupling points can revert to the unprogrammed state. The return to the unprogrammed state may occur after prolonged faultless operation of the store (Electronic Industry, 11-1976, p.300-302).

According to the invention, there is provided a method of detecting and preventing the retransmission of subsequently altered store contents, in which: two paired store locations are allocated to each data bit; the programming of the store is effected in such a manner that the store location of the pair allocated to each data bit assume opposing states, respectively; during readout, the opposite state of each store location pair associated with each data bit is checked by a logic circuit; and a switch controlled by the logic circuit, prevents the transmission of the stored data if the checking yields a negative result.

It is thus possible to recognize in programmed store matrices stored information which has been subsequently altered, and to exclude the altered information from the retransmission.

A method and apparatus for recoding of signals, in particular of selective calling, in which the otherwise required word-synchronization is replaced with a twofold serial transmission of the address in pailndrome-code is known. In this code, the individual code components are arranged in temporal mirror-image relative to an axis of symmetry, that is, an address is transmitted alternately in normal and inverted sequence. However, the bit-positions associated with each other are equal and not inverted (German Auslegeschrift 23 39 868).

However, in a preferred method, for a relatively low expenditure, an almost complete security against store changes caused by manipulation or environmental influences can be achieved.

The invention will be further described, by way of example, with reference to Figure 3 of the accompanying drawings, which shows a store matrix 1 with five word addresses 13 of four bits each. In contrast to known arrangements, the coupling points and the readout wires are duplicated. The store matrix is shown in the unprogrammed state.

Programming is effected in the manner whereby in each case two coupling points associated with a data bit of the same word address assume opposite states after programming, which can be read out in the conventional manner over the readout wires A to D and, in the inverted manner over the readout wires A' to D'.

The readout lines A and A', B and B', C and C' and D and D' are connected in pairs to the inputs respective exclusive-OR gates 2 to 5. If the fourbit word appearing on the readout lines is true, i.e.

if the coupling points associated with a pair are, owing to correct programming, in the inverse state (one coupling point conducts, the other does not), then the exclusive-OR gates 2 to 5 receive on their inputs the logic levels LH (Low-High) or HL (High-Low). In this case, the outputs of the exclusive-OR gates 2 to 5 are at H-level. The outputs of the exclusive-OR gates 2 to 5 are connected to respective inputs of an AND-gate 6.

The AND-gate 6 supplies at its output the logic-level H when all the exclusive-OR gates 2 to 5 supply H-levels at their outputs, i.e. when the information read is true. The readout wires A, B, C and D also lead to a switch 7. The switch switches the readout four-bit word through to the output of the assembly, because its control input receives the logic-level H from the AND-gate 6.

On the other hand, if the store content has been altered after completed programming, then at least one pair of coupling points will be in the same state. It then follows that the inputs of the exclusiveOR gate associated with the defective coupling point pair concerned receives the logiclevels L/L or H/H and the output thereof is at logic-level L. The corresponding output Level L is thus supplied to one of the inputs of the ANDgate 6, whose output is thus also at logic-level L, resulting in blocking of the switch 7. The control input of the switch 7 receives L-level, and the switch passes into the open state (tri-state). The defective word data is excluded from transmission.

If the outputs of the switch 7 are connected to a computer, then from the latter a further connecting line, not shown in Figure 3, leads to the switch 7. Only when a call signal from the computer appears on this line will the data available on the inputs be transmitted to the computer. When this call signal is absent, the outputs of switch 7 are highly resistive (isolated).

If the switch 7 is blocked by the AND-gate 6, it can nevertheless happen that the state prevailing on the output of switch 7 does not clearly signify an error condition for the computer, but rather a correct word signal is being deceptively offered.

For this reason, the switch 7 arranged so that on blocking it allows a special pseudotetrade to appear at the output, which is then recognized by the computer as an error condition. This pseudotetrade may for example be generated by applying through high value resistors the logiclevel H to at least two of the highest-ranking output lines of the switch 7.

Claims

1. A method of detecting and preventing the retransmission of subsequently altered store contents, in which: two paired store locations are allocated to each data bit; the programming of the store is effected in such a manner that the store locations of the pair allocated to each data bit assume opposing states, respectively; during readout, the opposite state of each store location pair associated with each data bit is checked by a logic circuit; and a switch controlled by the logic circuit, prevents the transmission of the stored data if the checking yields a negative result.

2. A method as claimed in claim 1, in which a predefined logic level is supplied through high value resistors to at least the two highest-ranking output lines of the switch.

3. A method of detecting and preventing the retransmission of subsequently altered store contents in diode matrices constructed as identification keyers in communications technology, substantially as herein-before described with reference to Figure 3 of the accompanying drawings.