GB2307320A

GB2307320A - Non-volatile memory cell and method of storing data therein

Info

Publication number: GB2307320A
Application number: GB9523665A
Authority: GB
Inventors: Yair Orbach; Vladimir Koifman
Original assignee: Motorola Inc
Current assignee: Motorola Solutions Inc
Priority date: 1995-11-18
Filing date: 1995-11-18
Publication date: 1997-05-21
Anticipated expiration: 2015-11-18
Also published as: GB9523665D0; GB2307320B

Abstract

A memory cell 1 comprises a common signal line 3 connected to the input of a switching arrangement 2, the common signal line 3 being connected to first and second reference voltages Vn, Vp via first and second fusible or anti-fusible links 4, 5. The conductive state of one of the fusible or anti-fusible links 4, 5 is permanently changed during a programming procedure, so that during normal operation the cell provides the desired output even after a reset operation or a shut down. The fusible link may be conductive and changed to a permanent open circuit or the anti-fusible link may be non-conducting and changed to a permanent low resistance path. The memory cell is particularly useful in applications that must not have floating gates, such as CMOS integrated circuit chips.

Description

NON-VOLATILE MEMORY CELL AND METHOD OF STORING DATA THEREIN Field of the Invention This invention relates to the storage of information and, more particularly, to the storage of data in a non-volatile memory cell, which may be a CMOS memory cell.

Background of the Invention In integrated circuit applications there is often the need to pre-program the behaviour of an integrated circuit chip following the interruption of the power supply, or after a reset. There are many functions that may require preprogramming, such as security key programming or the multiplication factor of an on-chip phase-locked-loop (PLL).

In order to ensure the reliable operation of the chip in these circumstances, it is necessary to store the parameters for these functions in such a way that they are not affected by the above-mentioned operations.

One technique for ensuring the desired functioning of a chip after a reset is to store the necessary data in read only memory (ROM). However, since this option requires the information to be included in the chip design at the manufacturing stage it is generally only suitable for the production of large numbers of identical chips.

It is also known to store information in electrically programmable read only memory (EPROM) , but this is an expensive alternative involving nonstandard processes.

In chips incorporating bipolar technology, it is known to store data by selectively opening a fuse associated with each memory cell. In such a cell the absence of a fuse connection sets the cell to a logic '1' state, whereas the presence of a fuse connection sets the cell to a logic '0' state. The output of the memory cell is permanently set by the presence or absence of a fuse connection. Such a device is a write once device and offers a convenient and flexible way of storing parameters on a chip.

However, it is not possible to employ the known cells with fuses from bipolar technology in chips based on CMOS technology, because in CMOS circuits an undefined input associated with an open fuse would result in a floating gate and hence an undefined cell output.

The present invention therefore seeks to provide a non-volatile memory cell which mitigates the above-mentioned disadvantages.

Summarv of the Invention According to the present invention there is provided a non-volatile memory cell comprising a first voltage rail coupled to a common signal path via a first fusible link and a second voltage rail coupled to the common signal path via a second fusible link; switching means comprising an input coupled to said common signal path; and programming means for permanently changing the conductive state of one of said first and second fusible links.

In this manner it is possible to provide a non-volatile memory cell offering the flexibility of fusible links, whilst avoiding the disadvantage of floating inputs associated, for example, with CMOS chips.

In addition, the invention provides a method of storing data in a non-volatile memory cell comprising a first voltage rail coupled to a common signal path via a first fusible link and a second voltage rail coupled to said common signal path via a second fusible link; and switching means comprising an input coupled to said common signal path; said method comprising the steps of selecting a programming mode in which said switching means are disabled; selectively programming a predetermined one of said fusible links by applying a high voltage across the predetermined one of said fusible links, thereby permanently changing the conductive state of said fusible link; and selecting an operating mode in which said switching means are enabled and said high voltage is removed from the predetermined one of said fusible links, the output of said memory cell being dependent on the choice of fusible link selected during the selective application of said high voltage.

Hence the invention provides for the possibility of programming a memory cell in a special programming mode whilst the remaining circuits on the chip are disabled. With the chip in normal mode, the programmed data is active following a reset or a power-on operation.

Brief Description of the Drawing An exemplary embodiment of the invention will now be described with reference to the drawing in which: FIG. 1 shows a circuit diagram of programmable CMOS memory cell.

Detailed Description of a Preferred Embodiment Referring to FIG.1, there is shown a non-volatile floating gate memory cell 1 embodying the preferred features of the present invention. Typically, many cells of the type shown in FIG. 1 would be provided on a single integrated circuit chip. Since, however, the function of each cell is substantially identical, the following detailed explanation will be restricted to the single cell shown.

Memory cell 1 contains a transfer gate 2 having an input connected to a common signal line 3, which is connected via first fusible link 4 and second fusible link 5 to first and second reference voltage lines Vn and Vp, respectively. The output of the memory cell 1 is connected to internal circuits on the chip via inverter 6.

In the present example fusible links 4 and 5 consist of strips of conductive material such as metal or polysilicon having a cross-sectional area smaller than that of other circuit conductors. The fusible links are designed to conduct the current required for normal operation of the circuit without physical damage. However, a high current lasting for a period of tens of milliseconds will melt the conductive material of the fusible link and result in a permanent open circuit.

Alternatively, fusible links 4 and 5 may be replaced by so-called antifuses, which operate on the reverse principle, whereby a high current through the non-conducting antifuse results in a permanent low-resistance path.

Also associated with memory cell 1 is control logic (not shown) that is used to select a particular memory cell via the control line S and to define a programming mode (explained below) via the control line P.

In addition, the control logic switches a transistor 7 that is provided between the common signal line 3 and a reference potential, in the present example ground.

Typically, an array of memory cells of the type shown in FIG. 1 on a chip share the same Vp and Vn lines and control line P.

Prior to normal operation of a device containing the memory cell of FIG. 1 it is necessary to program each cell, so that every cell output is electrically defined.

The operation of programming the memory cells will now be explained.

In the first programming step, each cell is switched to programming mode by asserting a signal on the control line P. This operation may be carried out by means of a special chip mode, such as a secret test mode.

When control line P is asserted, circuits that are not involved in the programming operation are disabled and are thereby protected from the high voltages used during programming, leaving only control logic circuits associated with the programming active.

Next the control logic asserts the SELECT signal on control line S for each cell in turn and at the same time connects either the Vp or the Vn line to a high voltage (typically +12V) in accordance with the desired value to be programmed into the particular cell.

As can be seen from FIG.1, when both the control lines S and P are asserted transistor 7 is switched on by the control logic, thereby connecting the high voltage on the selected Vn or Vp line to ground via fusible link 4 or 5.

Transistor 7 is chosen to have a low on resistance of, say, a few ohms, so that almost all of the high voltage applied to the Vp or Vn line drops across the selected fusible link, melting the conductive material and forming an open circuit.

The programming of the individual cell ends when the fusible link melts and the high voltage is disconnected from common signal line D. At this time the control logic selects the next cell and the programming procedure is repeated.

When all cells have been programmed in the above manner the signal on control line P is negated, with the result that the transistor 7 is switched off.

Moreover, the control logic connects the voltage reference lines Vp and Vn to the levels required for normal chip operation. In a standard CMOS application, Vp would be set to +5V and Vn would be set to OV during normal operation.

With the signal on control line P negated, the chip reverts to normal mode in which the transfer gate 2 transfers the signal present on common signal line 3 to the inverter 6.

Thus for a typical CMOS application, if a logic value '0' is required on the common signal line 3 of a particular memory cell during normal operation, then the control logic must apply the high voltage to the line Vp during programming. Alternatively, application of the high voltage to the line Vn during programming would result in a logic value '1' on signal line 3 during normal operation.

In order to prevent a short circuit between the Vp and Vn voltage lines during normal operation of the chip, it is necessary to program every cell in the manner described above prior to running the chip in normal mode. If the programming is carried out correctly, then every memory cell on the chip will have a well defined input value and there will be no floating gates; hence the memory cells described are suitable for use in CMOS chips. Moreover, the double fuse structure ensures that each open fuse will not reconnect after programming. This is because even if a conducting path were to be reestablished in an opened fusible link, this conducting path will represent both a weak point and a highly resistive link and will automatically disconnect itself again even under normal operation.

Since transistors 7 and 2 are subjected to the high voltages used during programming, they will normally require a thicker gate oxide. However, this design feature does not require special processing.

Due to the presence of the relatively large transistor 7 in each cell, a preferred application of the present invention would be the storage of parameter values on a chip, rather than, say, the provision of a memory cache.

Claims

1. A non-volatile memory cell comprising: a first voltage rail (Vn) coupled to a common signal path (3) via a first fusible link (4) and a second voltage rail (Vp) coupled to said common signal path (3) via a second fusible link (5); switching means (2) comprising an input coupled to said common signal path (3); and programming means for permanently changing the conductive state of one of said first and second fusible links (4,5).

2. A non-volatile memory cell according to claim 1, wherein said memory cell is a transfer gate memory cell.

3. A non-volatile memory cell according to claim 1 or 2, wherein said memory cell is a CMOS memory cell.

4. A non-volatile memory cell according to any one of the proceeding claims, wherein said fusible links (4,5) are metal links.

5. A non-volatile memory cell according to any one of the proceeding claims, wherein said programming means comprise logic means adapted for switching a high voltage across one of said first or second fusible links (4,5) to change the conductive state of said one fusible link.

6. A non-volatile memory cell according to claim 5, wherein said programming means further comprise a transistor (7) having a current electrode coupled to said common signal path (3) and a control electrode coupled to said logic means.

7. A method of storing data in a non-volatile memory cell comprising a first voltage rail (Vn) coupled to a common signal path (3) via a first fusible link (4), a second voltage rail (Vp) coupled to said common signal path (3) via a second fusible link (5) and switching means (2) comprising an input coupled to said common signal path (3), said method comprising the steps of: selecting a programming mode in which said switching means (2) are disabled; selectively programming a predetermined one of said fusible links (4,5) by applying a high voltage across the predetermined one of said fusible links (4,5), thereby permanently changing the conductive state of said fusible link; and selecting an operating mode in which said switching means (2) are enabled and said high voltage is removed from the predetermined one of said fusible links (4,5), the output of said memory cell being dependent on the choice of fusible link selected during the selective application of said high voltage.

8. A method according to claim 7, wherein said memory cell is a transfer gate memory cell.

9. A method according to claim 7 or 8, wherein said memory cell is a CMOS memory cell.

10. A method according to any one of claims 7 to 9, wherein said fusible links (4,5) are metal links.

11. A method according to any one of claims 7 to 10, wherein said high voltage is applied across one of said first or second fusible links by a transistor (7) having a current electrode coupled to said common signal path (3).

12. A method according to any one of claims 7 to 11, wherein said memory cell is one of a plurality of memory cells and each of said plurality of memory cells is selected serially for said programming of said fusible links (4,5) prior to said selection of said operating mode.

13. A non-volatile memory cell substantially as hereinbefore described with reference to the accompanying drawing.

14. A method of programming a non-volatile memory cell substantially as hereinbefore described with reference to the accompanying drawing.