GB2010547A - Command Buffer for Cache Memory - Google Patents
Command Buffer for Cache MemoryInfo
- Publication number
- GB2010547A GB2010547A GB7848441A GB7848441A GB2010547A GB 2010547 A GB2010547 A GB 2010547A GB 7848441 A GB7848441 A GB 7848441A GB 7848441 A GB7848441 A GB 7848441A GB 2010547 A GB2010547 A GB 2010547A
- Authority
- GB
- United Kingdom
- Prior art keywords
- memory unit
- cache memory
- data
- cache
- main memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1673—Details of memory controller using buffers
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
- Information Transfer Systems (AREA)
- Image Input (AREA)
Abstract
Apparatus and method for providing a buffer stage, or cache memory command circuit, between a cache memory unit and a main memory unit. The transfer of data between a main memory unit and a cache memory unit can be complicated because the circuits utilized in the cache memory unit and/or the main memory unit in effectuating the data transfer can be pre-empted. In addition, the data transfers must be executed in sequential order. According to the present invention, the transfer of data is divided into two portions, a portion involving cache memory unit and a portion involving the main memory unit along with associated interface units. The cache memory unit stores the data transfer commands and the associated data in sequential order (in 220, 230). The cache memory unit and the main memory and interface units can execute their respective portions of the data transfer independently permitting overlapped instruction execution. The cache command buffer insures that the operations involving the two units of the data processing unit are executed in sequence. When data transfer has been completed, the cache command circuit continues to the execution of the next data transfer in sequence. <IMAGE>
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US86122877A | 1977-12-16 | 1977-12-16 |
Publications (2)
Publication Number | Publication Date |
---|---|
GB2010547A true GB2010547A (en) | 1979-06-27 |
GB2010547B GB2010547B (en) | 1982-05-19 |
Family
ID=25335228
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB7848441A Expired GB2010547B (en) | 1977-12-16 | 1978-12-14 | Command buffer for cache memory |
Country Status (6)
Country | Link |
---|---|
JP (1) | JPS5489532A (en) |
AU (1) | AU521383B2 (en) |
CA (1) | CA1116756A (en) |
DE (1) | DE2854286A1 (en) |
FR (1) | FR2412139B1 (en) |
GB (1) | GB2010547B (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2447077A1 (en) * | 1978-12-11 | 1980-08-14 | Honeywell Inf Systems | ANTEMEMORY UNIT WITH ORDER WAITING DEVICE |
EP0046781A1 (en) * | 1980-01-28 | 1982-03-10 | Digital Equipment Corp | Cached multiprocessor system with pipeline timing. |
EP0115344A2 (en) | 1983-01-27 | 1984-08-08 | Nec Corporation | Buffer control system |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
AU529675B2 (en) * | 1977-12-07 | 1983-06-16 | Honeywell Information Systems Incorp. | Cache memory unit |
US4370710A (en) * | 1980-08-26 | 1983-01-25 | Control Data Corporation | Cache memory organization utilizing miss information holding registers to prevent lockup from cache misses |
JPH0337955U (en) * | 1989-08-24 | 1991-04-12 |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR111566A (en) * | 1974-10-04 |
-
1978
- 1978-12-12 FR FR7834969A patent/FR2412139B1/en not_active Expired
- 1978-12-12 CA CA000317779A patent/CA1116756A/en not_active Expired
- 1978-12-12 AU AU42428/78A patent/AU521383B2/en not_active Expired
- 1978-12-13 JP JP15406278A patent/JPS5489532A/en active Granted
- 1978-12-14 GB GB7848441A patent/GB2010547B/en not_active Expired
- 1978-12-15 DE DE19782854286 patent/DE2854286A1/en active Granted
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2447077A1 (en) * | 1978-12-11 | 1980-08-14 | Honeywell Inf Systems | ANTEMEMORY UNIT WITH ORDER WAITING DEVICE |
EP0046781A1 (en) * | 1980-01-28 | 1982-03-10 | Digital Equipment Corp | Cached multiprocessor system with pipeline timing. |
EP0046781A4 (en) * | 1980-01-28 | 1984-06-13 | Digital Equipment Corp | Cached multiprocessor system with pipeline timing. |
EP0115344A2 (en) | 1983-01-27 | 1984-08-08 | Nec Corporation | Buffer control system |
Also Published As
Publication number | Publication date |
---|---|
AU4242878A (en) | 1979-06-21 |
FR2412139A1 (en) | 1979-07-13 |
JPS6148745B2 (en) | 1986-10-25 |
CA1116756A (en) | 1982-01-19 |
JPS5489532A (en) | 1979-07-16 |
DE2854286A1 (en) | 1979-06-28 |
DE2854286C2 (en) | 1989-10-12 |
GB2010547B (en) | 1982-05-19 |
FR2412139B1 (en) | 1986-05-09 |
AU521383B2 (en) | 1982-04-01 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PCNP | Patent ceased through non-payment of renewal fee |