GB1601753A - Method of defining film patterns on microelectronic substrates - Google Patents
Method of defining film patterns on microelectronic substrates Download PDFInfo
- Publication number
- GB1601753A GB1601753A GB1896078A GB1896078A GB1601753A GB 1601753 A GB1601753 A GB 1601753A GB 1896078 A GB1896078 A GB 1896078A GB 1896078 A GB1896078 A GB 1896078A GB 1601753 A GB1601753 A GB 1601753A
- Authority
- GB
- United Kingdom
- Prior art keywords
- film
- film coating
- coating
- substrate
- mask
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/04—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed mechanically, e.g. by punching
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
- H05K3/061—Etching masks
- H05K3/062—Etching masks consisting of metals or alloys or metallic inorganic compounds
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0302—Properties and characteristics in general
- H05K2201/0317—Thin film conductor layer; Thin film passive component
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/032—Materials
- H05K2201/0326—Inorganic, non-metallic conductor, e.g. indium-tin oxide [ITO]
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/20—Details of printed circuits not provided for in H05K2201/01 - H05K2201/10
- H05K2201/2081—Compound repelling a metal, e.g. solder
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/02—Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
- H05K2203/025—Abrading, e.g. grinding or sand blasting
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Metallurgy (AREA)
- Manufacturing Of Printed Circuit Boards (AREA)
- Manufacturing Of Printed Wiring (AREA)
- Electroplating Methods And Accessories (AREA)
Description
(54) METHOD OF DEFINING FILM PATTERNS ON
MICROELECTRONIC SUBSTRATES
(71) We, E-SYSTEMS INC., a corporation organised under the laws of the State of
Delaware, United States of America of 1600
Pacific, Dallas, Texas 75201, United States of America, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed to be particularly described in and by the following statement:
This invention relates to a process for forming electroconductive patterns on substantially nonconductive substrates, and more particularly to a process for delineating patterns having improved width and spacing tolerances.
In applications where electroconductive coatings are applied to nonconductive substrate materials such as glass, ceramics, plastics and the like, it is difficult to apply patterned coatings directly to the substrate.
Therefore, continuous coatings are applied and are thereafter patterned. Prior processes for delineating a pattern in a continuous coating have included placing a separately formed unattached mask over the continuous coating such that the mask has the desired pattern. The electroconductive coating is then sand-blasted around the mask. Because the mask is merely held in place, some undercutting of the coating takes place causing the resulting pattern to have uneven edges, resulting in undesirable electrical properties of the coating.
Other earlier methods of delineating a patterned electroconductive coating include etching, electric burning and the like.
However, these methods have been found to be unsatisfactory where the patterns are small, the substrate surface uneven and where the pattern line width or the spacing between the lines is small and requires a high degree of definition.
Prior methods of delineating a patterned electroconductive coating have also included bonding of the mask to a nonconductive substrate. A prior bonding method is described and claimed in U.S. Patent No.
3,240,624 by Ronald A. Beck entitled "Method of Forming a Pattern Electro
conductive Coating" and issued March 15, 1966. Such a method has required the application of a synthetic resin catalyst to be applied to the substrate film coating before the mask is applied. The mask, where a catalyst is used, is required to be of an uncured and uncatalyzed synthetic resinous material adapted to be cured by the catalyst.
The application of such a mask material tends to yield masks which have poor line width and tolerances. Furthermore, masks which are composed of snythetic resinous materials cannot be utilized as an integral part of the electroconductive pattern to in dude fabricated circuit elements.
A need has thus arisen for a process for forming electroconductive patterns having improved line width and spacing resolution, that is easily and economically feasible to manufacture. Moreover, a need has arisen for a process for delineating a patterned electroconductive coating in which circuit elements are fabricated within the mask that is used to fabricate the pattern.
The present invention provides for an improved process of delineating patterned electroconductive coatings on a nonconductive substrate. This process provides for an economical and simplified process for fabricating patterned electroconductive coatings.
In accordance with the present invention, there is provided a process for delineating a patterned electroconductive coating on a substantially nonconductive substrate, the process comprising the steps of:- forming a substantially continuous film coating of an electroconductive abradable material on the substrate;
applying to said film coating a mask film of metallic material which is abrasive resistant so that said metallic material intimately contacts said film coating.
forming masked and unmasked portions of said film coating corresponding to the desired patterned coating by selectively removing portions of said mask film while said mask film is in intimate contact with said film coating;
air abrading the unmasked portions of said film coating, while said mask film is in intimate contact with said film coating, thereby leaving the masked portions of said film coating remaining on the substrate and forming the desired pattern in said film coating; and
removing said mask film from said film coating, resulting in the desired pattern delineated in said film coating on the substrate.
An embodiment of the present invention will now be described in conjunction with the accompanying drawings, in which:
FIGURE 1 is a cross-sectional view of a substrate illustrating a first step in the formation of a delineated pattern on the substrate in accordance with the embodiment of the present invention;
FIGURE 2 is a cross-sectional view of a substrate illustrating a second step of the process; FIGURE: 3 is a cross-sectional view of a substrate illustrating a third step of the process;
FIGURE 4 is a cros-sectional view of a substrate illustrating a fourth step of the process;
FIGURE 5 is a cross-sectional view of a substrate illustrating a fifth step of the process; and
FIGURE 6 is a cross-sectional view of a substrate illustrating an alternative sixth step of the process.
Referring to FIGURE 1, the first step in the process is the application of a sub- stantially continuous film coating 10 of an electroconductive material to a nonconductive substrate 12. Suitable substrate materials are glass, ceramics, alumina, and the like. The electroconductive material forming film coatings 10 may comprise, for example, antimony doped tin oxide and is applied to the substrate 12 in the conventional manner.
Referring to FIGURE 2, the second step in the process is the application to the film coating 10 of a mask film 14 of metallic material having the characteristics of being air abrasive resistant relative to the film coating 10. An important aspect of the process is that the mask film 14 is in intimate contact with the electroconductive material such as antimony doped tin oxide of the film coating 10 of the substrate 12.
The intimate contact of mask film 14 with film coating 10 reduces any undercutting which could occur when unmasked portions of film coating 10 are air abraded, as will be hereinafter discussed, thereby providing improved pattern delineation.
The mask film 14 may be applied to the electroconductive film coating 10 either by selectively electroplating the mask film 14 on to the deposited film coating 10 or by using standard vacuum deposit techniques to apply the mask film 14 directly to the film coating 10.
As illustrated in FIGURE 3, the next step in the process is to selectively chemically etch the mask film 14. This step results in the formation of masked portions such as at 16 and unmasked portions such as at 18 of the film coating 10 corresponding to the desired pattern. The etching of the mask film 14 can be performed using standard photolithographic techniques.
The mask film 14 is comprised of a metallic material and may be formed from such material as copper, nickel or gold.
The process used to generate a typical copper mask consists of vacuum depositing a thin film of gold (not shown) on to the film coating 10. The film of gold is then selectively plated up to approximately 300 microinches with copper using a Photoresist as a mask. The thin film of gold, approximately 1000 angstroms in thickness, covers the film coating 10. Masked and unmasked portions of the film coating 10 are then formed corresponding to the desired pattern by selectively removing portions of the mask film while the mask film is in intimate contact with the film coating.
Areas of the gold film which are not plated with copper can be selectively etched to form the desired pattern of unmasked portions 18 which afe next subjected to an air abrading technique as described below.
Referring to FIGURE 4, the fourth step in the process is the removal of the unmasked portions 18 of the film coating 10 using an air abrading technique. The air abrading process cah be performed by standard sandblasting methods using a stream of suitably sized particles. For example, particles having a size from about 10 microns to about 25 microns can be used in a stream of air to remove the film coating 10 in the region of the unmasked portions 18 to thereby uncover portions of the surface of the substrate 12.
As illustrated in FIGURE 5, the final step in the process is the removal of the remaining portions 16 of the mask film 14 to leave the delineated pattern in the film coating 10. The mask film can be removed by standard etching techniques.
As an alternative step to removing the entire mask film coating 14, selective parts of portions 16 of the mask film 14 can be etched, using standard procedures well known in the art as illustrated in FIGURE 6. This step forms usable electrical components in the mask film 14. In this embodiment, the mask forms an integral portion of the end semiconductor device and may include resistors, capacitors and inductors, such as at 20 and terminals such as at 22 for the bonding of discrete components.
It can therefore be seen that the above process for delineating a patterned electroconductive coating on a substrate is simple to perform, rapid to complete and results in a more versatile end product. The process has been demonstrated to yield lines and spaces with tolerances of + .0002 inches and a degree of resolution which has been heretofore not possible with prior patterned delineating processes.
WHAT WE CLAIM IS:
1. A process for delineating a patterned electroconductive coating on a substantially nonconductive substrate, the process comprising the steps of:
forming a substantially continuous film coating of an electroconductive abradable material on the substrate;
applying to said film coating a mask film of metallic material which is abrasive resistant so that said metallic material intimately contacts said film coating
forming masked and unmasked portions of said film coating corresponding to the desired patterned coating by selectively removing portions of said mask film while said mask film is in intimate contact with said film coating;
air abrading the unmasked portions of said film coating, while said mask film is in intimate contact with said film coating, thereby leaving the masked portions of said film coating remaining on the substrate and forming the desired pattern in said film coating; and
removing said mask film from said film coating, resulting in the desired pattern delineated in said film coating on the substrate.
2. The process described in Claim 1 wherein said mask film or portions thereof are removed from said film coating by chemical etching.
3. The process described in Claim 1 or 2 wherein said mask film is applied to said film coating by electroplating.
4. The process described in Claim 1 or 2 wherein said mask film is applied to said film coating by vacuum depositing.
5. The process described in any one of the preceding claims wherein the electroconductive abradable material is antimony doped tin oxide.
6. The process described in any one of the preceding claims wherein said metallic material is selected from a group consisting of copper, nickel, gold or combinations thereof.
7. The process described in any one of claims 1-5 wherein said mask film includes a film of gold which is vacuum deposited on the film coating.
8. The process described in any one of the preceding claims wherein said air abrading step includes the use of air abrading particles having a particle size of from
about 10 microns to about 25 microns.
9. A process for delineating a patterned electroconductive coating on a substantially non-conductive substrate substantially as herein described with reference to the accompanying drawings.
10. A patterned substrate produced according to the method of any one of the preceding claims.
**WARNING** end of DESC field may overlap start of CLMS **.
Claims (10)
1. A process for delineating a patterned electroconductive coating on a substantially nonconductive substrate, the process comprising the steps of:
forming a substantially continuous film coating of an electroconductive abradable material on the substrate;
applying to said film coating a mask film of metallic material which is abrasive resistant so that said metallic material intimately contacts said film coating
forming masked and unmasked portions of said film coating corresponding to the desired patterned coating by selectively removing portions of said mask film while said mask film is in intimate contact with said film coating;
air abrading the unmasked portions of said film coating, while said mask film is in intimate contact with said film coating, thereby leaving the masked portions of said film coating remaining on the substrate and forming the desired pattern in said film coating; and
removing said mask film from said film coating, resulting in the desired pattern delineated in said film coating on the substrate.
2. The process described in Claim 1 wherein said mask film or portions thereof are removed from said film coating by chemical etching.
3. The process described in Claim 1 or 2 wherein said mask film is applied to said film coating by electroplating.
4. The process described in Claim 1 or 2 wherein said mask film is applied to said film coating by vacuum depositing.
5. The process described in any one of the preceding claims wherein the electroconductive abradable material is antimony doped tin oxide.
6. The process described in any one of the preceding claims wherein said metallic material is selected from a group consisting of copper, nickel, gold or combinations thereof.
7. The process described in any one of claims 1-5 wherein said mask film includes a film of gold which is vacuum deposited on the film coating.
8. The process described in any one of the preceding claims wherein said air abrading step includes the use of air abrading particles having a particle size of from
about 10 microns to about 25 microns.
9. A process for delineating a patterned electroconductive coating on a substantially non-conductive substrate substantially as herein described with reference to the accompanying drawings.
10. A patterned substrate produced according to the method of any one of the preceding claims.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US82520977A | 1977-08-17 | 1977-08-17 |
Publications (1)
Publication Number | Publication Date |
---|---|
GB1601753A true GB1601753A (en) | 1981-11-04 |
Family
ID=25243385
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB1896078A Expired GB1601753A (en) | 1977-08-17 | 1978-05-11 | Method of defining film patterns on microelectronic substrates |
Country Status (2)
Country | Link |
---|---|
JP (1) | JPS5432771A (en) |
GB (1) | GB1601753A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2002021882A1 (en) * | 2000-09-04 | 2002-03-14 | Cambridge Consultants Limited | Coating removal |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4232059A (en) * | 1979-06-06 | 1980-11-04 | E-Systems, Inc. | Process of defining film patterns on microelectronic substrates by air abrading |
-
1978
- 1978-04-27 JP JP5068378A patent/JPS5432771A/en active Pending
- 1978-05-11 GB GB1896078A patent/GB1601753A/en not_active Expired
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2002021882A1 (en) * | 2000-09-04 | 2002-03-14 | Cambridge Consultants Limited | Coating removal |
US6893326B2 (en) | 2000-09-04 | 2005-05-17 | Cambridge Consultants Limited | Coating removal |
Also Published As
Publication number | Publication date |
---|---|
JPS5432771A (en) | 1979-03-10 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PS | Patent sealed | ||
PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 19940511 |