GB1601115A - Rectifier circuits - Google Patents

Description

(54) IMPROVEMENTS RELATING TO RECTIFIER CIRCUITS (71) We, QUESTECH LIMITED, a British Company of 5, Chesters Road, Camberley, Surrey GU15 1AD, do hereby declare the invention for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement: This invention relates to rectifier circuits and concerns balanced full-wave rectifying circuits and anologue to digital converters embodying such circuits.

The circuit shown in Figure 1 of the accompanying drawing comprises transistors VT1 , VT2, VT3 and VT4 connected as a long tailed pair as shown with constant current loads 12, 14 in the two arms of the long tailed pair respectively defined by transistors VT1 and VT3 in series and transistors vT2 and VT4 in series. The emitters of transistors VTI and VT2 are coupled through associated emitter resistors R1 and R2 to a constant current source 16 in a conventional manner. A balanced input signal can be applied, in use, to terminals 18a and 18b and a balanced output signal would appear at the collectors of the transistors VT3 and VT4. The collectors of transistors VT3 and VT4 are connected across one diagonal of a full-wave bridge rectifier comprising diodes Dl, D2, D3 and D4, the other diagonal of which is connected through resistors R3 and R4 of equal value to a source of a reference voltage Vref and to balanced output terminals 20a and 20b. The collectors of the transistors VT3 and VT4 are also coupled by way of resistors R5 and R6 respectively to the bases of two further transistors VTs and VT6 having their emitters coupled through resistors R7 and R8 respectively and a common resistor Rg to a source of positive potential.

In operation of the circuit, a balanced input signal applied to the input terminals 18a and 18b is amplified by transistors VT1 , VT2, VT3 and VT4 and full-wave rectified by diodes D1, D2, D3 and D4 to provide a differential output signal which can be described by the equation: Vout = K(Vin - Vb) where K = the effective stage gain of the circuit, Vb = magnitude of a bias voltage effectively between the input terminals 1 8a and 18b, and is a function of the values of the resistance of resistors R1 and R2 and the static through transistors VT1 and VT2.

By suitable choice of the magnitudes of K, Vb and the dynamic range of the input voltage Vin, the output signal can be full-wave rectified such that each successive stage in a chain of similar stages as shown in Figure 1 yields one bit of digital information defining the magnitud of the input signal. In a practical arrangement, the first and succeeding odd numbered stages would have a configuration as shown in Figure 1, and the even numbered stages would include transistors of opposite conductivity type and reversed circuit polarities so that direct coupling could be used from stage to stage.

The transistors VT5 and VT6 serve to provide an output which detects the point at which the pairs of diodes Dl /D4 andD2/D3 change from a conductive to a non-conductive state; this output being fed to logic circuits (not shown) to produce a digitally coded output signal representative of the magnitude of the input signal Vin. The point of change of conduction through the diodes D1 to D4 occurs when the sign of the amplification of the stage changes, and occurs when Vin -Vb Two difficulties are experienced with this type of full-wave rectifier stage. First, the input base current for the transistors VT1 and VT2 imposes a load upon the output of the previous stage in a chain of similar circuits connected in cascade, and because of the temperature dependence of the base current, introduces a temperature variable factor which affects the accuracy and stability of analogue to digital conversion.

The second difficulty arises from the nonideal characteristic of practical diodes, in which the conduction resistance increases as the applied voltage is reduced. The effect of this is to produce a non-linear relationship between the output voltage Vout and the input voltage Vin. Whilst the use of the constant current collector loads 12, 14, as shown in Figure 1, for transistors VT3 and VT4 mini; mises this effect, the finite output impedance of transistors VT3 and VT4, and the need to connect transistors VTs and VT6 for detecting the diode switching point, impose a limit to the extent by which the non-linear effects can be reduced.

The present invention seeks to overcome one or both of these shortcomings by replacing transistors VTI and VT2, each by a transistor negative-feedback pair, in which one of the transistors is preferably of the field effect type.

In addition, there may be included a positive feedback circuit which enables the effective output impedance of the transistors VT3 and VT4 connected to the diode rectifiers to be raised substantially to infinity. To accommodate the variations of transistor characteristics present in practice, a variable element may be included for setting the positive feedback loop gain to the point where substantially ideal diode switching action is obtained.

According to the invention there is provided a balanced full-wave diode rectifying circuit comprising a balanced d.c. amplifier having first and second balanced outputs coupled to a fullwave diode rectifier and first and second balanced inputs and in which the amplifier is a differential amplifier including two, transistorpair negative feedback amplifiers, said two, transistor-pair amplifiers being connected in a long-tailed pair circuit, and the said balanced d.c. amplifier being provided with positive feedback means for increasing the output impedance at the first and second outputs.

By the term 'transistor-pair negative feedback amplifier' is meant an amplifier comprising a pair of transistors connected to form a twostage amplifier, the characteristics and interconnection of the transistors being such that the amplifier has negative voltage feedback.

Further according to the present invention, there is provided an analogue to digital converter comprising at least one circuit according to the invention, and preferably a plurality of such circuits connected in cascade, such that an output signal from each amplifier stage provides a digital representation of the sign of the amplification of each stage.

The invention will now be described by way of example, with reference to the accompanying drawings, in which: Figure 2 shows a circuit diagram of one embodiment of a balanced full-wave diode rectifying circuit according to the invention, Figure 3 shows a block circuit diagram of an analogue to digital converter according to the invention embodying circuits according to Figure 2, and Figure 4 shows diagrams illustrating operation of the circuit of Figure 2.

In Figure 2 circuit elements corresponding to those shown in Figure 1 have been allocated similar references and only the changes made to the circuit of Figure 1 will be described in detail.

In Figure 2, transistor VTI of Figure 1 is replaced by a transistor VT7 and a field effect transistor VT8 connected as shown with resistors R1 o, R1 1 to form a two transistor negative feedback amplifier. Similarly, transistor VT2 of Figure 1 is replaced by a transistor VTg and a field effect transistor VT10 connected as shown with resistors Tri 2, R13 to form a second two transistor negative feedback amplifier. For transistors VT7, VT8 , the negative feedback loop gain is determined by resistors R1 and R10 in conjunction with the characteristics of the transistors VT7 and VT8. Similarly, the negative feedback loop gain for transistors VTg and VT10 is determined by resistors R2 and R12 and in conjunction with the characteristics of transistors VTg and VTz o.

The positive feedback loop for the circuit comprising transistors VT7, VT8 and VT3 is provided by resistor R1 i which also serves as the drain load for field effect transistor VT8.

The positive feedback loop for the circuit comprising transistors VTg, VT10 and VT4 is provided by resistor R13 which likewise also serves as the drain load for field effect transistor VT10. A variable resistor Rf connected between the collectors of transistors VT3 and VT4 forms a collector load for these two transistors enabling the positive feedback gain to be controlled and set to provide a substantially infinite output impedance at the said collectors.

The presence of field effect transistors VT8 and VT10 ensures a sufficiently high input impedance, both static and dynamic, to reduce the loading effect on the previous stage to negligible proportions.

Such a stage as described with reference to Figure 2 employing field effect transistors at the input terminals could be connected to the output of a 'sample-and-hold' circuit without the need for an intermediate buffer stage.

Whilst the circuit of Figure 2 has been described as using field effect transistors VT8 and VT10 to obtain a high input impedance, other transistors such as bi-polar transistors could be used, in which case the input impedance would not be so high but the circuit would still have the advantages of the substantially infinite output inpedance.

Figure 3 shows an analogue to digital convertor 23 with a plurality of stages interconnected in series, where the first and following odd numbered stages 22 are of a similar configuration to that shown in Figure 2. The even numbered stages 22a use transistors of opposite conductivity type and reversed circuit polarities to that of Figure 2 so that direct coupling may be used from stage to stage.

Logic comparator circuits 24, 24a having inputs 24b, 24c coupled to the collectors of tran sistors VTs, ,VT6 respectively of their associated stage sense the sign of the amplication provided by each stage by detecting the sudden change in sign of the conduction voltage across the diode bridge as conduction switches abruptly between the diode pairs Dl/D4 and D2/D3 of Figure 2.

Figure 4(a) is a diagram showing the variation of the output voltage Vout of a circuit according to Figure 2, with variation of its input voltage Vin - Vb, and is seen to be always positive, with a change of sign in the amplification taking place where Vin = Vb. By arranging that each stage has an effective gain K = 2, the magnitude of the signal presented to successive stages is the same. Figure 4(b) is a diagram showing the output wareform of a logic comparator 24, 24a from which it will be noted that the binary output of a stage changes from binary 0 to binary 1 when Via increases to a value equal to or greater than Vb and changes from binary 1 to binary 0 when Vin reduces to a value equal to or less than Vb. Thus the outputs 24d" 24d2, 24d3, 24d4 and so on of the comparators 24 provide a digitally coded output representative of the magnitude of the input signal applied to the first stage of the analogue to digital convertor 23.

WHAT WE CLAIM IS: 1. A balanced full-wave diode rectifying circuit comprising a balanced d.c. amplifier having first and second balanced outputs coupled to a full-wave diode rectifier and first and second balanced inputs and in which the amplifier is a differential amplifier including two, transistor-pair negative feedback amplifiers, said two, transistor-pair amplifiers being connected in a long-tailed pair circuit, and the said balanced d.c. amplifier being provided with positive feedback means for increasing the output impedance at the first and second outputs.

2. A circuit according to Claim 1, in which one of the transistors in each negative feedback amplifier is a field effect transistor, the said first and second inputs being coupled to the gate electrode of an associated field effect transistor.

3. A circuit according to Claim 1 or 2, comprising means for adjusting the positive feedback between the first output and the first input relative to the positive feedback between the second output and the second input.

4. A circuit according to Claim 3, in which the means for adjusting comprises a variable resistance coupled between the first and second outputs.

5. A circuit according to Claim 2,3 or 4 as dependent upon claim 2, in which said positive feedback means comprises resistance means coupled between the drain electrode of each field effect transistor and the respective balanced output of the circuit.

6. A circuit according to any one of the preceding claims, comprising means for detecting and providing an output signal when the diodes in said rectifier change from one conductive state to the other conductive state.

7. A balanced full-wave diode rectifying circuit substantially as hereinbefore described with reference to and as illustrated in Figure 2 of the accompanying drawings.

8. An analogue to digital converter comprising at least one circuit .-.according to any one of the preceding claims.

9. An analogue to digital convertor according to claim 8 as dependent upon claim 6 comprising a plurality of said circuits connected in cascade and in which the said output signal from each amplifier stage is representative of the digital value of the stage.

10. An analogue to digital convertor substantially as hereinbefore described with reference to and as illustrated in Figure 3 of the accompanying drawings.

**WARNING** end of DESC field may overlap start of CLMS **.

Claims (10)

**WARNING** start of CLMS field may overlap end of DESC **. to Figure 2, with variation of its input voltage Vin - Vb, and is seen to be always positive, with a change of sign in the amplification taking place where Vin = Vb. By arranging that each stage has an effective gain K = 2, the magnitude of the signal presented to successive stages is the same. Figure 4(b) is a diagram showing the output wareform of a logic comparator 24, 24a from which it will be noted that the binary output of a stage changes from binary 0 to binary 1 when Via increases to a value equal to or greater than Vb and changes from binary 1 to binary 0 when Vin reduces to a value equal to or less than Vb. Thus the outputs 24d" 24d2, 24d3, 24d4 and so on of the comparators 24 provide a digitally coded output representative of the magnitude of the input signal applied to the first stage of the analogue to digital convertor 23. WHAT WE CLAIM IS:

1. A balanced full-wave diode rectifying circuit comprising a balanced d.c. amplifier having first and second balanced outputs coupled to a full-wave diode rectifier and first and second balanced inputs and in which the amplifier is a differential amplifier including two, transistor-pair negative feedback amplifiers, said two, transistor-pair amplifiers being connected in a long-tailed pair circuit, and the said balanced d.c. amplifier being provided with positive feedback means for increasing the output impedance at the first and second outputs.

2. A circuit according to Claim 1, in which one of the transistors in each negative feedback amplifier is a field effect transistor, the said first and second inputs being coupled to the gate electrode of an associated field effect transistor.

3. A circuit according to Claim 1 or 2, comprising means for adjusting the positive feedback between the first output and the first input relative to the positive feedback between the second output and the second input.

4. A circuit according to Claim 3, in which the means for adjusting comprises a variable resistance coupled between the first and second outputs.

5. A circuit according to Claim 2,3 or 4 as dependent upon claim 2, in which said positive feedback means comprises resistance means coupled between the drain electrode of each field effect transistor and the respective balanced output of the circuit.

6. A circuit according to any one of the preceding claims, comprising means for detecting and providing an output signal when the diodes in said rectifier change from one conductive state to the other conductive state.

7. A balanced full-wave diode rectifying circuit substantially as hereinbefore described with reference to and as illustrated in Figure 2 of the accompanying drawings.

8. An analogue to digital converter comprising at least one circuit .-.according to any one of the preceding claims.

9. An analogue to digital convertor according to claim 8 as dependent upon claim 6 comprising a plurality of said circuits connected in cascade and in which the said output signal from each amplifier stage is representative of the digital value of the stage.

10. An analogue to digital convertor substantially as hereinbefore described with reference to and as illustrated in Figure 3 of the accompanying drawings.