GB1589443A

GB1589443A - Electrical communication system

Info

Publication number: GB1589443A
Application number: GB4240277A
Authority: GB
Original assignee: Ford Motor Co Ltd; Ford Motor Co
Current assignee: Ford Motor Co Ltd; Ford Motor Co
Priority date: 1977-10-12
Filing date: 1977-10-12
Publication date: 1981-05-13
Also published as: CA1112327A

Description

(54) ELECTRICAL COMMUNICATION SYSTEM (71) We, FORD MOTOR COMPANY LIM ITED, of Eagle Way, Brentwood, Essex CM13 3BW, a British Company, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement: This invention relates to a multiplex electrical communication system and is particularly, but not exclusively, intended for use in motor vehicles.

Conventional practice in motor vehicles has been to provide each powered device (light, horn, windscreen wiper motor, etc.) with its own power lead and associated driver's control switch, and to provide a number of warning and indicating instruments (fuel gauge, tachometer, oil pressure warning, etc.) each connected to an appropriate sensor by separate wiring. This gives rise to wiring looms of considerable complexity and cost, and which have a poor reliability. It is also necessary to fabricate and stock different wiring harnesses for each model of vehicle.

There have hitherto been a considerable number of proposals to overcome these problems by using a common channel interconnecting all electrically powered devices and monitoring devices with a central control station, information being passed along the channel by multiplexing techniques.

None of these proposals has yet been put into practice in volume vehicle production, principally for reasons of cost, and/or complexity. The factors which can be identified as necessary for a commercially viable system are: (a) the system must be mechanically simple and robust.

(b) the number of different components required must be kept to a minimum.

(c) the system must be sufficiently fast to maintain information such as road and engine speed sufficiently up to date in real time for the purpose of the driver.

(d) it must be possible to control at least 50 functions and to receive information from a similar number of sensors.

(e) there must be signal security which prevents spurious signals caused by interference effecting erroneous operation of controlled devices.

Of the systems previously proposed, some have been too slow or have too small a channel capacity to be suitable for use in vehicles, while others have achieved the required speed and channel capacity by using long trains of pulses at high repetition rates which requires the use of high frequency components with attendant expense. Other systems are unsuitable because they require a number of signal-carrying conductors, which increases cost and the risk of incorrect connection.

The invention accordingly seeks to provide a communication system which overcomes or reduces the disadvantages of the prior art proposals.

According to the invention there is provided a communication system having a signal bus, a master station, and a plurality of peripheral stations controlled by signals transmitted on the signal bus by the master station in a time division multiplex manner, the signals being transmitted cyclically in information frames with the information frame for each peripheral station occupying a given position in the cycle; a peripheral station apparatus comprising: gating means for coupling signals from the signal bus to one or more outputs in response to an enable signal; address decoding means adapted to identify the information frame for that station and to generate said enable signal in response thereto, the address decoding means including address setting means and a counter for counting information frames; verifying means interposed between the gating means and the output(s), the verifying means being arranged to store each gated signal, compare it with the corresponding next-received signal, and pass the original signal when the compared signals agree; and syne detector means arranged to detect synchronising (sync) signals on the signal bus, to compare the occurrence of said syne signals with the count held in said counter, and to disable the verifying means on detecting a lack of synchronism between the bus signals and the address decoding means.

Figure 2 is a detailed circuit diagram of one of the peripheral stations of Figure 1; Figure 3 shows a typical pulse train used in the apparatus of Figures 1 and 2; Figure 4 is a perspective view of a peripheral station in position on a bus member of the system; Figure 4a is a plan view, partly in section of the bus and peripheral station of Figure 4 with a top cover of the peripheral station removed; Figure 5 is a more detailed circuit diagram of part of the circuit of Figure 2; and Referring to Figure 1, the system has a power bus 10 in circuit with a storage battery 12. The power bus 10 is formed by a single conductor, the return circuit being provided via vehicle earth. A signal bus 14 is associated with the power bus 10, and also comprises a single conductor. The buses 10 and 14 are molded into a single insulating sheath 16 (Fig. 4) to form a unitary bus member which may readily be passed around a vehicle in a convenient route.

A master station 18 is connected to the buses 10 and 14, and to a vehicle control panel 20. Sixteen peripheral stations 22 are each connected to the buses 10 and 14. Each peripheral unit is connected by external leads to up to four controlled devices and up to four sensors; by way of example, one of the stations 22 in Figure 1 is shown connected to a headlight HL a direction indicator light DL, a temperature sensor TS and an oil pressure sensor PS. The connections of the other peripheral stations 22 are not shown, for clarity of the drawing.

The control panel 20 contains the usual control switches, warning lights, and instruments for use by the driver. The master station 18 scans the driver-actuated controls in a sequential manner and transmits an addressed signal which is acted upon by the appropriate peripheral station to activate or de-activate the desired device. At the same time, the outputs of sensors for functions such as oil pressure, coolant temperature, road speed etc. are coupled to the corresponding peripheral stations 22 and are thence repetitively called up by the master station 18, decoded, and displayed as appropriate on warning lights and instruments on the control panel 20.

The manner in which information handling is accomplished in the peripheral stations will now be discussed with reference to Figures 2 and 3.

Figure 3 shows the voltage level of a typical signal on the signal bus 14. The voltage at any instant is controlled at one of four levels, labelled A, B, C and D. Level A is suitably tied to the vehicle earth (ground) voltage. The master station 18 includes a clock circuit which cyclically generates synchronising (sync) and clock pulses. Sync pulses are set at level D and occur once per complete cycle (in this case 16 frames). Clock pulses are at level C and subdivide each frame into equal time slots, in this embodiment eight in number. Information is conveyed by controlling the signals within the time slots at levels A and B.

Turning to Figure 2, the circuit of a single peripheral station 22 is shown. It should be noted that the stations 22 have identical circuitry. This simplifies stockholding and installation and assists in reducing costs.

The circuit of Figure 2 has an input at 24 from the signal bus 14.

The power bus 10 may be connected to powered devices via parallel bistable gates 26 controlled by the remainder of the circuit.

The signal input at 24 passes to an amplitude discriminator 28 which has four outputs enabled respectively by signal levels C, D, (C or D) and (B or C). The receipt of a signal at level (C or D), i.e. a sync or clock pulse, causes an output pulse to be passed to an eight-way selector 30 which in turn passes every eighth pulse to a 4-bit counter 32.

The bits of the counter 32 are connected in parallel to a decode circuit 34. The decode circuit 34 has an address set externally, over leads 36, as described in our copending British Patent Application No. 42403/77 (Serial No. 1,589,444).

It will thus be seen that the counter 32 is incremented once for every eight clock (and sync) pulses, i.e. once per frame. When the count held by the counter 32 is that set via the leads 36, the decode circuit generates an output on line 38 for eight time slot periods, i.e. for one frame period. Line 38 is connected in parallel to gates G1--G8. These gates are also connected to sequential outputs of the eight-way selector 30, each output being enabled for one time slot period. Thus, when the particular station 22 receives an information frame corresponding to the address code set, the gates G1--G8 are sequentially enabled each for one time slot.

Received signals of level (B or C) are passed by the amplitude discriminator to a pulse width discriminator 40 whose function is to separate the clock pulses, which are of lesser duration, from time slot information.

Signals at level B are passed by output 42 to gates G1--G4 in parallel and are then used, via a command and verify circuit 44 to be described, to enable the gates 26. Ignoring for the moment the command and verify circuit 44, the operation is thus that the controlled devices connected to terminals 1, 2, 3, 4 are turned on by B-level signals in time slots 1, 2, 3, 4 respectively and are turned of by A-level signals in these slots. Similarly, inputs from sensors connected to terminals 5, 6, 7, 8 are sequentially gated by gates G5--G8. Such inputs may be either on/off or analog. The gated sensor signals pass to a pulse width modulator 46 which generates an output signal onto the signal bus 14 during time slots 5, 6, 7, 8. A typical set of output signals is shown in Fig. 3. Time slots 6 and 7 are occupied by tell-back signals monitoring the condition of devices controlled by the signals in time slots 2 and 3.

Slot 6 represets an "off" tell-back signal and is wholly occupied by level A signal. Slot 7 represents "on" and is wholly occupied by level B signal. Slots 5 and 8 are exemplarily shown as carrying analog coolant tem- perature and oil pressure signals. These are pulse width modulated, the fraction of the time slot occupied at level B representing a fraction of a predetermined full scale deflection for that signal. The timing of the output of the pulse width modulator 46 is synchronised with the time slots 5-8 by C-level or clock pulses switched by the amplitude discriminator over line 48.

The purpose of the command and verify circuit 44 is to provide signal security. This circuit operates in conjunction with a sync detector 50 connected to receive sync pulses from the amplitude discriminator 28. The sync detector 50 is also connected to the 4bit counter 32 by a line 52. On receipt of the sync pulse, the counter 32 should reset to zero, and the counter is so constructed that on resetting it transmits a pulse over line 52 to the sync detector 50. If both pulses arrive simultaneously, the sync detector emits a gating pulse on line 54 to the command and verify circuit 44.

The command and verify circuit comprises four channels, each connected between one of the gates G1--G4 and the respective output terminals 1-4. One such channel is shown in Fig. 5. The signal from gate G is applied over line 55 and is held in a resettable store 56, which may for instance be a bistable multivibrator. The stored signal is compared with the next signal gated to that channel by a comparator 58. If the two values agree, an enable signal passes by line 60 to a gate 62.

The gate 62 is also connected to receive the gating pulse on line 54 from the sync detector 50, an to receive signals over line 64 from the pulse width discriminator 40. The first of these is provided to block execution of commands where there is a failure of syn chronism in the system, and the second to ensure that a command signal is passed only during a suitable time slot. Thus a command signal will not be passed by the circuit 44 to the controlled device unless (1) the same signal is received- twice in- succession and (2) the address decode is operating correctly in synchronism with the master station. The first of these is principally a safeguard against a signal which is correctly timed but in which a positive pulse is dropped, thile the second is of particular use in dealing with the case where an interference-induced spike appears on the signal bus and produces lack of synchronism. If either of these conditions is not met, the signal to the appropriate gate 26 is blocked and the controlled device continues in its pre-existing state.

The sync detector 50 is also connected to the 4-b-it counter 32 to reset the latter n receipt of a sync pulse. (If the system is correctly in synchronism, the counter 32 will also be recycling to zero of its owh accord at the same time).

It will be seen that this embodiment is capable of controlling 64 functions and of monitoring 64 sensors. Suitably, each information frame occupies 8 ms, giving a total cycle time of 128 ms. Since two consecutive identical signals are required to actuate controlled devices, the maximum delay in switching on or off is 256 ms. Readouts to the driver are updated every 128 ms. These speeds are sufficiently fast to be practically instantaneous from the driver's point of view while not requiring high pulse repetition rates.

Turning to Figures 4 and 4a, one possible physical form of peripheral station is shown.

The circuitry is encapsulated in a housing 64 which is formed with a recess dimensioned to accommodate the sheath 16. A cover 65 is hinged at 66 to the housing 64 and may be locked shut by spring steel arms 67. Connecting blades 68 extend from the housing 64 to effect connection with the buses 10 and 14. In use, slots for the blades 68 are preformed at suitable locations on the sheath 16 and the bus member is positioned in the vehicle. At each station, a housing 64 is arranged in a position to receive the bus member with the connecting blades in contact with the buses 10 and 14. The housing is then secured to a vehicle body panel (not shown) as by self-tapping screws 69 passed through a metal strap 70 secured to the housing 64 and supporting the arms 67. The strap 70 and screws 69 suitably act as an electrical ground connector and heat sink. When the cover 65 is closed, the peripheral station also acts as a retainer for the bus member. As described in more detail in our copending patent application No 42403/77 (Serial No 1,589,444), the station is connected to the sensors and con sumers by a printed circuit member 71 held in the housing by pins 72 passing through holds 73 in the member 71. The address setting means for the station comprises contacts 75, connected to the decode circuit 34, which engage conductors 77 on the mem- ber 71. The conductbrs are interconnected at 79 so that the address for the station can be identified by punching or drilling through selected strips 77 between the position of their respective contact with the contacts 75 and the interconnection 79.

The invention thus provides a peripheral station including a verifying means which nullifies the effect of failures in signal transmission, not only those where signal pulses are lost or distorted but also those due to interference causing spurious pulses or lengthening of the pulse train.

It will be appreciated that modifications may be made to the embodiment described within the scope of the invention, as defined in the claims. For instance, the input on the line 64 to the command and verify circuit 44 may be taken directly from a suitable output of the amplitude discriminator rather than being derived by pulse width discrimination.

The four-bit counter 32 could be fed directly by a "D" output of the amplitude discriminator. The inputs from sensors may be omitted, together with the corresponding gates and the modulator 46, where only a control function is desired.

Further features of the system disclosed herein are described and claimed in our copending British Patent Applications Nos 42403/77 and 42404/77 (Serial Nos 1,589,444 and 1,589,445).

WHAT WE CLAIM IS:- 1. For use in a communication systcm having a signal bus, a master station, and a plurality of peripheral stations controlled by signals transmitted on the signal bus by the master station in a time division multiplex manner, the signals being transmitted cyclically in information frames with the information frame for each peripheral station occupying a given position in the cycle; a peripheral station apparatus comprising: gating means for coupling signals from the signal bus to one or more outputs in response to an enable signal; address decoding means adapted to identify the information frame for that station and to generate said enable signal in response thereto, the address decoding means ineluding address setting means and a counter for counting information frames; verifying means interposed between the gating means and the output(s), the verifying means being arranged to store each gated signal, compare it with the corresponding next-received signal, and pass the orginal signal when the compared signals agree; and syne detector means arranged to detect synebronising (sync) signals on the signal bus, to compare the occurrence of said syne signals with the count held in said counter, and to disable the verifying means on detecting a lack of synchronism between the bus signals and the address decoding means.

2. Apparatus according to claim 1, including an amplitude discriminator for connection to the signal bus, the sync detector means being coupled to receive sync signals from the amplitude discriminator.

3. Apparatus according to claim 2, in which said counter is arranged to receive one pulse per frame from the amplitude discriminator.

4. Apparatus according to any preceding claim, in which there are n outputs and the gating means comprises n gates connected to receive signals from the signal bus in parallel, each gate being enabled by the simultaneous occurrence of signals at two enable inputs one of which is connected to receive said enable signal from the address decoding means, and including means for applying signals to the other enable inputs of the gates sequentially during the information frame for the station.

5. Apparatus according to any preceding claim, in which the verifying means comprises, between the gating means and each output, a store having an input connected to the gating means and an output; a comparator having a first input connected to the store output, a second input connected to the gating means, and an output enabled by identity at the inputs; and a gate having a controlled path connected between said gating means and the respective apparatus output, said controlled path being enabled by the simultaneous occurence of signals at two enable inputs of the gate, one said enable input being connected to the comparator output and the other to said sync detector means.

6. Apparatus according to claim 5, in which the or each verifying means gate has a further enable input connected to receive an enable signal at a predetermined time within the information frame for the station.

7. Apparatus according to any preceding claim, in which said address setting means comprises contacts for receiving an external member having interconnected conductors identifying an address.

8. Apparatus according to any preceding claim, including switching means adapted for connection to a power bus and arranged to be enabled by the output signals passed by said verifying means.

9. Apparatus according to any preceding claim further including one or more signal inputs for connection to respective sensors, a modulator adapted for connection to the signal bus, and further gating means arrange to connect the or each said signal input to the modulator at a predetermined time in the information frame.

10. Apparatus according to claim 9, in which the modulator is a pulse width modulator.

11. A peripheral station apparatus as

**WARNING** end of DESC field may overlap start of CLMS **.

Claims

**WARNING** start of CLMS field may overlap end of DESC **. at 79 so that the address for the station can be identified by punching or drilling through selected strips 77 between the position of their respective contact with the contacts 75 and the interconnection 79. The invention thus provides a peripheral station including a verifying means which nullifies the effect of failures in signal transmission, not only those where signal pulses are lost or distorted but also those due to interference causing spurious pulses or lengthening of the pulse train. It will be appreciated that modifications may be made to the embodiment described within the scope of the invention, as defined in the claims. For instance, the input on the line 64 to the command and verify circuit 44 may be taken directly from a suitable output of the amplitude discriminator rather than being derived by pulse width discrimination. The four-bit counter 32 could be fed directly by a "D" output of the amplitude discriminator. The inputs from sensors may be omitted, together with the corresponding gates and the modulator 46, where only a control function is desired. Further features of the system disclosed herein are described and claimed in our copending British Patent Applications Nos 42403/77 and 42404/77 (Serial Nos 1,589,444 and 1,589,445). WHAT WE CLAIM IS:-

1. For use in a communication systcm having a signal bus, a master station, and a plurality of peripheral stations controlled by signals transmitted on the signal bus by the master station in a time division multiplex manner, the signals being transmitted cyclically in information frames with the information frame for each peripheral station occupying a given position in the cycle; a peripheral station apparatus comprising: gating means for coupling signals from the signal bus to one or more outputs in response to an enable signal; address decoding means adapted to identify the information frame for that station and to generate said enable signal in response thereto, the address decoding means ineluding address setting means and a counter for counting information frames; verifying means interposed between the gating means and the output(s), the verifying means being arranged to store each gated signal, compare it with the corresponding next-received signal, and pass the orginal signal when the compared signals agree; and syne detector means arranged to detect synebronising (sync) signals on the signal bus, to compare the occurrence of said syne signals with the count held in said counter, and to disable the verifying means on detecting a lack of synchronism between the bus signals and the address decoding means.

11. A peripheral station apparatus as

claimed in claim 1 and substantially as hereinbefore described with reference to the accompanying drawings.

12. A communication system comprising a signal bus, a control station connected to the signal bus for transmitting thereon control signals in a time division multiplex manner, and a plurality of peripheral stations in accordance with any preceding claim each connected to the signal bus.

13. A motor vehicle including the system of claim 12.