GB1589445A - Communication system for electronic transmission of information - Google Patents

Description

(54) COMMUNICATION SYSTEM FOR ELECTRONIC TRANSMISSION OF INFORMATION (71) We, FORD MOTOR COMPANY LIMITED, of Eagle Way, Brentwood, Essex CM13 3BW, a British Company, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement: This invention relates to a multiplex communication system for the transmission of information and is particularly, but not exclusively, intended for use in motor vehicles.

Conventional practice in motor vehicles has been to provide each powered device (light, horn, windscreen wiper motor, etc.) with its own power lead and associated driver's control switch, and to provide a number of warning and indicating instruments (fuel gauge, tachometer, oil pressure warning, etc.) each connected to an appropriate sensor by separate wiring. This gives rise to wiring looms of considerable complexity and cost, and which have a poor reliability. It is also necessarv to fabricate and stock different wiring harnesses for each model of vehicle.

There have hitherto been a considerable number of proposals to overcome these problems by using a common channel interconnecting all electrically powered devices and monitoring devices with a centraI control station, information being passed along the chanel by multiplexing techniques. None of these proposals has yet been put into practice in volume vehicle production, principally for reasons of cost, and/or complexity. The factors which can be identified as necessary for a commercially viable sys tem are: (a) the system must be mechanically simple and robust.

(b) the number of different com ponents required must be kept to a mini mum.

(c) the system must be sufficiently fast to maintain information such as road and engine speed sufficiently up to date in real time for the purposes of the driver.

(d) it must be possible to control at least 50 functions and to receive informa tion from a similar number of sensors.

(e) there must be signal security which prevents spurious signals caused by interference effecting erroneous operation of controlled devices.

Of the systems previously proposed, some have been too slow or have too small a channel capacity to be suitable for use in vehicles, while others have achieved the required speed and channel capacity by using long trains of pulses at high repetition rates which requires the use of high frequency components with attendant expense.

Other systems are unsuitable because they require a number of signal-carrying conductors, which increases cost and the risk of incorrect connection.

The invention accordingly seeks to provide a communication system which overcomes or reduces the disadvantages of the prior art proposals.

According to the invention there is provided a system for the communication of information comprising a signal bus, a plurality of peripheral stations connected to the signal bus, and a control station arranged to transmit signals on the signal bus in sequential cycles, each cycle comprising pulses on four discrete signal levels and incIuding a synchronisation pulse at a first level, and clock pulses at a second level dividing the cycle into a fixed number of time slots, the signal between the clock pulses in each time slot being at either a third level or a fourth level in accordance with information transmitted between thecontrol station and the peripheral stations.

An embodiment of the present invention will now be described, by way of example, with reference to the accompanying drawings, in which: Figure I is a block diagram of an information handling system fbr use in a motor vehicle; Figure 2 is a detailed circuit diagram of one of the peripheral stations of Figure l; Figure 3 shows a typical pulse train used in the apparatus of Figures 1 and 2; Figure 4 is a perspective view of a peripheral station in position on a bus member of the system; Figure 4a is a plan view, partly in section of the bus and peripheral station of Figure 4 with a top cover of the peripheral station removed; Figure 5 is a more detailed circuit diagram of part of the circuit of Figure 2; and Referring to Figure 1, the system has a power bus 10 in circuit with a storage battery 12. The power bus 10 is formed by a single conductor, the return circuit being provided via vehicle earth. A signal bus 14 is associated with the power bus 10, and also comprises a single conductor. The buses 10 and 14 are molded into a single insulating sheath 16 (Fig. 4) to form a unitary bus member which may readily be passed around a vehicle in a convenient route.

A master station 18 is connected to the buses 10 and 14, and to a vehicle control panel 20. Sixteen peripheral stations 22 are each connected to the buses 10 and 14. Each peripheral unit is connected by external leads to up to four controlled devices and up to four sensors; by way of example, one of the stations 22 in Figure 1 is shown connected to a headlight HL, a direction indicator light DL, a temperature sensor TS and an oil pressure sensor PS. The connections of the other peripheral stations 22 are not shown, for clarity of the drawing.

The control panel 20 contains the usual control switches. warning lights, and instruments for use by the driver. The master station 18 scans the driver-actuated controls in a sequential manner and transmits an addressed signal which is acted upon by the appropriate peripheral station to activate or de-aetivate the desired device. At the same time. the outputs of sensors for functions such as oil pressure, coolant temperature, road speed etc. are couplcd to the corresponding peripheral stations 22 and are thence repetitively called up by the master station 18, decoded, and displayed as appropriate on warning lights and instruments on the control panel 20.

The manner in which information handling is accomplished in the peripheral stations will now be discussed with reference to Figures 2 and 3.

Figure 3 shows the voltage level of a typical signal on the signal bus 14. The voltage at any instant is controlled at one of four levels, labelled A, B, C and D. Level A is suitably tied to the vehicle earth (ground) voltage. The master station 18 includes a clock circuit which cyclically generates - synchronising (sync) and clock pulses.

Sync pulses are set at level D and occur once per complete cycle (in this case 16 frames). Clock pulses are at level C and subdivide each frame into equal time slots, in this embodiment eight in number. Information is conveyed by controlling the signals within the time slots at levels A and B.

Turning to Figure 2, the circuit of a single pheripheral station 22 is shown. It should be noted that the stations 22 have identical circuitry. This simplifies stockholding and installation and assists in reducing costs. The circuit of Figure 2 has an input at 24 from the signal bus 14. The power bus 10 may be connected to powered devices via parallel bistable gates 26 controlled by the remainder of the circuit. The signal input at 24 passes to an amplitude discriminator 28 which has four outputs enabled respectively by signal levels C, D (C or D) and (B or C). The receipt of a signal at level (C or D), i.e. a sync or clock pulse, causes an output pulse to be passed to an eight-way selector 30 which in turn passes every eighth pulse to a 4-bit counter 32. The bits of the counter 32 are connected in parallel to a decode circuit 34. The decode circuit 34 has an address set externally over leads 36, as described in detail in our copending British Patent Application No. 42403/77 (Serial No.

1589444).

It will thus be seen that the counter 32 is incremented once for every eight clock (and sync) pulses, i.e. once per frame. When the count held by the counter 32 is that set via the leads 36, the decode circuit generates an output on line 38 for eight time slot periods, i.e. for one frame period. Line 38 is connected in parallel to gates G1--G8.

These gates are also connected to sequential outputs of the eight-way selector 30, each output being enabled for one time slot period. Thus, when the particular station 22 receives an information frame corresponding to the address code set, the gates G1--G8 are sequentially enabled each for one time slot.

Received signals of level (B or C) are passed by the amplitude discriminator to a pulse width discriminator 40 whose function is to separate the clock pulses, which are of lesser duration, from time slot information.

Signals at level B are passed by output 42 to gates G1--G4 in parallel and are then used, via a command and verify circuit 44 to be described, to enable the gates 26. Ignoring for the moment the command and verify circuit 44, the operation is thus that the controlled devices connected to terminals 1, 2, 3, 4 are turned on by B-level signals in time slots 1, 2, 3, 4 respectively and are turned of by A-levd signals in these slots. Similarly, inputs from sensors connected to terminals 5, 6, 7, 8 are sequentially gated by gates G5--C8. Such inputs may be either on/off or analog. The gated sensor signals pass to a pulse width modulator 46 which generates an output signal onto the signal bus 14 during time slots 5, 6, 7, 8. A typical set of output signals is shown in Fig. 3. Time slots 6 and 7 are occupied by tell-back signals monitoring the condition of devices controlled by the signals in time slots 2 and 3.

Slot 6 represents an "off" tell-back signal and is wholly occupied by level A signal.

Slot 7 represents "on" and is wholly occupied by level B signal. Slots 5 and 8 are exemplarily shown as carrying analog coolant temperature and oil pressure signals.

These are pulse width modulated, the fraction of the time slot occupied at level B representing a fraction of a predetermined full scale deflection for that signal. The timing of the output of the pulse width modulator 46 is synchronised with the time slots 5-8 by C-level or clock pulses switched by the amplitude discriminator over line 48.

The purpose of the command and verify circuit 44 is to provide signal security. This circuit operates in conjunction with a sync detector 50 connected to receive sync pulses from the amplitude discriminator 28. The sync detector 50 is also connected to the 4-bit counter 32 by a line 52. On receipt of the sync pulse, the counter 32 should reset to zero, and the counter is so constructed that on resetting it transmits a pulse over line 52 to the sync detector 50. If both pulses arrive simultaneously, the sync detector emits a gating pulse on line 54 to the command and verify circuit 44.

The command and verify circuit comprises four channels, each connected between one of the gates G1--G4 and the respective output terminals I4. One such channel is shown in Fig. 5. The signal from gate G is applied over line 55 and is held in a resettable store 56, which may for instance be a bistable multivibrator. The stored signal is compared with the next signal gated to that channel by a comparator 58. If the two values agree, an enable signal passes by line 60 to a gate 62. The gate 62 is also connected to receive the gating pulse on line 54 from the sync detector 50, and to receive signals over line 164 from the pulse width discri mix'atop 40. The first of these is provided to block execution of commands where there is a failure of synchronism in the system, and the second to esure that a command signal is passed only during a suitable time slot. Thus a command signal will not be passed by the circuit 44 to the controlled device unless (1) the same signal is received twice in succession and (2) the address decode is operating correctly in synchronism with the master station. The first of these is principally a safeguard against a signal which is correctly timed but in which a positive pulse is dropped, while the second is of particular use in dealing with the case where an interference-induced spike appears on the signal bus and produces lack of synchronism. If either of these conditions is not met, the signal to the appropriate gate 26 is blocked and the controlled device continues in its pre-existing state.

The sync detector 50 is also connected to the 4-bit counter 32 to reset the latter on receipt of a sync pulse. (If the system is correctly in synchronism, the counter 32 will also be recycling to zero of its own accord at the same time.) It will be seen that this embodiment is capable of controlling 64 functions and of monitoring 64 sensors. Suitably, each information frame occupies 8 ms, giving a total cycle time of 128 ms. Since two consecutive identical signals are required to actuate controlled devices, the maximum delay in switching on or off is 256 ms. Readouts to the driver are updated every 128 ms. These speeds are sufficiently fast to be practically instantaneous from the driver's point of view while not requiring high pulse repetition rates.

Turning to Figures 4 and 4a, one possible physical form of peripheral station is shown.

The circuitry is encapsulated in a housing 164 which is formed with a recess dimensioned to accommodate the sheath 16. A cover 65 is hinged at 66 to the housing 64 and may be locked shut by spring steel arms 67. Connecting blades 68 extend from the housing 164 to effect connection with the buses 10 and 14. In use, slots for the blades 68 are preformed at suitable locations on the sheath 16 and the bus member is positioned in the vehicle. At each station, a housing 164 is arranged in a position to receive the bus member with the connecting blades in contact with the buses 10 and 14. The housing is then secured to a vehicle body panel (not shown) as by self-tapping screws 69 passed through a metal strap 70 secured to the housing 164 and supporting the arms 67. The strap 70 and screws 69 suitably act as an electrical ground connector and heat sink. When the cover 65 is closed, the peripheral station also acts as a retainer for the bus member.

The four-level pulse format of the present invention permits the required amount of information to be carried without the use of unduly long pulse trains and/or repetition rates. Moreover, all signal detection can be based on ratios rather than absolute values, and control of supply voltages is therefore not critical. At the same time, the invention permits the use of relatively simple peripheral stations, which may all be identical.

Further features of the system disclosed herein are described and claimed in our copending British Patent Applications Nos.

42402/77 and 42403/77 (Serial Nos.

1589443 and 1589444).

Claims (11)

WHAT WE CLAIM IS:-

1. A system for the communication of information comprising a signal bus, a plurality of peripheral stations connected to the signal bus, and a control station arranged to transmit signals on the signal bus in sequential cycles, each cycle comprising pulses on four discrete signal levels and including a synchronisation pulse at a first level, and clock pulses at a second level dividing the cycle into a fixed number of time slots, a signal between the clock pulses in each time slot being at either a third or a fourth level in accordance with information transmitted between the control station and the peripheral stations.

2. A system according to claim 1, in which each peripheral station includes means for counting the clock pulses in each cycle, means for setting a station address, and signal gating means arranged to be enabled during a frame of time slots constituting part of the cycle when the counting means has reached a count corresponding to an address set by the address setting means.

3. A system according to claim 2, in which each cycle comprises a plurality of frames of n time slots, each frame being associated with a respective peripheral station, each peripheral station is adapted for connection to n external devices, and said signal gating means comprises n gates each enabled for a respective time slot of its associated frame.

4. A system according to claim 3, in which n is eight.

5. A system according to any of claims 2 to 4, in which each peripheral station is connected to a common power bus, and each peripheral station includes power gates for connecting the power bus to external devices in response to signals in respective time slots of the frame for that station.

6. A system according to claim 5, in which the number of power gates in each peripheral station is less than the number of time slots in the frame, the peripheral station being adapted to transmit signals from other external devices to the control station during the remaining time slots of the frame.

7. A system according to claim 6, in which each peripheral station includes a pulse width modulator coupled to the signal bus, and gating means arranged to couple said other external devices to the pulse width modulator during respective time slots.

8. A system according to claim 7, in which each peripheral station includes an amplitude discriminator having an input connected to the signal bus and an output connected to the pulse width modulator to synchronise the latter with the time slots.

9. A system according to any preceding claim, in which said fourth signal level is tied to the ground voltage of the system and the third, second and first signal levels are respectively higher voltage levels.

10. A system according to claim 1 and substantially as hereinbefore described with reference to the accompanying drawings.

11. A motor vehicle including a system in accordance with any preceding claim.