GB1585376A - Field effect transistor having an interdigital structure - Google Patents

Description

(54) A FIELD EFFECT TRANSISTOR HAVING AN INTERDIGITAL STRUCTURE (71) We, THOMSON-C SF, a French Body Corporate, of 173, Boulevard Haussmann 75008 Paris - France - do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement: This invention relates to field-effect transistors having an interdigital structure and to processes for producing these transistors. More particularly, the invention relates to fieldeffect transistors having their three electrodes (source, gate and drain) situated on the same surface of a semiconductor device and intended to operate at very high frequencies and relatively high power levels.

It is known that power transistors for very high frequency applications can only be produced in the form of interdigital structures.

Now, in the case of devices having their three electrodes distributed over the same surface of the substrate, the input or output connections of the electrodes necessarily cross in the common distribution plane. Although it is known how to produce crossings such as these by the interposition of insulating layers, the outcome is an increase in the complexity of construction, in addition to which troublesome parasitic capacitances are created between connections which is harmful and, in some cases, prohibitive in very high frequency applications.

It is also known how to construct interdigital structures having only two electrodes on one surface of the substrate with a common gate on the opposite surface. However, the control of a gate such as this lacks rapidity and, for this reason, is not always suitable in very high frequency applications.

The present invention obviates these various disadvantages.

According to the present invention there is provided a field effect transistor comprising a heavily doped semiconductor substrate carrying a first high resistivity semiconductor layer and an overlying semiconductor layer, a series of parallel grooves being etched in the surface of said layers to a depth sufficient to cut into said substrate, a first set of electrodes destined to be source or drain electrodes being deposited in the shape of metallizations in said grooves and on the margins of the same, a second and a third set of electrodes parallel to said grooves being deposited so as to form an interdigitated structure with said grooves, the electrodes of said second and third sets being interconnected by two metallizations each of them forming the spine of a comb having respectively the electrodes of one set as teeth, and the electrodes of said first set being interconnected by the substrate itself.

The invention will be better understood and other features thereof will become apparent from the following description in conjunction with the accompanying drawings wherein: Figure 1 is a sectional view illustrating a first embodiment of the invention.

Figures 2 and 3 are explanatory diagrams.

In the embodiment of Figure 1 there is formed on a silicon substrate 41 with P+ (or N+) - type doping layer of very high resistivity (F.R.) 42 (obtained for example by epitaxial growth without any doping in the case of silicon) and then an N-doped layer 43 (for example by a second epitaxial growth). Grooves 44 pe+netratirsg into the layers 42 and 43 up to the P (or ma material of the substrate 41 are then physically or chemically etched at the place intended for the drain (or source) electrode. A metallisation 45 covering the groove and overlapping the two sides is deposited at the same time as the deposition of other electrodes S, G. In the example selected, gate electrodes have been interposed both in the intervals SD and also in the intervals DS. An arrangement such as this enables the efficiency of the interdigital structure to be increased whilst doubling the current output of each electrode. This is because, in a series of transistors such as that illustrated in Figure 2, the roles of the source and drain may be reversed in alternate devices. This reversal is effected by connecting the electrodes selected as source to the so-called "source" feed terminal, i.e. the feed terminal giving the lowest d.c. voltage, and the electrodes selected as drains to the opposite feed terminal. Under these conditions, it is possible to simplify the structure shown in Figure 2 by merging the intermediate electrodes into pairs which gives the block diagram shown in Figure 3 which is no different from that shown in Figure 1 apart from the particular profile of the electrodes D in this latter case.

In this embodiment, all the drains have common conducive path formed by the P substrate. The P -substrate is provided with a metallisation 46 which is intended to facilitate the connection to the feed drain and to the load circuits.

In addition to the above-mentioned advantage of reducing the parasitic capacitance between electrode connections, the embodiment of Figure 1 has the following advantages: 1 - the almost complete suppression of the inherent inductance of the electrode interconnected by the substrate rendered conductive by doping, which is a particularly important advantage when the electrode in question is the source (contrary to the illustration in Figures 1); 2 - the reduction in the thermal resistance, particularly in the case of a substrate of gallium arsenide, the doping of this material reducing its resistivity; 3 - compatibility with methods of thinning down the substrate for reducing its thermal resistance.

WHAT WE CLAIM IS: 1. A field effect transistor comprising a heavily doped semiconductor substrate carrying a first high resistivity semiconductor layer and an overlying semiconductor layer, a series of parallel grooves being etched in the surface of said layers to a depth sufficient to cut into said substrate, a first set of electrodes destined to be source or drain electrodes being deposited in the shape of metallizations in said grooves and on the margins of the same, a second and a third set of electrodes parallel to said grooves being deposited so as to form an interdigital structure with said grooves, the electrodes of said second and third sets being interconnected by two metallizations each of them forming the spine of a comb having respectively the electrodes of one set as teeth, and the elctrodes of said first set being interconnected by the substrate itself.

2. A field effect transistor as claimed in claim 1, wherein the sequence of interdigitated electrodes is as follows: source, gate, drain, gate, source, gate, drain.

3. A field effect transistor as claimed in claim 1, wherein: the sequence of interdigitated electrodes is as follows: drain, gate, source, gate, drain, gate, source.

4. A field effect transistor substantially as herein before described with reference to the accompanying drawings.

**WARNING** end of DESC field may overlap start of CLMS **.

Claims (4)

**WARNING** start of CLMS field may overlap end of DESC **. shown in Figure 1 apart from the particular profile of the electrodes D in this latter case. In this embodiment, all the drains have common conducive path formed by the P substrate. The P -substrate is provided with a metallisation 46 which is intended to facilitate the connection to the feed drain and to the load circuits. In addition to the above-mentioned advantage of reducing the parasitic capacitance between electrode connections, the embodiment of Figure 1 has the following advantages:

1 - the almost complete suppression of the inherent inductance of the electrode interconnected by the substrate rendered conductive by doping, which is a particularly important advantage when the electrode in question is the source (contrary to the illustration in Figures 1);

2 - the reduction in the thermal resistance, particularly in the case of a substrate of gallium arsenide, the doping of this material reducing its resistivity;

3 - compatibility with methods of thinning down the substrate for reducing its thermal resistance.

WHAT WE CLAIM IS: 1. A field effect transistor comprising a heavily doped semiconductor substrate carrying a first high resistivity semiconductor layer and an overlying semiconductor layer, a series of parallel grooves being etched in the surface of said layers to a depth sufficient to cut into said substrate, a first set of electrodes destined to be source or drain electrodes being deposited in the shape of metallizations in said grooves and on the margins of the same, a second and a third set of electrodes parallel to said grooves being deposited so as to form an interdigital structure with said grooves, the electrodes of said second and third sets being interconnected by two metallizations each of them forming the spine of a comb having respectively the electrodes of one set as teeth, and the elctrodes of said first set being interconnected by the substrate itself.

2. A field effect transistor as claimed in claim 1, wherein the sequence of interdigitated electrodes is as follows: source, gate, drain, gate, source, gate, drain.

3. A field effect transistor as claimed in claim 1, wherein: the sequence of interdigitated electrodes is as follows: drain, gate, source, gate, drain, gate, source.

4. A field effect transistor substantially as herein before described with reference to the accompanying drawings.