GB1577786A

GB1577786A - Matrix circuit

Info

Publication number: GB1577786A
Application number: GB691077A
Authority: GB
Original assignee: Nippon Electric Co Ltd
Current assignee: NEC Corp
Priority date: 1977-02-18
Filing date: 1977-02-18
Publication date: 1980-10-29

Description

(54) MATRIX CIRCUIT (71) We, NIPPON ELECTRIC CO., LTD., a Company duly organized and existing under the laws of Japan and having its executive office at 33-1, Shiba Gochome, Minato-ku, Tokyo, Japan, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement:- This invention relates to a matrix circuit e.g. for cyclically driving, in an electrostatic recording device, a sequence of control electrodes, two at each instant. The invention is also applicable to a matrix having two outputs in each of succussive time slots.

An electrostatic recording device comprises a multiplicity of aligned stylus electrodes and a conductive member along the stylus electrodes to record an electrostatic image on a recording medium placed in an electrostatic field formed between the stylus electrodes and the conductive member. Usually, the conductive member is divided into a sequence of control electrodes. In order to cyclically drive the control electrodes at successive time slots, two consecutive ones in the sequence at each time slot, use is made of a matrix circuit to which this invention is applicable.

A matrix circuit generally comprises a plurality of matrix conductors, namely a plurality of row conductors and a plurality of column conductors crossing the row conductors without ohmic contact therewith to form matrix or cross points, and a plurality of cross-point elements adjacently of the respective cross points. For use in an electrostatic recording device comprising a sequence of control electrodes, the cross-point elements are assigned to the control electrodes in one-to-one correspondence. Only two of the cross-point elements are selected at each time slot to drive the two consecutive control electrodes.It is, however, inevitable with a conventional matrix circuit for general purposes that spurious cross-point elements in excess of two are undesirably selected at a certain time slot as will later be described with reference to one of several figures of the accompanying drawing.

Another conventional matrix circuit proposed specifically for an electrostatic recording device being dealt with is capable of avoiding the spurious selection. The proposed matrix circuit, however, is complicated in structure as will also be described hereunder with reference to another figure of the accompanying drawing. The operation is also complicated particularly when one of the two consecutive control electrodes that next follows in the sequence the other has to be continuously driven at the next succeeding time slot together with another of the control electrodes that next follows in the sequence the said one control electrode.

It is therefore an object of the present invention to provide a matrix circuit capable of readily driving via matrix cross-points a sequence of control electrodes e.g. of an electrostatic recording device at successive time slots, with two consecutive control electrodes in the sequence driven at each time slot and with one of the two consecutive control electrodes next following in the sequence the other continuously driven at the next succeeding time slot together with another control electrode next following in the sequence the said one control electrode.

It is another object of this invention to provide a matrix circuit of the type described, which is capable of reducing or avoiding spurious selection of the control electrodes and is yet simple in structure and operation.

It is a further object of this invention to provide a matrix circuit of the type described, wherein a pair of cross-point elements of the circuit is selected by only three selection signals.

According to the present invention there is provided a selection matrix comprising first and second sets of conductors, said first and second sets crossing each other's conductors to form cross-points to be selected and constituting output points of the matrix, and means to supply selection signals as inputs selectively to energize the conductors of the sets, wherein: said means to supply is arranged to select a pair of said cross-points in each one of a sequence of time slots; any two consecutive ones of said time slots has one but not the other of its selected cross-points in common; and the pair of cross-points selected in any one of the time slots involves energization of one conductor of either one of the first and second sets and two conductors of the other one of the first and second sets.

According to one detailed embodiment of this invention, there is provided a matrix circuit arrangement to be used in an electrostatic recording device comprising a multiplicity of aligned stylus electrodes and a sequence of control electrodes along the stylus electrodes. For cyclically driving the control electrodes at successive time slots, with two consecutive control electrodes in the sequence driven at each of the time slots and with one of the two consecutive control electrodes next following in the sequence the other of the two consecutive control electrodes is again driven during the next succeeding time slot together with a further control electrode next following in the sequence the said one of the two consecutive control electrodes.The matrix circuit comprises a plurality of conductors of a first set, a plurality of conductors of a second set successively crossing the first-set conductors without ohmic contact therewith to form a plurality of cross points, and a plurality of cross-point elements adjacently of the respective cross points in one-to-one correspondence with the control electrodes.

Each of the cross-point elements bridges one each of the first-set and second-set conductors crossing at one of the cross points that is adjacent to the said each cross-point element. The matrix circuit further comprises means for supplying selection signals selectively to the first-set and second-set conductors to select a pair of the cross-point elements at each of the time slots. The cross-point elements are for driving the corresponding control electrodes when selected. This means for supplying is so arranged that all of the cross-point elements to be selected as a pair in a time slot bridge one of the conductors of one of the first and second sets and two respective ones of the conductors of the other of the first and second sets.

Known arrangements, together with embodiments of the invention will now be described, by way of example, with reference to the accompanying drawings, in which: Fig. 1 schematically shows a generic electrostatic recording device in which a matrix circuit according to the present invention is to be used; Fig. 2 shows a conventional matrix circuit for general purposes; Fig. 3 shows another conventional matrix circuit specifically proposed for use in the recording device depicted in Fig. 1; Fig. 4 shows in principle a matrix circuit according to a first embodiment of this invention; Fig. 5 is a circuit diagram, partly shown by a block, of a matrix circuit according to the first embodiment; Fig. 6 is a circuit diagram of a distributor illustrated in Fig. 5 by the block; Fig. 7 is a time chart of several signals used in the distributor shown in Fig. 6;; Fig. 8 shows in principle a matrix circuit according to a second embodiment of this invention; Fig. 9 shows in principle a matrix circuit according to a third embodiment of this invention; and Fig. 10 shows again in principle a matrix circuit according to a fourth embodiment of this invention.

Referring to Fig. 1, a generic electrostatic recording device in which a matrix circuit according to the present invention is to be used comprises a multiplicity of aligned stylus electrodes (for example, 1680 in number) divided into first and other odd-numbered groups St, S,..., and S2n~, and second and other even-numbered groups S2, . . 53 and S2n and a plurality of signal input terminals divided into a first and second group T1 and T2.The first-group input terminals T1 are connected to the respective stylus electrodes of the odd-numbered groups S,--S,,~,, while the second-group input terminals T2, to the respective stylus electrodes of the even numbered groups S2S2n. The input terminals T, and T2 are cyclically supplied with signals to be recorded. The device further comprises a sequence of first, second, third .. ., 2n-th, and last or (2n+l)-th control electrodes C1, C2, C2, C2, and C2n+; along the stylus electrodes S,S2n. Despite the suffix 2n+ I for the last control electrode C2n+, in the sequence, the number of the control electrodes C,C2n+, may alternatively be an even number, such as sixteen, in which case the stylus electrodes are divided into an odd number of groups.

The control electrodes C,C2n+, are cyclically driven in successive time slots in the manner later described to electrostatically form in cooperation with the stylus electrodes S,S2n an electrostatic record on a recording medium (not shown) placed in an electrostatic field produced by the stylus electrodes SlS2n and the control electrodes C,C2n+, in compliance with the signals supplied to the input terminals T, and T2.

Further referring to Fig. 1, it may be pointed out here that the stylus electrodes of each of the groups S,S2n are associated with two consecutive ones in the sequence of the control electrodes C1C2n+1, such as the control electrodes C1 and C2 or C2 and C3. This is to compensate the otherwise unavoidable reduction of intensity of the electrostatic record at both ends of each control electrode.

Therefore, two consecutive control electrodes should be driven at each time slot.

Inasmuch as this device comprises a sequence of control electrodes C1C2n+1 and a pair of input terminal groups T1 and T2, reduction is possible in the number of amplifiers (not shown) for supplying the signals to be recorded to the stylus electrodes S,S2n. However, a matrix circuit is indispensible to cyclically drive the control electrodes C1C2n+1, two at each time slot, in synchronism with the signals supplied to the input terminals T1 and T2.In addition, one of the two consecutive control electrodes driven at each time slot that next follows in the sequence the other must be continuously driven in the next succeeding time slot by the matrix circuit together with another control electrode immediately following in the sequence the said one control electrode (one, the other, and another being, for example, identified as the control electrodes C2, C1, and C3, respectively). In other words, each control electrode must be driven for two successive time slots during one complete period of drive of the control electrodes C1C2n+1 except the first and last control electrodes C1 and C2n+1, each of which must be driven for only one time slot.

Referring to Fig. 2, description will be made of a conventional matrix circuit for general purposes for a better understanding of a matrix circuit according to this invention. In the illustrated example, the matrix circuit is a four by four matrix circuit and comprises first through fourth column conductors X1, X2, X3, and X4, first through fourth row conductors Y1, Y2,Y2, and Y4 successively crossing the first through fourth column conductors X1-X4 without ohmic contact with the column conductors X1-X4 to form sixteen cross points, and first through sixteenth crosspoint elements 1--16 adjacently of the respective cross points.Each cross-point element may comprise a series connection of a diode and a resistor as illustrated only for the first cross-point element 1. The series connection bridges one each of the column and row conductors, such as X, and Y1, crossing at one of the cross points that is adjacent to the series connection. The cross-point elements 1--16 are connected to the first through sixteenth control electrodes C1-C16, respectively, as indicated by an arrow again for the first cross-point element 1. The second through sixteenth cross-point elements 2-16 are symbolized by dots with the connection omitted.To cyclically drive the control electrodes 1--16, the two cross-point elements arranged along different column and row conductors, such as the crosspoint elements 4 and 5, must be selected at a certain time slot. In other words, selection signals must be supplied to a pair of row conductors Y and Y2 as well as to a pair of column conductors X4 and X1. It will, however, be seen that spurious cross-point elements I and 8 are also selected in this case.

Referring to Fig. 3, another conventional matrix circuit proposed to avoid the spurious selection comprises two additional column conductors X,' and X4,. In this matrix circuit, cross-point elements 1, 4, 9, and 12 are disposed in the manner depicted in the above-referenced Fig. 2. Cross-point elements 5 and 8 are placed adjacent to the cross points of the additional column conductors X,' and X4,, on the one hand, and the second row conductor Y2, on the other hand. Cross-point elements 13 and 16 are similarly arranged. As symbolized by small circles 1', 4', 5', 8', 9', 12', 13', and 16', no cross-point elements are disposed adjacent to the cross points of the first and fourth column conductors X, and X4 and the second and fourth row conductors Y2 and Y4. Although the spurious selection is avoided, the matrix circuit is inevitably complicated both in structure and operation.

Referring now to Fig. 4, description will be made of principles of a matrix circuit according to a first embodiment of this invention. In the depicted example, the matrix circuit comprises first through fourth column conductors X,--X,, first through fourth row conductors Y1-Y4, and cross-point elements 1 to 16 adjacently of the cross-points in one-to-one correspondence with the control electrodes C1-C16. The cross-point elements 1--4 bridge the first row conductor Y1 and the successive column conductors X1-X4 crossing the row conductor Y1 successively in one of senses along a predetermined one of the row conductors, such as Y1.The cross-point elements 5-8 bridge the second row conductor Y2 and the column conductors X4-X1 crossing the row conductor Y2 successively in the other of the senses. As a result, the cross-point elements 4 and 5 bridge the fourth column conductor X4 and the first and second row conductors Y1 and Y2. Likewise, the cross-point elements 9-12 or 13-16 are arranged along one of the row conductors Y3 and Y4 while the elements 8-9 and 12-13 are arranged along the first and fourth column conductors X1 and X4, respectively. In this manner, all of those pairs of the cross-point elements which are to be selected at a time slot are always disposed along only one of the row and column conductors X1-X4 and Y1-Y4.

With the arrangement of cross-point elements 1--16, it is possible always to select a pair by selection of only three row and column conductors and it is impossible to simultaneously select three or more elements by the three selected conductors.

From Fig. 4, it is understood that the first through sixteenth cross-point elements 1--16 corresponding to the first through sixteenth control electrbdes C1-C16 of the sequence are arranged along the respective cross-points so as to be traced with one stroke from a strating cross point for the cross-point element 1 to 16 to an end cross point for the element 16 or 1.More specifically, the first through sixteenth control electrodes C1-C10 correspond respectively to the first through fourth cross-point elements l bridging the first row conductor Y1 and the first through fourth conductors X1-X4 crossing the first row conductor Y1 successively in the abovementioned one sense, the fifth through eighth cross-point elements 5-8 bridging the second row conductor Y2 and the fourth through first column conductors X4-X1 crossing the second row conductor Y2 successively in the other sense, and the thirteenth through sixteenth cross-point elements 13-16 eventually bridging, in the example being illustrated, the fourth row conductor Y4 and the column conductors X1-X4 crossing the fourth row conductor Y4 successively in the one sense. In the manner known in the art, each cross-point element may comprise another similarly directed diode in place of the resistor. Alternatively, each crosspoint element may comprise another resistor in place of the depicted diode. The column conductors X1 -X4 need not be equal in number to the row conductors Y1-Y4. The column conductors X1-X4 need not be parallel to one another and may be arranged on a curved surface, this applies alternatively or also to the row conductors Y1-Y4.

Referring to Fig. 5, a matrix circuit 20 illustrated with reference to Fig. 4 comprises a series circuit of a diode D and a resistor R as each of the cross-point elements connected to the respective control electrodes C1-C16. The matrix circuit further comprises a driver circuit 30 and a distributor 40 to supply selection signals selectively to three of the column and row conductors X1-X4 and Y1-Y4 at each time slot.As will later be described, the distributor 40 has first output terminals Xa-Xd and second output terminals YaYd corresponding to the column and row conductors X1-X and Y1-Y4 and produces distributor output signals of a first and a second group at the first and second distributor output terminals XaXd and YaYd. The distributor output signals become logic "1" and "0" signals in a manner to be presently described with reference to Tables 1 and 2 given hereunder.The driver circuit 30 comprises transistor pairs Tor., Tr2; Tor2, Tr4; Tr5, Tre; and Tr, and Tra between the first distributor output terminals XaXd and the respective column conductors X1-X4, nearer to the cathods of the diodes D, and transistors Trg, Tor,,, Tor", and Tor'2 between the second distributor output terminals YaYd and the respective row conductors Y1-Y4, nearer to the diode anodes. The transistors Tr1-Tr12 are supplied with a voltage E.

Referring to Figs. 6 and 7, a distributor 40 for a matrix circuit described in conjunction with Fig. 4 comprises a counter circuit 41 having four stages a, b, c, and d for counting clock pulses CL supplied thereto from a clock input terminal 42 at a repetition period corresponding to the time slots to produce four-bit counter output signals from the respective stages a, b, c, and d which cyclically vary from logic "0000" to logic "1111" through logic "1000," "0100," "1100," ., . , and "0111" as given in Tables 1 and 2.The counter output signals except the most significant digit are supplied from the stages a, b, and c to two input terminals e and f of a first decoder 43 through a first logic circuit comprising and gates A1-A4, OR gates O, and 02, and inverters 1,13 connected as shown to convert the three less significant digit counter output signals into two-bit binary signals in a manner exemplified in Table 1. Responsive to the two-bit binary signals, the first decoder 43 produces first four-bit decorder output signals at its output terminals g, h, i, andj in a manner exemplified also in Table 1.The distributor 40 further comprises a second logic circuit comprising AND gates A5-A12 and OR gates O309 controlled by the counter output signal fo the most significant digit but one supplied from the stage c of the counter circuit 41 for converting the first decoder output signals into the first-group distributor output signals supplied to the first distributor output terminals XaXd as exemplified again in Table 1.

TABLE 1 counter outputs decoder inputs decoder outputs distributor outputs a b c e f g h i j Xa Xb Xc Xd 0 0 0 0 0 1 0 0 0 1 1 0 0 100 1 0 0 1 0 0 O 1 1 0 0 1 0 0 1 0 0 1 0 0 1 110 11 0 0 0 1 0 0 0 0 0 1 1 1 0 0 0 1 0 0 1 1 101 0 1 0 0 1 0 0 1 10 0 1 1 1 0 0 1 0 0 1 1 0 0 111 0 0 1 0 0 0 1 0 0 0 Further referring to Figs. 6 and 7, the most significant digit and the most significant digit but one of the counter output signals are supplied from the stages d and c to two input terminals k and I of a second decoder 44, which decodes the two or more significant digits into second four-bit counter output signals supplied to its output terminals m, n, o, and p in a manner exemplified in Table 2. The distributor 40 still further comprises a third logic circuit comprising AND gates A13-A15 and OR gates O,OO,2 controlled by those two of the first decoder output signals which are produced at the output terminals g and j of the first decoder 43 for converting the second decoder output signals into the second-group distributor output signals supplied to the second distributor output terminals YaYd as exemplified again in Table 2.With particular reference to Fig. 7, it will be understood that only two logic "1" signals are supplied to the second distributor output terminals coupled to two adjacent ones of the row conductors Y, and Y2, Y2 and Y3tor Y2 and Y4 while only one logic "1" signal is supplied to one first distributor output terminal coupled to one of the column conductors X1, X2, X3, or X4 on riving the fourth, eighth, twelfth, or sixteenth control electrode C4, C8, C,2, or C16 a the preceding one of the two consecutive control electrodes.On the other hand, only two logic "1" signals are supplied to the first distributor output terminals coupled to two adjacent ones of the column conductors Xl and X2, X2 and X3, or X2 and X4 at other time slots while only one logic "1" signal is supplied to one second distributor output terminal coupled to one of the row conductors Yl, Y2, Y3, or Y4. It will also be understood that the first-group distributor output signals supplied to the No. 1 and No. 4 first distributor output terminals Xa and Xd become logic "1" for only one time slot and for as long as three time slots as the case may be, while those supplied to the No. 2 and No. 3 first distributor output terminals Xb and X, for two time slots.

TABLE 2 counter outputs decoder outputs distributor outputs a b c d m n o p Ya Yb Yc Yd 0000 1 0 0 0 1 0 0 0 1100 1 0 0 0 1 1 0 0 O 0 1 0 0 1 0 0 0 1 0 0 1 1 1 0 0 1 0 0 0 1 1 0 O 0 0 1 0 0 1 0 0 0 1 0 1 1 0 0010 0 0 1 1 0 0 1 1 0 0 0 0 0 0 1 1111 0 0 0 1 0 0 0 1 Referring to Fig. 8, a four by four matrix circuit according to a second embodiment of this invention comprises the cross-point elements 1--16 arranged between each pair of the row conductors Y1-Y4 in a staggering manner while the seventh cross-point element 7 which reaches the fourth column conductor X4 and the following cross-point elements 8-10 are arranged along the fourth column conductor X4 until the tenth cross-point element 10 reaches the fourth row conductor Y4. It will readily be seen that a matrix circuit according to this embodiment should have an even number of row or column conductors.

Referring to Fig. 9, a four by four matrix circuit according to a third embodiment of this invention comprises the cross-point elements 1--16 passing through the cross points in an angled spiral manner.

Finally referring to Fig. 10, a four by four matrix circuit according to a fourth embodiment of this invention comprises the cross-point elements 1--16 arranged in a somewhat irregular manner wherein it is impossible to trace the cross-point elements 1--16 for the sequential control electrodes C1-C18 with a stroke. It should, however, be pointed out that two consecutively numbered cross-point elements, such as the cross-point elements 3 and 4 or 4 and 5, are arranged along a common matrix conductor.

It will now be easy for those skilled in the art to arrange the cross-point elements in a number of different manners and to design the distributor 40 suitable to the cross-point arrangement in consideration of an example taught herein with reference to Figs. 6 and 7. A matrix circuit according to this invention is applicable to an electrostatic recording device of any type provided that the device comprises a sequence of control electrodes along a multiplicity of aligned stylus electrodes.

WHAT WE CLAIM IS: 1. A selection matrix comprising first and second sets of conductors, said first and second sets crossing each other's conductors to form cross-points to be selected and constituting output points of the matrix, and means to supply selection signals as inputs selectively to energize the conductors of the sets, wherein: said means to supply is arranged to select a pair of said cross-points in each one of a sequence of time slots; any two consecutive ones of said time slots have one but not the other of its selected cross-points in common; and the pair of cross-points selected in any one of the time slots involves energization of one conductor of either one of the first and second sets and two conductors of the other one of the first and second sets.

2. A selection matrix as claimed in claim 1, wherein the means to supply is such that the sequence of two-at-a-time selection of the cross-points traces a rath along one conductor of one set in one sense, back along the next conductor of said one

**WARNING** end of DESC field may overlap start of CLMS **.

Claims

**WARNING** start of CLMS field may overlap end of DESC **. TABLE 2 counter outputs decoder outputs distributor outputs a b c d m n o p Ya Yb Yc Yd 0000 1 0 0 0 1 0 0 0 1100 1 0 0 0 1 1 0 0 O 0 1 0 0 1 0 0 0 1 0 0 1 1 1 0 0 1 0 0 0 1 1 0 O 0 0 1 0 0 1 0 0 0 1 0

1 1 0 0010 0 0 1 1 0 0 1 1 0 0 0 0 0 0 1 1111 0 0 0 1 0 0 0 1 Referring to Fig. 8, a four by four matrix circuit according to a second embodiment of this invention comprises the cross-point elements 1--16 arranged between each pair of the row conductors Y1-Y4 in a staggering manner while the seventh cross-point element 7 which reaches the fourth column conductor X4 and the following cross-point elements 8-10 are arranged along the fourth column conductor X4 until the tenth cross-point element 10 reaches the fourth row conductor Y4. It will readily be seen that a matrix circuit according to this embodiment should have an even number of row or column conductors.

set in the other sense, along the next conductor of the one set in said one sense, and so on in meandering fashion, each conductor being traced such as to cross all the conductors of the second set.

3. A selection matrix as claimed in claim I wherein the means to supply is such that the sequence of cross-points selected two-at-a-time traces a staggering path back and forth between two successive conductors of the first set, then a staggering path back and forth between the next two successive conductors of the first set, and so on, there being an even number of conductors in the first set.

4. A selection matrix as claimed in claim 1 being a rectangular matrix, wherein the means to supply is such that the sequence of cross-points selected two-at-a-time traces an angled spiral path through the rectangular matrix.

5. A selection matrix as claimed in claim 1 being a four-by-four rectangular matrix wherein the means to supply is such that the sequence of two-at-a-time selection of the cross-points traces an irregular path, but maintaining the feature that any two consecutive cross-points in the sequence are arranged along one conductor of the first set or the second set.

6. A matrix circuit arrangement when used in an electrostatic recording device comprising a multiplicity of aligned stylus electrodes and a sequence of control electrodes along said stylus electrodes, for cyclically driving said control electrodes at successive time slots, wherein two consecutive control electrodes in said sequence are driven during each of said time slots and wherein, for any two consecutive control electrodes, one of the two consecutive control electrodes next following in said sequence the other of the two consecutive control electrodes is again driven during the next succeeding time slot together with a further control electrode next following in said sequence said one of the two consecutive control electrodes, said matrix circuit comprising a plurality of conductors of a first set, a plurality of conductors of a second set successively crossing said first-set conductors without ohmic contact therewith to form a plurality of cross points, and a plurality of cross-point elements adjacently of the respective cross points in oneto-one correspondence with said control electrodes, each of said cross-point elements bridging one each of said first-set and second-set conductors crossing at one of said cross points adjacent to said each cross-point element, said matrix circuit further comprising means for supplying selection signals selectively toXsaid first-set and second-set conductors to select a pair of said cross-point elements at each of said time slots, said cross-point elements being for use in driving the corresponding control electrodes when selected, the means for supplying being such that any two of said cross-point elements to be selected as a pair in a time slot bridge one of the conductors of one of said first and second sets and two respective ones of the conductors of the other of said sets.

7. A matrix circuit arrangement as claimed in claim 6, said first-set conductors being at least three in number, wherein the sequence of the cross-point elements bridging a first of outermost ones of said first-set conductors and the second-set conductors successively crossing said first outermost first-set conductor in one of two senses along said first outermost one of said first-set conductors, of the crosspoint elements bridging the one of said first-set conductors that is next adjacent to said first outermost first-set conductor and the second-set conductors successively crossing said next adjacent one first-set conductor in the other of said two senses, and, if appropriate, so on, until the cross-point elements bridging the second of the outermost ones of said first-set conductors and the second-set conductors successively crossing said second outermost first-set conductor in said one or said other of said two senses according as the number of said first-set conductors is odd or even, respectively, is chosen to correspond to the sequence of the respective control electrodes to be driven.

8. A matrix circuit arrangement as claimed in claim 7, the conductors of each of said first and second sets being four in number, wherein said means comprises distributor means having four first and four second distributor output terminals for producing in response to clock pulses of a repetition period corresponding to said time slots distributor output signals of a first and a second group at said first and second distributor output terminals, respectively, said distributor output signals varying between two logic values, said means further comprising supply means for supplying said first-group and second-group distributor output signals with the logic values of the distributor output signals of a predetermined one of said first and second groups reversed to said first-set and second-set conductors, respectively, said distributor means comprising counter means for counting said clock pulses to produce counter output signals of four binary digits, said counter output signals varying cyclically from decimal zero to decimal fifteen, said distributor means further comprising logic means responsive to said counter output signals for successively in certain time slots giving one of said logic values to those two of said first-group distributor output signals which are supplied by said supply means to an adjacent pair of said first-set conductors while giving said one logic value to one of said second-group distributor output signals to one of said second-set conductors, and in other time slots, for giving said one logic value to one of said first-group distributor output signals that is supplied by said supply means to an outermost first-set conductor crossing said second-set conductors while giving said one logic value to those two of said second-group distributor output signals which are supplied by said supply means to two adjacent ones of said second-set conductors, the distributor output signals of said one logic value serving as said selection signals.

9. A matrix circuit arrangement as claimed in claim 8, wherein said logic means comprises a first decoder having four first decoder output terminals for supplying respective first decoder output bits and a second decoder having four second decoder output terminals for supplying respective second decoder output bits, each of said first and second decoder output bits being capable of being rendered logic "I" and'logic "0", said logic means further comprising a first logic circuit responsive to the counter output signals except the counter output signal of the most significant digit for making said first decoder successively render said first decoder output bits one at a time in a certain order to be logic "I" and render the other three first decoder output bits each time to be logic "0" during a first half of an interval during which the counter output signal of the most significant digit but one assumes one of said logic values, and successively render said first decoder output bits one at a time in the reverse order to be logic "1" and render the other three first decoder output bits each time to be logic "0" during a second half of said interval, and a second logic circuit supplied with said first decoder output signals and controlled by the counter output signal of the most significant digit but one for supplying said first-group distributor output signals to said first distributor output terminals, said second decoder being responsive to the counter output signals of the most significant digit and the most significant digit but one to successively render, the four second decoder output signals one at a time to be logic "1" and render the other three second decoder output signals each time to be logic "0," said logic means still further comprising a third logic circuit responsive to said first and second decoder output bits for supplying said second-group distributor output signals to said second distributor output terminals.

10. A matrix circuit arrangement substantially as described herein with reference to Figs. 4, 5, 6 and 7, Fig. 8, Fig. 9 or Fig. 10 of the accompanying drawings.