US3466459A - Current steering switch - Google Patents

Description

. Sept. 9, 1969 JAMES E. WEBB 3,466,459 ADMINIsTRAToR OF THE NATIONAL AERONAUTICS AND SPACE ADMINISTRATION CURRENT STEERING SWITCH Filed May 17, 1967 4 Sheets-Sheet 1 LOAD LOAD

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J E INVENTOR. g LAWRENC J. @OTTARELLI 3 w 31/95 ATTORNEYS Sept. 9, 1969 JAMES E. WEBB 3,466,459

. ADMINISTRATOR OF THE NATIONAL AERONAUTICS AND SPACE ADMINISTRATION CURRENT STEERING SWITCH Filed May 17, 1967 4 Sheets-Sheet 2 I *5 4 s I i I l I I FIG. 2 621 I III 841 I I92 I WM (0) as as I3 ML/UUUL/L/ (b) 82 ID 1X (0) es I M 64 1s OUTPUTOFCORE II II II II (e) 94 IIIIIPIIIoFcoIIE l2 .JY (f) I2 CURRENTPULSE IN A {X (g) DIODE 56 0F OORES IIuI ND 88 CURRENT PULSE III j jL/\ f (h) DIODE 56 0F CORES l2a& l2b

INPUTS AT STAGE II T B L UPON QgPEI C ATION IIIIII c c II II E E or 1 o o I o I o l o o o I o I I 0 o o o I I o o l o o o I I o I o o o I o o I o I o o I o o I l o o o I o I o o I o o I o I o I o o I o l o I o I I I o l o l I 0 3:1

I o l I I o o I I I o I I o I 0 1mm l I o o I o I WW I l o o I I 0 mm I I 0 I o o I 1 l I 0 I 0 i 0 (M1) INVENTOR. 5 LAW gs J. ZO'I'TARELLI ATTORNEYS Sept. 9, 1969 JAMES E. WEBB AND SPACE ADMINISTRATION CURRENT STEERING SWITCH 4 Sheets-Sheet 5 Filed May 17, 1967 k FL J 2 3% 3 y K L ifi u: IE

INVENTOR. LAWRENCE J. ZOTTARELLI BY QL Q S-Qfi ATTORNEYS Sept. 9, 1969 JAMES E. WEBB ADMINISTRATOR OF THE NATIONAL AERONAUTICS AND SPACE ADMINISTRATION CURRENT STEERING SWITCH 4 Sheets-Sheet 4 Filed May 17, 1967 ax-wa n. S R

R V mA V m w W H 17W 03 A U E/L M United States Patent Oflice 3,466,459 Patented Sept. 9, 1969 U.S. Cl. 307-88 13 Claims ABSTRACT OF THE DISCLOSURE A multistage current steering switch employing magnetic cores. Each stage includes an output core and a plurality of logic cores. All the output cores are inductively coupled in series by a first activating winding, while all the logic cores are inductively coupled by a second activating winding. Similarly, each output core is inductively coupled in series by a first control winding, with one logic core of each stage, while a second control winding inductively couples each output core to all the logic cores of its respective stage. An activating pulse drives one of the output cores to the magnetic state of the other cores, inducing a current in the first control winding which tends to switch all the logic cores coupled thereto. However, currents in inhibit windings inhibit all but one logic core from switching. That single core is again switched by a current in the second activating winding, inducing a current in the second control winding which causes the output core coupled thereto to be switched.

ORIGIN OF INVENTION The invention described herein was made in the performance of work under a NASA contract and is subject to the provisions of section 305 of the National Aeronautics and Space Act of 1958, Public Law 85-568 (72 Stat. 435; 42 USC 4257).

BACKGROUND OF THE INVENTION Field of the invention This invention relates to electrical switching circuits and, more particularly, to a current switching circuit utilizing magnetic elements.

Description of the prior art Various types of current steering switches are presently known. The basic function of such switches is to produce a current pulse on any one of a plurality of output lines which are adapted to be connected to a plurality of loads. In some switches, the output line in which a current pulse is induced is dependent on a particular combination of activating signals supplied to the switch. Such switches may be defined as of the address type, since a unique combination of signals, constituting an address, must be provided to produce an output current pulse on a particular line. Other current steering switches are of the commutating type, in which current pulses are produced in the output lines in a fixed unalterable sequence, in response to a sequence of activating signals.

A characteristic disadvantage of an address type switch is the need for specific addressing which can become costly and complex, especially as the number of the output lines increases. On the other hand, in the commutating type switch, the fact that output pulses are produced in a fixed sequence of output lines is often undesirable, since it limits the use of such switches only to applications in which a fixed sequence of pulses is useful.

OBJECTS AND SUMMARY .OF THE INVENTION Accordingly, it is an object of the present invention to provide a new current steering switch which overcomes some of the limitations of the prior art.

Another object is to provide a new current steering switch utilizing magnetic elements for producing a controllable sequence of current pulses.

A further object of the invention is the provision of a novel current steering switch which, like commutator type switches, does not require specific addressing, but which unlike commutator type switches, is operable to provide a flexible alterable sequence of current pulses.

Still a further object is to provide a current steering commutator switch which is controllable to provide output current pulses from any desired sequence of output lines.

These and other objects are achieved by providing a current steering switch utilizing magnetic cores, some of which are defined as output cores while others are de fined as sequence controlling cores, also referred to as logic cores. A separate logic core is associated with each output core for each stepping capability. Assuming an n stage switch, i.e. one with n output cores, n logic cores are associated with each output core for a total of n logic cores to provide maximum sequence flexibility. In such a switch, a sequence of output pulses is produced in which each pulse in the sequence may be provided from any one of the n output cores, without specifically addressing each output core.

Briefly, once the switch is activated to provide the first output pulse in the sequence from a selected output core, the next output core to provide an output pulse is selected by the logic cores which are in turn controlled by logic signals in a manner to be described hereafter in detail.

The novel features that are considered characteristic of this invention are set forth with particularity in the appended claims. The invention will best be understood from the following description when read in connection with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS FIGURE 1 is a block diagram of one embodiment of the invention;

FIGURE 2 is a multiline waveshape diagram useful in explaining the embodiment of FIGURE 1;

FIGURE 3 is a block diagram of another embodiment of the invention;

FIGURE 4 is a block diagram of still another embodiment of the invention; and

FIGURE 5 is a truth table useful in explaining the operation of the embodiment shown in FIGURE 4.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference is now made to FIGURE 1 which is a diagram of one specific embodiment of the novel switch of the present invention. The particular embodiment is presented as exemplary only, rather than as a limitation on the teachings disclosed herein. The switch is shown comprising of eight output cores 11 through 18. The cores may be of the well known ferrite type capable of assuming either of two conditions or states of magnetic remanence to which they may individually be driven by an applied magnetomotive force. Such forces are produced by currents in windings which are inductively coupled to the cores. Hereinafter, these two states will be referred to as the set state and reset state.

Each output core is inductively coupled by an activating winding 20 and an output winding 22. The activating windings 20 are connected in series by lead 24, between an activating pulse source 25 and a terminal 26. Each output winding 22 is connected at one end to terminal 26 and at the other end to a diode 28 which is in turn connected to a reference potential, such as ground, through a load 30. Lead 32 may provide such connections. As will be explained hereafter, leads 32 are connected to control windings which are inductively coupled to logic cores associated with their respective output cores.

The output cores may include reset windings (not shown) to drive the cores to a common reset state. Also each of the output cores may be inductively coupled by a set winding (not shown) so that after all the cores are in the reset state, one of the cores may be chosen to be driven to the other or set state.

The arrangement described thus far is known in the art. In one prior art switching circuit, the output cores such as 11 through 18 are driven to a reset state. Thereafter, a signal or pulse is provided by a source such as 25 to drive the cores to their set state. However, by means of additional windings, all but one of the cores are inhibited from changing state. Only the single unhibited core changes to the set state, steering the pulse from source 25 through its respective output winding and, therefrom to the load. Such an arrangement is described in U.S. Patent No. 3,215,993.

Similarly, one of the output cores such as core 11, may be driven by means of a set pulse to the set state after all cores have been driven to the reset state. Thereafter, the pulse from source 25 may be applied to drive all cores to their reset state. Since only core 11 is in a set state, only it will change magnetic state inducing a pulse in the output load coupled thereto. It is the latter type arrangement which forms the known portion of the switch of the present invention.

However, in addition to such known arrangements, the novel switch diagrammed in FIGURE 1 includes two logic cores associated with each of the output cores. The two logic cores are designated by the output core numerical designations, such as 11 followed by the letters a and b, such as 11a and 11b. Logic cores 11a, 12a through 18a may be regarded as a first row of logic cores, while cores 11b, 12b through 18b form a second row of logic cores.

Each core in the first row has an inhibit winding 36, all of which are connected in series between ground and an inhibit pulse source 40. Similarly, each of the cores in the second row has an inhibit winding 42, all of which are serially connected between ground and a second inhibit pulse source 44. Also, the cores in the first and second rows are inductively coupled by activating windings 46, which are connected in series between a terminal 48 and a second activating source 50.

In addition, each output core is inductively coupled by a control winding 52, while its associated logic cores are coupled by an output windings 54. Winding 52 and the two windings 54 are connected in series with one another, and a diode 56 between terminal 48 and ground. A logic core in the first row such as 11a and a logic core in the second row, associated with a succeeding output core, such as 12b are inductively coupled by control windings 58 which are connected in series by means of connection 32, with the output winding 22 of an output core such as core 11.

The arrangement shown in FIGURE 1 may best be described in conjunction with an exemplary cycle of operation, in which it is assumed that all the cores 11 through 18, 11a through 18a and 11b through 18b, are in a reset state. Thereafter, one output core such as core 11 is driven to its set state by a current induced in its set Winding (not shown). Following the setting of core 11, a pulse or signal designated I is provided by source 25, tending to drive cores 11 through 18 to their reset state. Since cores 12 through 18 are already in a reset state, the I pulse does not affect them. However, pulse I does affect core 11 which is in a set state, driving it to the reset state.

The change of state of core 11 from set to reset induces a voltage in the output winding 22, forward biasing diode 28 so that the I pulse is directed to the load 30 associated with core 11, thereby providing the first output current pulse. Also, the current is directed to ground through control windings 58 of 11a and 12b, tending to drive these cores to their set states. Simultaneously with pulse I an inhibit pulse 1 is provided by source 44, or source 40 provides an inhibit pulse I If pulse I is provided, a current flows in inhibit winding 42 of core 12!), which produces a magnetomotive force tending to drive core 12b to its reset state, thereby overcoming the force provided by control winding 58. Consequently, core 12b remains in its reset state and only core 11a switches to its set state. On the other hand, if source 40 supplies pulse I in coincidence with pulse I core 11a is inhibited from switching and only core 12b is switched to the set state. Thus, after pulse I and one of the inhibit pulses are supplied, only one core is in a set state.

Let it be assumed that core 11a is switched and is in the set state. Thereafter, a second activating pulse I is provided by source 50. Its function is to drive, by means of activating windings 46 all the logic cores to their reset states. However, since except for 11a, all the cores are already in such state only core 11a is switched. This induces a voltage in the output winding 54 of 11a, which forward biases diode 56 so that pulse I is steered to ground therethrough. Consequently, current flows in control winding 52 of output core 11, switching it to the set state. Thus, after pulse I all the cores are again in the reset state except output core 11, which is in the set state. As a result, when pulse I is again provided, the output core 11 provides a second successive current pulse to load 30 coupled thereto. Such a performance may be thought of as a repeat stepping function in that two successive output current pulses are provided by the same output core.

If on the other hand, simultaneously with pulse I inhibit pulse I is supplied, core 11a is inhibited from switching and core 12b switches to the set state. Then when pulse I is supplied, a current is induced in the control winding 52 of output core 12, switching that core to the set state. Thus, when a next succeeding pulse I is supplied, output core 12 is switched to the reset state inducing a current in its load 30. Such a performance may be defined as a forward stepping function by one stage since two successive output current pulses are supplied by two successive output cores of the switch, i.e. cores 11 and 12. Thus, the aforedescribed switch is capable of performing two unique stepping functions.

The operation of the switch may best be summarized in conjunction with FIGURE 2 which is a multiline waveform diagram of the current pulses herebefore referred to. Assuming that before time 11 core 11 is set. Then at time t1 when pulse I designated in line a by numeral 62 is supplied, core 11 provides an output pulse 64 (line e). If at the same time an inhibit pulse I designated by numeral 66 is supplied, core 11a (FIGURE 1) is switched. Thus, when an 1;; pulse 68 is supplied at time t2, current flows through diode 56 of core 11a as indicated by pulse 72, switching core 11 to the set state. Consequently, at time t3, when a subsequent I pulse 74 is provided, core 11 again provides an output pulse 76. Thus, core 11 provides two successive output pulses. The same core will continue to be the only one providing output pulses (line e) as long as an inhibit I pulse (line d) is supplied in time coincidence with each 1,, pulse (line a).

If, however, at time t4 an inhibit I pulse 82 is supplied together with an I pulse 84, core 12b is set. Then when the next I pulse 86 is supplied at time 25, core 12b is reset causing current to flow in diode 56 of core 1212 as indicated by pulse 88. This current sets core 12 so that when the next I pulse 92 is supplied at time t6, an output pulse 94 is provided by core 12, by being driven to its reset state. Thus the switch steps forward by one stage.

The switch shown in FIGURE 1 may be summarized as a multistage switch characterized by two stepping functions, which are the repeat and forward stepping by one stage. The capability to perform each function is provided by each one of the rows of logic cores. If cores 11a through 18a were eliminated, the switch would operate as a commutator. Once more than one row of logic cores is provided, means such as sources 40 and 44 need be provided to selectively inhibit all but one of the logic cores from changing state. Sources 40 and 44 as well as sources 25 and '50 are shown in block form. They may comprise any well known circuit capable of applying current pulses. The timing between such pulses is controlled 'by a timing circuit 100 to which the four sources are connected.

' As herebefore indicated, the switch shown i FIG-,

URE l is exemplary of the teachings of the invention. By adding rows of logic cores, the number of stepping functions of the switch may be increased. In an n stage switch, 11 rows of logic cores would provide maximum flexibility in controlling the sequence of output cores providing the output pulses. To describe such capabilities, two additional embodiments are diagrammed in FIGURES 3 and 4 to which reference is made herein.

In FIGURE 3, is diagrammed a 6 stage switch which is operable to perform any one of three stepping functions, including the repeat, forward by one and backward by one step functions. In FIGURE 3, elements similar to those shown in FIGURE 1 are designated by like numerals. In add tion, in FIGURE 3 a row of logic cores 110 through 160 are shown. Their function is to provide the backward stepping capability of the switch. Also since three rows of cores are employed, a third inhibit line in which inhibit pulses I may be induced is diagrammed. Such a line is necessary so that when one of the output cores such as 14 is reset by an I pulse, two out of the three logic cores 14a, 14b and 140 may be inhibited from being set, limiting the setting to only one logic core. Depending on the logic core which is set, either of output cores 13, 14 or 15 will be set when the set logic core is subsequently reset by the I pulses.

Reference is now made to FIGURE 4 in which is a diagram, in mirror notation, of an eight stage steering switch capable of being stepped from any stage to any other. Therein lines (31 through C8 represent the eight output cores. The slanted lines represent windings which are designated by numerals like those utilized in designating identical windings in FIGURES 1 and 3. To provide total flexibility, that is, the capability to step from any one stage to any other stage, eight logic cores are associated with each output core. These are designated by lines Cla through Clh, C2a through C2h and C8a through C8h.

The output windings 22 of cores C1 through C8 are connected to terminals F through M. Each of the logic cores has one control winding 58, with the control windings 58 of eight different logic cores from the eight different groups connected in series with a diode 28 between are of the terminals and ground, as shown in FIGURE 4. In addition, the switch includes six inhibit lines 111 through 116, which are assumed to be connected to inhibit pulse sources (not shown) to provide inhibit pulses 1 T I I I and Three inhibit pulses on different combinations of the lines are supplied simultaneously with each activating I pulse. Also, each of the logic cores is inductively coupled by three inhibit windings 120. Line 111 connects in series the inhibit windings 120 on the first four logic cores of each group of eight cores. Similarly, line 112 connects the inhibit windings 120 on the last four logic cores of each group, line 113 the windings on the first, second, fifth and sixth cores, line 114 the windings on the third, fourth, seventh and eighth, line 115 every odd core and line 116 every even core. The basic function of these inhibit windings and pulses is to control the logic cores so that when a current flows between one of the terminals, FM and ground, only one of the eight cores which may be affected by such current is driven to the set state and the other seven remain in their reset state.

Such a mode of operation may best be described in conjunction with FIGURE 5, which is a truth table of the logic of any stage of the switch of FIGURE 4. In the table N represents any one of the eight stages. In the absence of an 1 pulse, there will be no output upon application of I indicated by a 0. If, however, an 1 pulse is supplied, the stage providing an output after I depends on the combination of three inhibit pulses sup- With I Let N be stage 4, represented by output core C4. Then when I is applied, core C4 is reset causing a current to flow through the control windings 58 between terminal I and ground. The eight cores which may be affected by such current are C1 C2g, C3h, C4a, C5b, C6c, C7d, and CSe, The inhibit pulses determine which of these cores is set. If I E and E are true indicated by 1 only core C4a is not inhibited, so that the current in winding 58 thereof switches it to the set state. Then when I is received, core 041: is reset, steering the 1;; current through control winding 52 of C4, thereby providing the output pulse 1 If, however, 1 I and I are true, as shown on the last line of the table, only logic core C3h is set. Consequently, when I is received, core C3h is reset steering the current I to ground through winding 52 of C3, and thereby providing an output at a stage which is seven stages removed from the prior stage 4, i.e. stage 3 represented by C3.

In FIGURE 4, the loads 30 are deleted. It should be appreciated, however, that such loads may be connected in series with diodes 28 and/ or 56 in which case the output pulses would be produced when an output core is driven by I and/ or I to its reset state.

There has accordingly been shown and described herein a novel current steering switch capable of providing a sequence of current pulses which are provided by a plurality of output stages. Once the switch is adjusted to provide the first pulse from a specific stage, the stage to provide a succeeding pulse is selected by techniques other than specifically addressing the desired stage. A plurality of magnetic cores used as logic elements are inductively coupled so that depending on inhibiting pulses, only a selected logic core is switched to a selected state of magnetization which thereafter affects a desired output core to provide an output pulse. For total flexibility in selecting which of a plurality of output cores is to provide an output pulse in an n stage, switch N logic cores are required, 11 logic cores for each stepping function.

What is claimed is:

1. A current steering switch comprising:

11 magnetic output cores each of said cores having first and second states of magnetic remanence and drivable therebetween, each core having an activating winding, a control winding and an output winding, inductively coupled thereto;

means for serially connecting said activating windings between a first terminal and a second terminaladapted to be connected to a first source of activating pulses;

at least 2n magnetic logic cores each having first and second states of magnetic remanence and drivable therebetween, each logic core having an activating winding, a control winding and an output winding, each logic core associated with a diiferent output core;

means serially connecting the activating windings of said 2n magnetic logic cores between a third terminal and a fourth terminal adapted to be connected to a second source of activating pulses;

means for serially connecting the output winding of each output core with the control winding of a selected logic core between said first terminal and a reference potential, means for serially connectingthe control winding of each output core and the output winding of its associated logic core between said third terminal and said reference potential; and timing control means for controlling the time relationships between activating pulses from said first and second sources, whereby an activating pulse from said first source drives one of the output cores from said first state to said second state in which all other output cores are in, the change in state of said one output core inducing a current in the output winding thereof and the control winding of at least one logic core serially connected therewith to drive said logic core to said first state, said second source subsequently providing an activating pulse to drive said one logic core to said second state inducing a current in the output winding thereof and the control winding of the output core with which it is associated to drive the output core to said first state.

2. The current steering switch as recited in claim 1 including k rows, each of n logic cores, the output winding of each output core being serially connected with the control windings of k logic cores in different rows, each of said k logic cores being associated with different output cores, each output core having k logic cores associated therewith, the control winding of each output core being connected in series with the output windings of the k logic cores associated therewith between said third terminal and said reference potential, each logic core having a plurality of inhibit windings; and

inhibit means coupled to said time control means to provide inhibit currents in selected ones of said inhibit windings in time coincidence with an activating pulse from said first source, whereby only a selected one of the k logic cores coupled to each output core is driven to said first state, said selected one logic core driving the output core associated therewith to said first state when an activating pulse from said second source is applied to the activating winding of said selected one logic core.

3. The steering switch as recited in claim 2 in which at least k is equal to 2 and not greater than n.

4. The steering switch as recited in claim 2 in which k=n, each row of n cores providing said switch with a different stepping function.

5. The steering switch as recited in claim 4 including means for connecting the output winding of each output core in series with the control windings of the first logic core associated therewith, the second logic core associated with a succeeding output core, the third logic core associated with the next succeeding output core and with a succeeding logic core associated with each suceeding output core.

'6. The steering switch as recited in claim 4 in which each logic core is inductively coupled by at least log n inhibit windings.

7. In a current steering switch of the type including n magnetic output cores, each switchable between first and second stable magnetic states, the output cores being inductively coupled to windings whereby an activating pulse from a first activating source drives one of the cores which is in a state opposite to the states of the cores to the same, inducing an output pulse in an output winding of the core driven from one state to the other, the improvement comprising:

at least two rows, each of n logic cores, one logic core from each row associated with an output core, each logic core being inductively coupled by an activating winding, a control winding, an output winding and an inhibit winding; means serially connecting the output winding of an output core with the control windings of at least two logic cores associated with different output cores;

means for selectively inducing inhibit currents in inhibit windings of said logic cores in time coincidence with the activating pulse from said first source, whereby only one of the logic cores with its control winding coupled to the output winding of an output core is driven to a state other than the state of all other logic cores when a current is induced in the output winding of said output core;

means serially connecting the output windings of the logic cores associated with each output core with a control winding thereof; and

a second activating source for providing an activating pulse in the activating windings of said logic cores to drive the logic core which is in a state other than the rest of the logic cores to the same state, the driven logic core inducing a current in the control winding of the output core with which it is associated, to drive said output core to a state opposite to the states of the rest of said output cores.

8. The improvement as recited in claim 7 including n rows of logic cores, each row of n cores, whereby said switch is controllable to provide a sequence of current pulses each pulse being suppliable by any one of said It output cores.

9. In a current steering switch of the type including a plurality of magnetic output cores, each switchable between first and second magnetic states and inductively coupled to a winding in which a current pulse is induced as a function of the change of state of the output core, an arrangement for controlling said switch to possess 11 stepping functions, whereby after an output pulse from one of said output cores said switch is operable to provide a pulse from a select one of said output cores, n not being greater than the number of output cores, the arrangement comprising:

a separate logic core associated with each output core for each stepping function;

first and second sources of activating pulses;

inhibit pulse means;

means serially inductively coupling said output cores with said first source of activating pulses;

means serially inductively coupling said output cores with said second source of activating pulses;

first and second windings for serially coupling groups of logic cores to each output core, the number of logic cores in each group equalling the number of stepping functions;

timing means for controlling said first source of activating pulses and said inhibit pulse means to provide pulses substantially simultaneously, whereby one of said output cores is driven to a first state in which all other output cores are in, inducing a pulse in said first winding to switch one uninhibited logic core to a second state, opposite the first state in which all other logic cores are in, whereby when said second source of activating pulses provides a pulse said one logic core switches back to said first state inducing a pulse in said second winding to switch the output core coupled therewith to said second state, opposite the state in which all other output cores are in.

10. The arrangement as recited in claim 9 wherein said first winding inductively couples a first group of logic cores each associated with a different output core, and said second winding inductively couples a second group of logic cores, all associated with the same output core.

11. The arrangement as recited in claim 10 wherein said first and second groups of logic cores have one common logic core for performing a repeat stepping function, whereby two consecutive current pulses are provided by the same output core.

12. The arrangement as recited in claim 11 wherein said first winding further inductively couples logic cores associated with adjacent output cores, whereby said switch is further capable of performing a step-forward-by-one and step-backward-by-one stepping functions.

13. The arrangement as recited in claim 9 wherein said inhibit pulse means includes n inhibit pulse sources, each inductively coupled to a number of logic cores equal to the number of output cores, 11-1 of said n inhibit pulse sources providing inhibit pulses substantially simultaneously with said first source of activating pulses to inhibit all but one of the logic cores inductively coupled to an output core which is driven by the pulse from said first source.

References Cited UNITED STATES PATENTS 3,047,730 7/1962 Brown 307-88 3,391,285 7/1968 King 30788 3,052,872 9/ 1962 Hanewinkel 340'-174 3,083,354 3/19-63 Hanewinkel 340174 3,127,590 3/1964 Euler 340-174 STANLEY M. URYNOWICZ, 111., Primary Examiner U.S. Cl. X.R. 340l74

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