GB1571492A - Fabrication of solid state devices - Google Patents

Fabrication of solid state devices Download PDF

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Publication number
GB1571492A
GB1571492A GB9614/76A GB961476A GB1571492A GB 1571492 A GB1571492 A GB 1571492A GB 9614/76 A GB9614/76 A GB 9614/76A GB 961476 A GB961476 A GB 961476A GB 1571492 A GB1571492 A GB 1571492A
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Prior art keywords
layer
contact
resist
slice
zone
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GB9614/76A
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UK Secretary of State for Defence
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UK Secretary of State for Defence
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Priority to GB9614/76A priority Critical patent/GB1571492A/en
Publication of GB1571492A publication Critical patent/GB1571492A/en
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/46Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428
    • H01L21/461Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/469Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers
    • H01L21/471Inorganic layers
    • H01L21/473Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/46Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428
    • H01L21/461Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/465Chemical or electrical treatment, e.g. electrolytic etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1828Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof the active layers comprising only AIIBVI compounds, e.g. CdS, ZnS, CdTe
    • H01L31/1832Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof the active layers comprising only AIIBVI compounds, e.g. CdS, ZnS, CdTe comprising ternary compounds, e.g. Hg Cd Te

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electromagnetism (AREA)
  • Light Receiving Elements (AREA)
  • Weting (AREA)

Description

(54) THE FABRICATION OF SOLID STATE DEVICE (71) I, Secretary of State for Defence, London, do hereby declare the invention, for which I pray that a patent may be granted to me, and the method by which it is to be performed, to be particularly described in and by the following statement: The present invention relates to the fabrication of solid state electronic devices, particularly semiconductors photodectors.
During the fabrication of solid state devices it is conventional to etch selective surface regions of the device being processed. For example, the surface regions may be those of a substrate, a semiconductor layer, or a metal contact layer. This etching is carried out in the following conventionl way. A layer of material known as resist is deposited on the appropriate surface. A mask is placed above the resist layer and the resist layer is exposed through the mask to radiation,eg ultra-violet radiation or an electron beam. The exposed areas either become soluble or insoluble in a particular solvent compared with the unexposesd areas depending on whether the resist is a socalled 'positive' or 'negative' material. The soluble areas only are removed by the solvent exposing selective areas of the underlying surface. The underlying surface is then etched to remove part of its material.
For example, in the fabrication of semiconductor photo detectors, particularly of the photovoltaic kind, it is necessary to etch regions chemically in a compound or alloy semiconductor material whose width and depth are defined as accurately as possible.
It is conventional to apply the chemical etchant directly to the semiconductor material. Unfortunately with conventional etchants it is difficult to control the edgedefinition of the etched regions and their depths to an accuracy better than a few thousand Angstroms. Also, conventional etchants for photodetector materials are organic liquids containing halogens, eg 5% bromine in methanol, and are very unsatisfactory since the halogen may contaminate unetched parts of the material being processed. Lengthy methods have been devised for subsequently removing bromine from the material being processed.
According to the present invention a method of fabricating a solid state electronic device which has a region of compound semiconductor material includes the steps of forming by anodisation an oxidised layer in a surface of the region by making the surface, or a part thereof, the anide of an electrolytic cell, and removing the oxidised layer by a halogen-free chemical etchant.
The term 'solid state' device is intended to include not only all-solid devices but also devices which are not all-solid but which have some solid parts similar to all-solid devices, e.g. liquid crystal device substrates.
The oxidation and removal steps may be repeated in a sequential fashion to remove material accurately to a predetermined thickness.
The oxidation and removal steps may be applied to parts only of the said surface and these parts may be pre-defined by exposure through a layer of resist patterned accordingly (in a conventional way).
If necessary the regions of the surface where compound semiconductor material has been removed may be filled again with another material, e.g. by sputtering with a dialectric such as silicon dioxide, make these regions coplanar with the unetched regions.
The dielectric may also serve as a surface passivation layer.
The method according to the invention is particularly suitable for the selective removal of the photodetector materials cadmium mercury telluride (known as CMT) and lead telluride (known in the art as LTT).
The method allows such removal to be carried out more accurately and with less contamination than with conventional etchants applied directly. For these materials electrolytic oxidation may be performed using, for example, sodium hydrogen carbonate solution or sodium hydroxide solution, or potassium dichromate solution as electrolyte. Also the chemical etchant used may be, for example, formic or acetic acid.
Electrolysis is known in the prior art as an accurate way of removing solid material from a surface to a predetermined thickness. The material forms an electrolytic anode for this purpose. Accurate etching of materials such as CMT and LTT in this way would not be possible however, since the different elements present in the material would be affected differently by such electrolysis. However by choosing an electrolyte which permits an oxide layer to form on the anode without continuously dissolving the layer, and subsequently removing the layer by etching (according to one form of the invention noted above) it is possible to take advantage of the accuracy of electrolysis without experiencing difficulties arising from the composition of materials such as CMT and LTT.
As an example of the method according to the present invention the fabrication of a CMT photovoltaic infra-red detector will not be described with reference to the accompanying drawings, in which: Figures 1 to 9 are cross-sectional diagrams of the detector during its various fabrication stages: and Figure 10 is a circuit diagram, partly in cross-section, of an electrolytic arrangement used during the fabrication.
As shown in Figure 1 a polished p-type slice 1 of CMT typically 200 Fm thick with a carrier concentration of about 1016 cm3 has an n-type layer 3 formed on its surface by ion implantation. e.g. using A13+ ions. The n-type layer 3 is typically 2000 A thick with a carrier concentration typically in the range 1016 to 10l8 cam~3. A layer 5 of positive photoresist material, e.g. Shipley AZ 1350H, is deposited on the n-type layer 3 to a thickness of about 5000 A as shown in Figure 2.
A mask 7 is then placed on the resist layer 5. The mask 7 has regions 7a and 7b which are respectively opaque and transparent to ultra-violet radiation. As shown in Figure 3 the parts of the resist layer 5 beneath the regions 7b are exposed to ultra-violet radiation and are consequently polymerised and rendered soluble, e.g. in sodium hydroxide solution. The part of the layer 5 beneath the opaque region 7a of the mask is unaffected.
After removal of the mask 7 the soluble parts of the layer 5 are dissolved to leave an island 5a of the resist material, as shown in Figure 4.
The slice 1 together with its n-type layer 3 and island 5a is next mounted on a sapphire support 9 and forms the anode of an electrolytic cell as shown in Figure 10. The support 9 is placed in a vessel 11 containing an oxidising electrolyte solution 13, e.g.
sodium hydrogen carbonate or sodium hydroxide or potassium dichromate, so that the slice 1 is immersed in the solution 13. A fine wire 15, e.g. of tungsten, connects the slice 1 to a contact land 17. The cathode of the electrolytic cell consists of a piece of platinum foil 19. An electric current generator 22 consisting of a battery 21, a switch 23 and an adjustable resistor 24 is connected between the contacts 1 and 17 and the foil 19.
When current is passed through the electrolyte solution 13, the parts of the layer 3 not covered by the resist island 5a (Figure 4) are oxidised to form an oxide coating 25 as shown in Figure 5.
The thickness of the oxide coating 25 is greater than the particular thickness of CMT in the n-type layer 3 which becomes oxidised since the oxide formed from CMT has a larger crystal lattice structure than that of CMT itself.
Preferably about sooA of the n-type layer 3 is oxidised to form the coating 25. The exact thickness oxidised depends on the particular electrolyte and voltage used and for short periods of time, on the length of time for which the electrolysis takes place at a specific temperature.
For example, approximately 560 A of CMT is oxidised in a 0.001M sodium hydroxide solution at 15 violts d.c. and an electrolyte temperature of 25"C.
Similar results have been obtained using a 0.5 M solution of sodium hydrogen carbonate. Electrolysis may also be facilitated by application of a small a.c. ripple. In this case with a 1% a.c. ripple a lower d.c. voltage, typically 10 volts, has been used. It has also been found that in these circumstances the oxide layer is then more easily removed by the subsequent treatment.
Since the oxide coating 25 is an insulator the rate of its formation falls quickly towards zero and this fall accurately limits the thickness of the coating 25. However, the electrolysis may alternatively be stopped after a predetermined time interval to control the thickness of the coating 25.
When the oxide coating 25 has been formed to the required thickness the current is switched off and the slice 1 is transferred to an etchant bath, e.g. of 25% formic acid, typically for a few seconds to remove the oxide coating 25. The etchant does not significantly affect the resist island 5a of the unoxidised CMT beneath the coating 25.
The exposed parts of the n-type layer 3 are then oxidised again by the electrolytic process described above and the consequential oxide coating is again removed by etching. Several more alternate oxidation and etching steps are carried out until about 6,000 A of CMT material has been removed from both the n-type layer 3 and the slice 1 in their exposed parts. A mesa which includes an n-type zone 3a carrying the resist island 5a is left standing proud of the p-type slice 1 as shown in Figure 6.
The depth of the mesa can be controlled with an accuracy better than 100 A and the mesa has edges with a well defined slope of about 3() to the normal to the mesa.
Preferably the oxide coating produced in the final oxidation step, viz. a coating 27a is left unetched as shown in Figure 6. This coating 27a provides the base of a thicker oxide layer 27 shown in Figure 7 which may be built up by sputtering, e.g. using SiO2, and which has an outer surface made to be coplanar with that of the n-type zone 3a.
The oxide layer 27 provides an insulator, i.e. passivating or protective cover, for the p-n junction between the n-type zone 3a and the p-type slice 1.
After production of the layer 27 the resist island 5a is removed, e.g. using acetone.
Next. a further resist layer 21) is deposited on the oxide layer 27 and the n-type zone 3a. The resist layer 2') is selectively etched in the same wav as described with reference to Figure 3 above to produce a window 31 in the resist layer 35) which, as shown in Figure 8, exposes part of the zone 3a and an adjacent part of the oxide layer 29. Metal, e.g. gold. is then evaporated on the surface of the resist layer 29 and fills the window 31.
The resist layer 29. together with the metal on top of it. is then removed, e.g. using acetone. leaving a metal contact 33 on the oxide layer '7 and the zone 3a in the position of the window 31. As shown in Figure 9 a further contact 35, e.g. a continuous layer of gold. is evaporated on the underside of the slice 1. External connections to the contact 33. 35 may be made in a conventional wav.
The photodetector is then ready for use.
It detects infra-red radiation having a photon energy greater than the average band gap of the CMT material at the p-n junction between the n-type zone 3a and the p-type slice 1. When such radiation reaches this p-n junction its photons induce an electromotive force (emf) between the contacts 33 and 35 according to well known semiconductor photo-absorption theory.
This emf may be amplified by an amplifier (not shown).
In an alternative embodiment of the invention the contacts 33. 35 may be pro vided at an earlier stage in the fabrication.
In a further alternative embodiment of the invention the contact 33 may be re placed by a contact which is transparent to infra-red radiation. e.g. made of tin oxide.
Such a contact may cover the entire zone 3a (as well as part of the oxide layer 27).
The slice 1 may have an array of photodetector elements similar to that shown in Figure 9, all formed on different regions (not shown) on its surface. In this case the fabrication steps described with reference to Figures 1 to 10 are applied as common steps for the simultaneous formation of the elements. The contact 35 is a common contact to all of the elements.
WHAT I CLAIM IS 1. A method of fabricating a solid state electronic device having a region of compound semiconductor material, including the steps of forming by anodisation an oxidised layer in the surface of the region by making the surface, or a part thereof the anode of an electric cell and removing the oxidised layer using a suitable halogen free chemical etchant.
2. A method as claimed in claim 1 wherein the electrolytic cell includes sodium hydrogen carbonate solution as electrolyte.
3. A method as claimed in claim 1 wherein the electrolytic cell includes sodium hydroxide solution as electrolyte.
4. A method as claimed in claim 1 wherein the electrolytic cell includes potassium dichromate solution as electrolyte.
5. A method as claimed in any one of the preceding claims wherein the steps are applied to parts only of the surface, the parts being pre-defined by exposure through a layer of patterned resist.
6. A method as claimed in any one of the preceding claims wherein the etchant is formic acid.
7. A method as claimed in any one of the claims, claim 1 to 5, wherein the etchant is acetic acid.
8. A method as claimed in any one of the preceding claims wherein the compound semiconductor material is Cadmium Mercury Telluride.
9. A method as claimed in any one of the claims, claim 1 to 7, wherein the compound semiconductor material is Lead Tin I'elluride.
10. A method of fabricating a solid state device performed substantially as hereinbefore described with reference to the accompanying drawings.
11. A solid state device fabricated by any method claimed in the preceding claims.
12. A photo-voltaic infra-red detector fabricated by any method claimed in claims 1 to 10.
13. A planar array of photo-detector elements fabricated from a substrate of compound semiconductor material wherein each element is simultaneously fabricated in different regions of the substrate according to any method claimed in claims 1 to 10.
**WARNING** end of DESC field may overlap start of CLMS **.

Claims (13)

**WARNING** start of CLMS field may overlap end of DESC **. etching. Several more alternate oxidation and etching steps are carried out until about 6,000 A of CMT material has been removed from both the n-type layer 3 and the slice 1 in their exposed parts. A mesa which includes an n-type zone 3a carrying the resist island 5a is left standing proud of the p-type slice 1 as shown in Figure 6. The depth of the mesa can be controlled with an accuracy better than 100 A and the mesa has edges with a well defined slope of about 3() to the normal to the mesa. Preferably the oxide coating produced in the final oxidation step, viz. a coating 27a is left unetched as shown in Figure 6. This coating 27a provides the base of a thicker oxide layer 27 shown in Figure 7 which may be built up by sputtering, e.g. using SiO2, and which has an outer surface made to be coplanar with that of the n-type zone 3a. The oxide layer 27 provides an insulator, i.e. passivating or protective cover, for the p-n junction between the n-type zone 3a and the p-type slice 1. After production of the layer 27 the resist island 5a is removed, e.g. using acetone. Next. a further resist layer 21) is deposited on the oxide layer 27 and the n-type zone 3a. The resist layer 2') is selectively etched in the same wav as described with reference to Figure 3 above to produce a window 31 in the resist layer 35) which, as shown in Figure 8, exposes part of the zone 3a and an adjacent part of the oxide layer 29. Metal, e.g. gold. is then evaporated on the surface of the resist layer 29 and fills the window 31. The resist layer 29. together with the metal on top of it. is then removed, e.g. using acetone. leaving a metal contact 33 on the oxide layer '7 and the zone 3a in the position of the window 31. As shown in Figure 9 a further contact 35, e.g. a continuous layer of gold. is evaporated on the underside of the slice 1. External connections to the contact 33. 35 may be made in a conventional wav. The photodetector is then ready for use. It detects infra-red radiation having a photon energy greater than the average band gap of the CMT material at the p-n junction between the n-type zone 3a and the p-type slice 1. When such radiation reaches this p-n junction its photons induce an electromotive force (emf) between the contacts 33 and 35 according to well known semiconductor photo-absorption theory. This emf may be amplified by an amplifier (not shown). In an alternative embodiment of the invention the contacts 33. 35 may be pro vided at an earlier stage in the fabrication. In a further alternative embodiment of the invention the contact 33 may be re placed by a contact which is transparent to infra-red radiation. e.g. made of tin oxide. Such a contact may cover the entire zone 3a (as well as part of the oxide layer 27). The slice 1 may have an array of photodetector elements similar to that shown in Figure 9, all formed on different regions (not shown) on its surface. In this case the fabrication steps described with reference to Figures 1 to 10 are applied as common steps for the simultaneous formation of the elements. The contact 35 is a common contact to all of the elements. WHAT I CLAIM IS
1. A method of fabricating a solid state electronic device having a region of compound semiconductor material, including the steps of forming by anodisation an oxidised layer in the surface of the region by making the surface, or a part thereof the anode of an electric cell and removing the oxidised layer using a suitable halogen free chemical etchant.
2. A method as claimed in claim 1 wherein the electrolytic cell includes sodium hydrogen carbonate solution as electrolyte.
3. A method as claimed in claim 1 wherein the electrolytic cell includes sodium hydroxide solution as electrolyte.
4. A method as claimed in claim 1 wherein the electrolytic cell includes potassium dichromate solution as electrolyte.
5. A method as claimed in any one of the preceding claims wherein the steps are applied to parts only of the surface, the parts being pre-defined by exposure through a layer of patterned resist.
6. A method as claimed in any one of the preceding claims wherein the etchant is formic acid.
7. A method as claimed in any one of the claims, claim 1 to 5, wherein the etchant is acetic acid.
8. A method as claimed in any one of the preceding claims wherein the compound semiconductor material is Cadmium Mercury Telluride.
9. A method as claimed in any one of the claims, claim 1 to 7, wherein the compound semiconductor material is Lead Tin I'elluride.
10. A method of fabricating a solid state device performed substantially as hereinbefore described with reference to the accompanying drawings.
11. A solid state device fabricated by any method claimed in the preceding claims.
12. A photo-voltaic infra-red detector fabricated by any method claimed in claims 1 to 10.
13. A planar array of photo-detector elements fabricated from a substrate of compound semiconductor material wherein each element is simultaneously fabricated in different regions of the substrate according to any method claimed in claims 1 to 10.
GB9614/76A 1977-03-04 1977-03-04 Fabrication of solid state devices Expired GB1571492A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2151296A (en) * 1983-10-27 1985-07-17 Davies Design Projects Limited Cabinet assemblies
GB2261677A (en) * 1991-11-22 1993-05-26 Univ Southampton Electrolytic method and cell for etching semiconductors

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2151296A (en) * 1983-10-27 1985-07-17 Davies Design Projects Limited Cabinet assemblies
GB2261677A (en) * 1991-11-22 1993-05-26 Univ Southampton Electrolytic method and cell for etching semiconductors
GB2261677B (en) * 1991-11-22 1996-03-27 Univ Southampton Method and cell for etching semiconductors

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